1 // Initialize PCI devices (on emulators)
3 // Copyright (C) 2008 Kevin O'Connor <kevin@koconnor.net>
4 // Copyright (C) 2006 Fabrice Bellard
6 // This file may be distributed under the terms of the GNU LGPLv3 license.
8 #include "util.h" // dprintf
9 #include "pci.h" // pci_config_readl
10 #include "biosvar.h" // GET_EBDA
11 #include "pci_ids.h" // PCI_VENDOR_ID_INTEL
12 #include "pci_regs.h" // PCI_COMMAND
13 #include "xen.h" // usingXen
15 #define PCI_ROM_SLOT 6
16 #define PCI_NUM_REGIONS 7
18 static void pci_bios_init_device_in_bus(int bus);
20 static struct pci_region pci_bios_io_region;
21 static struct pci_region pci_bios_mem_region;
22 static struct pci_region pci_bios_prefmem_region;
24 /* host irqs corresponding to PCI irqs A-D */
25 const u8 pci_irqs[4] = {
29 static u32 pci_bar(u16 bdf, int region_num)
31 if (region_num != PCI_ROM_SLOT) {
32 return PCI_BASE_ADDRESS_0 + region_num * 4;
35 #define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
36 u8 type = pci_config_readb(bdf, PCI_HEADER_TYPE);
37 type &= ~PCI_HEADER_TYPE_MULTI_FUNCTION;
38 return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS;
41 static void pci_set_io_region_addr(u16 bdf, int region_num, u32 addr)
45 ofs = pci_bar(bdf, region_num);
47 pci_config_writel(bdf, ofs, addr);
48 dprintf(1, "region %d: 0x%08x\n", region_num, addr);
56 static int pci_bios_allocate_region(u16 bdf, int region_num)
59 u32 ofs = pci_bar(bdf, region_num);
61 u32 old = pci_config_readl(bdf, ofs);
63 if (region_num == PCI_ROM_SLOT) {
64 mask = PCI_ROM_ADDRESS_MASK;
65 pci_config_writel(bdf, ofs, mask);
67 if (old & PCI_BASE_ADDRESS_SPACE_IO)
68 mask = PCI_BASE_ADDRESS_IO_MASK;
70 mask = PCI_BASE_ADDRESS_MEM_MASK;
71 pci_config_writel(bdf, ofs, ~0);
73 u32 val = pci_config_readl(bdf, ofs);
74 pci_config_writel(bdf, ofs, old);
76 u32 size = (~(val & mask)) + 1;
80 if (val & PCI_BASE_ADDRESS_SPACE_IO) {
81 r = &pci_bios_io_region;
84 } else if ((val & PCI_BASE_ADDRESS_MEM_PREFETCH) &&
85 /* keep behaviour on bus = 0 */
86 pci_bdf_to_bus(bdf) != 0 &&
87 /* If pci_bios_prefmem_addr == 0, keep old behaviour */
88 pci_region_addr(&pci_bios_prefmem_region) != 0) {
89 r = &pci_bios_prefmem_region;
91 msg = "decrease BUILD_PCIMEM_SIZE and recompile. size %x";
93 r = &pci_bios_mem_region;
95 msg = "increase BUILD_PCIMEM_SIZE and recompile.";
97 u32 addr = pci_region_alloc(r, size);
99 pci_set_io_region_addr(bdf, region_num, addr);
103 "%s region of (bdf 0x%x bar %d) can't be mapped. "
105 type, bdf, region_num, msg, pci_region_size(r));
109 int is_64bit = !(val & PCI_BASE_ADDRESS_SPACE_IO) &&
110 (val & PCI_BASE_ADDRESS_MEM_TYPE_MASK) == PCI_BASE_ADDRESS_MEM_TYPE_64;
111 if (is_64bit && size > 0) {
112 pci_config_writel(bdf, ofs + 4, 0);
117 static void pci_bios_allocate_regions(u16 bdf, void *arg)
120 for (i = 0; i < PCI_NUM_REGIONS; i++) {
121 int is_64bit = pci_bios_allocate_region(bdf, i);
128 /* return the global irq number corresponding to a given device irq
129 pin. We could also use the bus number to have a more precise
131 static int pci_slot_get_pirq(u16 bdf, int irq_num)
133 int slot_addend = pci_bdf_to_dev(bdf) - 1;
134 return (irq_num + slot_addend) & 3;
137 /* PIIX3/PIIX4 PCI to ISA bridge */
138 static void piix_isa_bridge_init(u16 bdf, void *arg)
145 for (i = 0; i < 4; i++) {
147 /* set to trigger level */
148 elcr[irq >> 3] |= (1 << (irq & 7));
149 /* activate irq remapping in PIIX */
150 pci_config_writeb(bdf, 0x60 + i, irq);
152 outb(elcr[0], 0x4d0);
153 outb(elcr[1], 0x4d1);
154 dprintf(1, "PIIX3/PIIX4 init: elcr=%02x %02x\n", elcr[0], elcr[1]);
157 static const struct pci_device_id pci_isa_bridge_tbl[] = {
158 /* PIIX3/PIIX4 PCI to ISA bridge */
159 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0,
160 piix_isa_bridge_init),
161 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_0,
162 piix_isa_bridge_init),
167 #define PCI_IO_ALIGN 4096
168 #define PCI_IO_SHIFT 8
169 #define PCI_MEMORY_ALIGN (1UL << 20)
170 #define PCI_MEMORY_SHIFT 16
171 #define PCI_PREF_MEMORY_ALIGN (1UL << 20)
172 #define PCI_PREF_MEMORY_SHIFT 16
174 static void pci_bios_init_device_bridge(u16 bdf, void *arg)
176 pci_bios_allocate_region(bdf, 0);
177 pci_bios_allocate_region(bdf, 1);
178 pci_bios_allocate_region(bdf, PCI_ROM_SLOT);
180 u32 io_old = pci_region_addr(&pci_bios_io_region);
181 u32 mem_old = pci_region_addr(&pci_bios_mem_region);
182 u32 prefmem_old = pci_region_addr(&pci_bios_prefmem_region);
184 /* IO BASE is assumed to be 16 bit */
185 if (pci_region_align(&pci_bios_io_region, PCI_IO_ALIGN) == 0) {
186 pci_region_disable(&pci_bios_io_region);
188 if (pci_region_align(&pci_bios_mem_region, PCI_MEMORY_ALIGN) == 0) {
189 pci_region_disable(&pci_bios_mem_region);
191 if (pci_region_align(&pci_bios_prefmem_region,
192 PCI_PREF_MEMORY_ALIGN) == 0) {
193 pci_region_disable(&pci_bios_prefmem_region);
196 u32 io_base = pci_region_addr(&pci_bios_io_region);
197 u32 mem_base = pci_region_addr(&pci_bios_mem_region);
198 u32 prefmem_base = pci_region_addr(&pci_bios_prefmem_region);
200 u8 secbus = pci_config_readb(bdf, PCI_SECONDARY_BUS);
202 pci_bios_init_device_in_bus(secbus);
205 u32 io_end = pci_region_align(&pci_bios_io_region, PCI_IO_ALIGN);
207 pci_region_revert(&pci_bios_io_region, io_old);
211 pci_config_writeb(bdf, PCI_IO_BASE, io_base >> PCI_IO_SHIFT);
212 pci_config_writew(bdf, PCI_IO_BASE_UPPER16, 0);
213 pci_config_writeb(bdf, PCI_IO_LIMIT, (io_end - 1) >> PCI_IO_SHIFT);
214 pci_config_writew(bdf, PCI_IO_LIMIT_UPPER16, 0);
216 u32 mem_end = pci_region_align(&pci_bios_mem_region, PCI_MEMORY_ALIGN);
218 pci_region_revert(&pci_bios_mem_region, mem_old);
219 mem_base = 0xffffffff;
222 pci_config_writew(bdf, PCI_MEMORY_BASE, mem_base >> PCI_MEMORY_SHIFT);
223 pci_config_writew(bdf, PCI_MEMORY_LIMIT, (mem_end -1) >> PCI_MEMORY_SHIFT);
225 u32 prefmem_end = pci_region_align(&pci_bios_prefmem_region,
226 PCI_PREF_MEMORY_ALIGN);
227 if (prefmem_end == 0) {
228 pci_region_revert(&pci_bios_prefmem_region, prefmem_old);
229 prefmem_base = 0xffffffff;
232 pci_config_writew(bdf, PCI_PREF_MEMORY_BASE,
233 prefmem_base >> PCI_PREF_MEMORY_SHIFT);
234 pci_config_writew(bdf, PCI_PREF_MEMORY_LIMIT,
235 (prefmem_end - 1) >> PCI_PREF_MEMORY_SHIFT);
236 pci_config_writel(bdf, PCI_PREF_BASE_UPPER32, 0);
237 pci_config_writel(bdf, PCI_PREF_LIMIT_UPPER32, 0);
239 dprintf(1, "PCI: br io = [0x%x, 0x%x)\n", io_base, io_end);
240 dprintf(1, "PCI: br mem = [0x%x, 0x%x)\n", mem_base, mem_end);
241 dprintf(1, "PCI: br pref = [0x%x, 0x%x)\n", prefmem_base, prefmem_end);
243 u16 cmd = pci_config_readw(bdf, PCI_COMMAND);
244 cmd &= ~PCI_COMMAND_IO;
245 if (io_end > io_base) {
246 cmd |= PCI_COMMAND_IO;
248 cmd &= ~PCI_COMMAND_MEMORY;
249 if (mem_end > mem_base || prefmem_end > prefmem_base) {
250 cmd |= PCI_COMMAND_MEMORY;
252 cmd |= PCI_COMMAND_MASTER;
253 pci_config_writew(bdf, PCI_COMMAND, cmd);
255 pci_config_maskw(bdf, PCI_BRIDGE_CONTROL, 0, PCI_BRIDGE_CTL_SERR);
258 static void storage_ide_init(u16 bdf, void *arg)
260 /* IDE: we map it as in ISA mode */
261 pci_set_io_region_addr(bdf, 0, PORT_ATA1_CMD_BASE);
262 pci_set_io_region_addr(bdf, 1, PORT_ATA1_CTRL_BASE);
263 pci_set_io_region_addr(bdf, 2, PORT_ATA2_CMD_BASE);
264 pci_set_io_region_addr(bdf, 3, PORT_ATA2_CTRL_BASE);
267 /* PIIX3/PIIX4 IDE */
268 static void piix_ide_init(u16 bdf, void *arg)
270 pci_config_writew(bdf, 0x40, 0x8000); // enable IDE0
271 pci_config_writew(bdf, 0x42, 0x8000); // enable IDE1
272 pci_bios_allocate_regions(bdf, NULL);
275 static void pic_ibm_init(u16 bdf, void *arg)
277 /* PIC, IBM, MPIC & MPIC2 */
278 pci_set_io_region_addr(bdf, 0, 0x80800000 + 0x00040000);
281 static void apple_macio_init(u16 bdf, void *arg)
284 pci_set_io_region_addr(bdf, 0, 0x80800000);
287 static const struct pci_device_id pci_class_tbl[] = {
289 PCI_DEVICE_CLASS(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_1,
290 PCI_CLASS_STORAGE_IDE, piix_ide_init),
291 PCI_DEVICE_CLASS(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB,
292 PCI_CLASS_STORAGE_IDE, piix_ide_init),
293 PCI_DEVICE_CLASS(PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE,
296 /* PIC, IBM, MIPC & MPIC2 */
297 PCI_DEVICE_CLASS(PCI_VENDOR_ID_IBM, 0x0046, PCI_CLASS_SYSTEM_PIC,
299 PCI_DEVICE_CLASS(PCI_VENDOR_ID_IBM, 0xFFFF, PCI_CLASS_SYSTEM_PIC,
303 PCI_DEVICE_CLASS(PCI_VENDOR_ID_APPLE, 0x0017, 0xff00, apple_macio_init),
304 PCI_DEVICE_CLASS(PCI_VENDOR_ID_APPLE, 0x0022, 0xff00, apple_macio_init),
307 PCI_DEVICE_CLASS(PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_BRIDGE_PCI,
308 pci_bios_init_device_bridge),
311 PCI_DEVICE(PCI_ANY_ID, PCI_ANY_ID, pci_bios_allocate_regions),
316 /* PIIX4 Power Management device (for ACPI) */
317 static void piix4_pm_init(u16 bdf, void *arg)
319 // acpi sci is hardwired to 9
320 pci_config_writeb(bdf, PCI_INTERRUPT_LINE, 9);
322 pci_config_writel(bdf, 0x40, PORT_ACPI_PM_BASE | 1);
323 pci_config_writeb(bdf, 0x80, 0x01); /* enable PM io space */
324 pci_config_writel(bdf, 0x90, PORT_SMB_BASE | 1);
325 pci_config_writeb(bdf, 0xd2, 0x09); /* enable SMBus io space */
328 static const struct pci_device_id pci_device_tbl[] = {
329 /* PIIX4 Power Management device (for ACPI) */
330 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3,
336 static void pci_bios_init_device(u16 bdf)
338 int pin, pic_irq, vendor_id, device_id;
340 vendor_id = pci_config_readw(bdf, PCI_VENDOR_ID);
341 device_id = pci_config_readw(bdf, PCI_DEVICE_ID);
342 dprintf(1, "PCI: bus=%d devfn=0x%02x: vendor_id=0x%04x device_id=0x%04x\n"
343 , pci_bdf_to_bus(bdf), pci_bdf_to_devfn(bdf), vendor_id, device_id);
344 pci_init_device(pci_class_tbl, bdf, NULL);
346 /* enable memory mappings */
347 pci_config_maskw(bdf, PCI_COMMAND, 0, PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
349 /* map the interrupt */
350 pin = pci_config_readb(bdf, PCI_INTERRUPT_PIN);
352 pin = pci_slot_get_pirq(bdf, pin - 1);
353 pic_irq = pci_irqs[pin];
354 pci_config_writeb(bdf, PCI_INTERRUPT_LINE, pic_irq);
357 pci_init_device(pci_device_tbl, bdf, NULL);
360 static void pci_bios_init_device_in_bus(int bus)
363 foreachbdf_in_bus(bdf, max, bus) {
364 pci_bios_init_device(bdf);
369 pci_bios_init_bus_rec(int bus, u8 *pci_bus)
374 dprintf(1, "PCI: %s bus = 0x%x\n", __func__, bus);
376 /* prevent accidental access to unintended devices */
377 foreachbdf_in_bus(bdf, max, bus) {
378 class = pci_config_readw(bdf, PCI_CLASS_DEVICE);
379 if (class == PCI_CLASS_BRIDGE_PCI) {
380 pci_config_writeb(bdf, PCI_SECONDARY_BUS, 255);
381 pci_config_writeb(bdf, PCI_SUBORDINATE_BUS, 0);
385 foreachbdf_in_bus(bdf, max, bus) {
386 class = pci_config_readw(bdf, PCI_CLASS_DEVICE);
387 if (class != PCI_CLASS_BRIDGE_PCI) {
390 dprintf(1, "PCI: %s bdf = 0x%x\n", __func__, bdf);
392 u8 pribus = pci_config_readb(bdf, PCI_PRIMARY_BUS);
394 dprintf(1, "PCI: primary bus = 0x%x -> 0x%x\n", pribus, bus);
395 pci_config_writeb(bdf, PCI_PRIMARY_BUS, bus);
397 dprintf(1, "PCI: primary bus = 0x%x\n", pribus);
400 u8 secbus = pci_config_readb(bdf, PCI_SECONDARY_BUS);
402 if (*pci_bus != secbus) {
403 dprintf(1, "PCI: secondary bus = 0x%x -> 0x%x\n",
406 pci_config_writeb(bdf, PCI_SECONDARY_BUS, secbus);
408 dprintf(1, "PCI: secondary bus = 0x%x\n", secbus);
411 /* set to max for access to all subordinate buses.
412 later set it to accurate value */
413 u8 subbus = pci_config_readb(bdf, PCI_SUBORDINATE_BUS);
414 pci_config_writeb(bdf, PCI_SUBORDINATE_BUS, 255);
416 pci_bios_init_bus_rec(secbus, pci_bus);
418 if (subbus != *pci_bus) {
419 dprintf(1, "PCI: subordinate bus = 0x%x -> 0x%x\n",
423 dprintf(1, "PCI: subordinate bus = 0x%x\n", subbus);
425 pci_config_writeb(bdf, PCI_SUBORDINATE_BUS, subbus);
430 pci_bios_init_bus(void)
433 pci_bios_init_bus_rec(0 /* host bus */, &pci_bus);
439 if (CONFIG_COREBOOT || usingXen())
440 // Already done by coreboot or Xen.
443 dprintf(3, "pci setup\n");
445 pci_region_init(&pci_bios_io_region, 0xc000, 64 * 1024 - 1);
446 pci_region_init(&pci_bios_mem_region,
447 BUILD_PCIMEM_START, BUILD_PCIMEM_END - 1);
448 pci_region_init(&pci_bios_prefmem_region,
449 BUILD_PCIPREFMEM_START, BUILD_PCIPREFMEM_END - 1);
454 foreachbdf(bdf, max) {
455 pci_init_device(pci_isa_bridge_tbl, bdf, NULL);
457 pci_bios_init_device_in_bus(0 /* host bus */);