1 // Initialize PCI devices (on emulators)
3 // Copyright (C) 2008 Kevin O'Connor <kevin@koconnor.net>
4 // Copyright (C) 2006 Fabrice Bellard
6 // This file may be distributed under the terms of the GNU GPLv3 license.
8 #include "util.h" // dprintf
9 #include "pci.h" // PCIDevice
10 #include "biosvar.h" // GET_EBDA
11 #include "pci_ids.h" // PCI_VENDOR_ID_INTEL
12 #include "pci_regs.h" // PCI_COMMAND
14 #define PCI_ADDRESS_SPACE_MEM 0x00
15 #define PCI_ADDRESS_SPACE_IO 0x01
16 #define PCI_ADDRESS_SPACE_MEM_PREFETCH 0x08
18 #define PCI_ROM_SLOT 6
19 #define PCI_NUM_REGIONS 7
21 static u32 pci_bios_io_addr;
22 static u32 pci_bios_mem_addr;
23 static u32 pci_bios_bigmem_addr;
24 /* host irqs corresponding to PCI irqs A-D */
25 static u8 pci_irqs[4] = { 11, 9, 11, 9 };
27 static void pci_set_io_region_addr(PCIDevice d, int region_num, u32 addr)
32 if ( region_num == PCI_ROM_SLOT ) {
35 ofs = 0x10 + region_num * 4;
38 old_addr = pci_config_readl(d, ofs);
40 pci_config_writel(d, ofs, addr);
41 dprintf(1, "region %d: 0x%08x\n", region_num, addr);
43 /* enable memory mappings */
44 cmd = pci_config_readw(d, PCI_COMMAND);
45 if ( region_num == PCI_ROM_SLOT )
47 else if (old_addr & PCI_ADDRESS_SPACE_IO)
51 pci_config_writew(d, PCI_COMMAND, cmd);
54 /* return the global irq number corresponding to a given device irq
55 pin. We could also use the bus number to have a more precise
57 static int pci_slot_get_pirq(PCIDevice pci_dev, int irq_num)
60 slot_addend = (pci_dev.devfn >> 3) - 1;
61 return (irq_num + slot_addend) & 3;
64 static void pci_bios_init_bridges(PCIDevice d)
66 u16 vendor_id, device_id;
68 vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
69 device_id = pci_config_readw(d, PCI_DEVICE_ID);
71 if (vendor_id == PCI_VENDOR_ID_INTEL
72 && (device_id == PCI_DEVICE_ID_INTEL_82371SB_0
73 || device_id == PCI_DEVICE_ID_INTEL_82371AB_0)) {
77 /* PIIX3/PIIX4 PCI to ISA bridge */
81 for(i = 0; i < 4; i++) {
83 /* set to trigger level */
84 elcr[irq >> 3] |= (1 << (irq & 7));
85 /* activate irq remapping in PIIX */
86 pci_config_writeb(d, 0x60 + i, irq);
90 dprintf(1, "PIIX3/PIIX4 init: elcr=%02x %02x\n",
95 static void pci_bios_init_device(PCIDevice d)
99 int i, pin, pic_irq, vendor_id, device_id;
101 class = pci_config_readw(d, PCI_CLASS_DEVICE);
102 vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
103 device_id = pci_config_readw(d, PCI_DEVICE_ID);
104 dprintf(1, "PCI: bus=%d devfn=0x%02x: vendor_id=0x%04x device_id=0x%04x\n",
105 d.bus, d.devfn, vendor_id, device_id);
108 if (vendor_id == PCI_VENDOR_ID_INTEL
109 && (device_id == PCI_DEVICE_ID_INTEL_82371SB_1
110 || device_id == PCI_DEVICE_ID_INTEL_82371AB)) {
111 /* PIIX3/PIIX4 IDE */
112 pci_config_writew(d, 0x40, 0x8000); // enable IDE0
113 pci_config_writew(d, 0x42, 0x8000); // enable IDE1
116 /* IDE: we map it as in ISA mode */
117 pci_set_io_region_addr(d, 0, 0x1f0);
118 pci_set_io_region_addr(d, 1, 0x3f4);
119 pci_set_io_region_addr(d, 2, 0x170);
120 pci_set_io_region_addr(d, 3, 0x374);
124 if (vendor_id != 0x1234)
126 /* VGA: map frame buffer to default Bochs VBE address */
127 pci_set_io_region_addr(d, 0, 0xE0000000);
131 if (vendor_id == PCI_VENDOR_ID_IBM) {
133 if (device_id == 0x0046 || device_id == 0xFFFF) {
135 pci_set_io_region_addr(d, 0, 0x80800000 + 0x00040000);
140 if (vendor_id == PCI_VENDOR_ID_APPLE &&
141 (device_id == 0x0017 || device_id == 0x0022)) {
143 pci_set_io_region_addr(d, 0, 0x80800000);
148 /* default memory mappings */
149 for(i = 0; i < PCI_NUM_REGIONS; i++) {
153 if (i == PCI_ROM_SLOT)
157 pci_config_writel(d, ofs, 0xffffffff);
158 val = pci_config_readl(d, ofs);
160 size = (~(val & ~0xf)) + 1;
161 if (val & PCI_ADDRESS_SPACE_IO)
162 paddr = &pci_bios_io_addr;
163 else if (size >= 0x04000000)
164 paddr = &pci_bios_bigmem_addr;
166 paddr = &pci_bios_mem_addr;
167 *paddr = ALIGN(*paddr, size);
168 pci_set_io_region_addr(d, i, *paddr);
175 /* map the interrupt */
176 pin = pci_config_readb(d, PCI_INTERRUPT_PIN);
178 pin = pci_slot_get_pirq(d, pin - 1);
179 pic_irq = pci_irqs[pin];
180 pci_config_writeb(d, PCI_INTERRUPT_LINE, pic_irq);
183 if (vendor_id == PCI_VENDOR_ID_INTEL
184 && device_id == PCI_DEVICE_ID_INTEL_82371AB_3) {
185 /* PIIX4 Power Management device (for ACPI) */
186 u32 pm_io_base = BUILD_PM_IO_BASE;
187 pci_config_writel(d, 0x40, pm_io_base | 1);
188 pci_config_writeb(d, 0x80, 0x01); /* enable PM io space */
189 u32 smb_io_base = BUILD_SMB_IO_BASE;
190 pci_config_writel(d, 0x90, smb_io_base | 1);
191 pci_config_writeb(d, 0xd2, 0x09); /* enable SMBus io space */
195 static void pci_for_each_device(void (*init_func)(PCIDevice d))
198 u16 vendor_id, device_id;
200 for(bus = 0; bus < 1; bus++) {
201 for(devfn = 0; devfn < 256; devfn++) {
202 PCIDevice d = pci_bd(bus, devfn);
203 vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
204 device_id = pci_config_readw(d, PCI_DEVICE_ID);
205 if (vendor_id != 0xffff || device_id != 0xffff) {
216 // Already done by coreboot.
219 pci_bios_io_addr = 0xc000;
220 pci_bios_mem_addr = 0xf0000000;
221 pci_bios_bigmem_addr = GET_EBDA(ram_size);
222 if (pci_bios_bigmem_addr < 0x90000000)
223 pci_bios_bigmem_addr = 0x90000000;
225 pci_for_each_device(pci_bios_init_bridges);
227 pci_for_each_device(pci_bios_init_device);