1 // Initialize PCI devices (on emulators)
3 // Copyright (C) 2008 Kevin O'Connor <kevin@koconnor.net>
4 // Copyright (C) 2006 Fabrice Bellard
6 // This file may be distributed under the terms of the GNU LGPLv3 license.
8 #include "util.h" // dprintf
9 #include "pci.h" // pci_config_readl
10 #include "biosvar.h" // GET_EBDA
11 #include "pci_ids.h" // PCI_VENDOR_ID_INTEL
12 #include "pci_regs.h" // PCI_COMMAND
14 #define PCI_ROM_SLOT 6
15 #define PCI_NUM_REGIONS 7
17 static u32 pci_bios_io_addr;
18 static u32 pci_bios_mem_addr;
19 /* host irqs corresponding to PCI irqs A-D */
20 static u8 pci_irqs[4] = {
24 static void pci_set_io_region_addr(u16 bdf, int region_num, u32 addr)
28 if (region_num == PCI_ROM_SLOT) {
29 ofs = PCI_ROM_ADDRESS;
31 ofs = PCI_BASE_ADDRESS_0 + region_num * 4;
34 old_addr = pci_config_readl(bdf, ofs);
36 pci_config_writel(bdf, ofs, addr);
37 dprintf(1, "region %d: 0x%08x\n", region_num, addr);
40 /* return the global irq number corresponding to a given device irq
41 pin. We could also use the bus number to have a more precise
43 static int pci_slot_get_pirq(u16 bdf, int irq_num)
45 int slot_addend = pci_bdf_to_dev(bdf) - 1;
46 return (irq_num + slot_addend) & 3;
49 static void pci_bios_init_bridges(u16 bdf)
51 u16 vendor_id = pci_config_readw(bdf, PCI_VENDOR_ID);
52 u16 device_id = pci_config_readw(bdf, PCI_DEVICE_ID);
54 if (vendor_id == PCI_VENDOR_ID_INTEL
55 && (device_id == PCI_DEVICE_ID_INTEL_82371SB_0
56 || device_id == PCI_DEVICE_ID_INTEL_82371AB_0)) {
60 /* PIIX3/PIIX4 PCI to ISA bridge */
64 for (i = 0; i < 4; i++) {
66 /* set to trigger level */
67 elcr[irq >> 3] |= (1 << (irq & 7));
68 /* activate irq remapping in PIIX */
69 pci_config_writeb(bdf, 0x60 + i, irq);
73 dprintf(1, "PIIX3/PIIX4 init: elcr=%02x %02x\n",
78 static void pci_bios_init_device(u16 bdf)
82 int i, pin, pic_irq, vendor_id, device_id;
84 class = pci_config_readw(bdf, PCI_CLASS_DEVICE);
85 vendor_id = pci_config_readw(bdf, PCI_VENDOR_ID);
86 device_id = pci_config_readw(bdf, PCI_DEVICE_ID);
87 dprintf(1, "PCI: bus=%d devfn=0x%02x: vendor_id=0x%04x device_id=0x%04x\n"
88 , pci_bdf_to_bus(bdf), pci_bdf_to_devfn(bdf), vendor_id, device_id);
90 case PCI_CLASS_STORAGE_IDE:
91 if (vendor_id == PCI_VENDOR_ID_INTEL
92 && (device_id == PCI_DEVICE_ID_INTEL_82371SB_1
93 || device_id == PCI_DEVICE_ID_INTEL_82371AB)) {
95 pci_config_writew(bdf, 0x40, 0x8000); // enable IDE0
96 pci_config_writew(bdf, 0x42, 0x8000); // enable IDE1
99 /* IDE: we map it as in ISA mode */
100 pci_set_io_region_addr(bdf, 0, PORT_ATA1_CMD_BASE);
101 pci_set_io_region_addr(bdf, 1, PORT_ATA1_CTRL_BASE);
102 pci_set_io_region_addr(bdf, 2, PORT_ATA2_CMD_BASE);
103 pci_set_io_region_addr(bdf, 3, PORT_ATA2_CTRL_BASE);
106 case PCI_CLASS_SYSTEM_PIC:
108 if (vendor_id == PCI_VENDOR_ID_IBM) {
110 if (device_id == 0x0046 || device_id == 0xFFFF) {
112 pci_set_io_region_addr(bdf, 0, 0x80800000 + 0x00040000);
117 if (vendor_id == PCI_VENDOR_ID_APPLE &&
118 (device_id == 0x0017 || device_id == 0x0022)) {
120 pci_set_io_region_addr(bdf, 0, 0x80800000);
125 /* default memory mappings */
126 for (i = 0; i < PCI_NUM_REGIONS; i++) {
128 if (i == PCI_ROM_SLOT)
129 ofs = PCI_ROM_ADDRESS;
131 ofs = PCI_BASE_ADDRESS_0 + i * 4;
133 u32 old = pci_config_readl(bdf, ofs);
135 if (i == PCI_ROM_SLOT) {
136 mask = PCI_ROM_ADDRESS_MASK;
137 pci_config_writel(bdf, ofs, mask);
139 if (old & PCI_BASE_ADDRESS_SPACE_IO)
140 mask = PCI_BASE_ADDRESS_IO_MASK;
142 mask = PCI_BASE_ADDRESS_MEM_MASK;
143 pci_config_writel(bdf, ofs, ~0);
145 u32 val = pci_config_readl(bdf, ofs);
146 pci_config_writel(bdf, ofs, old);
149 u32 size = (~(val & mask)) + 1;
150 if (val & PCI_BASE_ADDRESS_SPACE_IO)
151 paddr = &pci_bios_io_addr;
153 paddr = &pci_bios_mem_addr;
154 *paddr = ALIGN(*paddr, size);
155 pci_set_io_region_addr(bdf, i, *paddr);
162 /* enable memory mappings */
163 pci_config_maskw(bdf, PCI_COMMAND, 0, PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
165 /* map the interrupt */
166 pin = pci_config_readb(bdf, PCI_INTERRUPT_PIN);
168 pin = pci_slot_get_pirq(bdf, pin - 1);
169 pic_irq = pci_irqs[pin];
170 pci_config_writeb(bdf, PCI_INTERRUPT_LINE, pic_irq);
173 if (vendor_id == PCI_VENDOR_ID_INTEL
174 && device_id == PCI_DEVICE_ID_INTEL_82371AB_3) {
175 /* PIIX4 Power Management device (for ACPI) */
177 // acpi sci is hardwired to 9
178 pci_config_writeb(bdf, PCI_INTERRUPT_LINE, 9);
180 pci_config_writel(bdf, 0x40, PORT_ACPI_PM_BASE | 1);
181 pci_config_writeb(bdf, 0x80, 0x01); /* enable PM io space */
182 pci_config_writel(bdf, 0x90, PORT_SMB_BASE | 1);
183 pci_config_writeb(bdf, 0xd2, 0x09); /* enable SMBus io space */
191 // Already done by coreboot.
194 dprintf(3, "pci setup\n");
196 pci_bios_io_addr = 0xc000;
197 pci_bios_mem_addr = BUILD_PCIMEM_START;
200 foreachpci(bdf, max) {
201 pci_bios_init_bridges(bdf);
203 foreachpci(bdf, max) {
204 pci_bios_init_device(bdf);