1 // PCI BIOS (int 1a/b1) calls
3 // Copyright (C) 2008 Kevin O'Connor <kevin@koconnor.net>
4 // Copyright (C) 2002 MandrakeSoft S.A.
6 // This file may be distributed under the terms of the GNU LGPLv3 license.
8 #include "types.h" // u32
9 #include "util.h" // handle_1ab1
10 #include "pci.h" // pci_config_readl
11 #include "bregs.h" // struct bregs
12 #include "biosvar.h" // GET_EBDA
13 #include "pci_regs.h" // PCI_VENDOR_ID
15 #define RET_FUNC_NOT_SUPPORTED 0x81
16 #define RET_BAD_VENDOR_ID 0x83
17 #define RET_DEVICE_NOT_FOUND 0x86
18 #define RET_BUFFER_TOO_SMALL 0x89
22 handle_1ab101(struct bregs *regs)
26 foreachpci(bdf, max) {
29 regs->al = 0x01; // Flags - "Config Mechanism #1" supported.
30 regs->bx = 0x0210; // PCI version 2.10
31 regs->cl = pci_bdf_to_bus(max - 1);
32 regs->edx = 0x20494350; // "PCI "
33 // XXX - bochs bios code sets edi to point to 32bit code - but no
34 // reference to this in spec.
35 set_code_success(regs);
40 handle_1ab102(struct bregs *regs)
42 u32 id = (regs->cx << 16) | regs->dx;
45 foreachpci(bdf, max) {
46 u32 v = pci_config_readl(bdf, PCI_VENDOR_ID);
52 set_code_success(regs);
55 set_code_fail(regs, RET_DEVICE_NOT_FOUND);
60 handle_1ab103(struct bregs *regs)
63 u32 classprog = regs->ecx;
65 foreachpci(bdf, max) {
66 u32 v = pci_config_readl(bdf, PCI_CLASS_REVISION);
67 if ((v>>8) != classprog)
72 set_code_success(regs);
75 set_code_fail(regs, RET_DEVICE_NOT_FOUND);
78 // read configuration byte
80 handle_1ab108(struct bregs *regs)
82 regs->cl = pci_config_readb(regs->bx, regs->di);
83 set_code_success(regs);
86 // read configuration word
88 handle_1ab109(struct bregs *regs)
90 regs->cx = pci_config_readw(regs->bx, regs->di);
91 set_code_success(regs);
94 // read configuration dword
96 handle_1ab10a(struct bregs *regs)
98 regs->ecx = pci_config_readl(regs->bx, regs->di);
99 set_code_success(regs);
102 // write configuration byte
104 handle_1ab10b(struct bregs *regs)
106 pci_config_writeb(regs->bx, regs->di, regs->cl);
107 set_code_success(regs);
110 // write configuration word
112 handle_1ab10c(struct bregs *regs)
114 pci_config_writew(regs->bx, regs->di, regs->cx);
115 set_code_success(regs);
118 // write configuration dword
120 handle_1ab10d(struct bregs *regs)
122 pci_config_writel(regs->bx, regs->di, regs->ecx);
123 set_code_success(regs);
126 // get irq routing options
128 handle_1ab10e(struct bregs *regs)
130 struct pir_header *pirtable_g = (void*)(GET_GLOBAL(PirOffset) + 0);
132 set_code_fail(regs, RET_FUNC_NOT_SUPPORTED);
140 } *param_far = (void*)(regs->di+0);
142 // Validate and update size.
143 u16 bufsize = GET_FARVAR(regs->es, param_far->size);
144 u16 pirsize = GET_GLOBAL(pirtable_g->size) - sizeof(struct pir_header);
145 SET_FARVAR(regs->es, param_far->size, pirsize);
146 if (bufsize < pirsize) {
147 set_code_fail(regs, RET_BUFFER_TOO_SMALL);
152 void *buf_far = (void*)(GET_FARVAR(regs->es, param_far->buf_off)+0);
153 u16 buf_seg = GET_FARVAR(regs->es, param_far->buf_seg);
155 // Memcpy pir table slots to dest buffer.
156 memcpy_far(buf_seg, buf_far
157 , get_global_seg(), pirtable_g->slots
160 // XXX - bochs bios sets bx to (1 << 9) | (1 << 11)
161 regs->bx = GET_GLOBAL(pirtable_g->exclusive_irqs);
162 set_code_success(regs);
166 handle_1ab1XX(struct bregs *regs)
168 set_code_fail(regs, RET_FUNC_NOT_SUPPORTED);
172 handle_1ab1(struct bregs *regs)
176 if (! CONFIG_PCIBIOS) {
182 case 0x01: handle_1ab101(regs); break;
183 case 0x02: handle_1ab102(regs); break;
184 case 0x03: handle_1ab103(regs); break;
185 case 0x08: handle_1ab108(regs); break;
186 case 0x09: handle_1ab109(regs); break;
187 case 0x0a: handle_1ab10a(regs); break;
188 case 0x0b: handle_1ab10b(regs); break;
189 case 0x0c: handle_1ab10c(regs); break;
190 case 0x0d: handle_1ab10d(regs); break;
191 case 0x0e: handle_1ab10e(regs); break;
192 default: handle_1ab1XX(regs); break;