4 * Copyright (C) 2008 Nguyen Anh Quynh <aquynh@gmail.com>
5 * Copyright (C) 2002 MandrakeSoft S.A.
7 * This file may be distributed under the terms of the GNU GPLv3 license.
18 u32 pm_io_base, smb_io_base;
20 PCIDevice i440_pcidev;
22 static u32 pci_bios_io_addr = 0xC000;
23 static u32 pci_bios_mem_addr = 0xF0000000;
24 static u32 pci_bios_bigmem_addr;
26 /* host irqs corresponding to PCI irqs A-D */
27 static u8 pci_irqs[4] = { 11, 9, 11, 9 };
31 pci_set_io_region_addr(PCIDevice *d, int region_num, u32 addr)
36 if (region_num == PCI_ROM_SLOT)
39 ofs = 0x10 + region_num * 4;
41 old_addr = pci_config_readl(d, ofs);
43 pci_config_writel(d, ofs, addr);
44 BX_INFO("region %d: 0x%08x\n", region_num, addr);
46 /* enable memory mappings */
47 cmd = pci_config_readw(d, PCI_COMMAND);
48 if (region_num == PCI_ROM_SLOT)
50 else if (old_addr & PCI_ADDRESS_SPACE_IO)
54 pci_config_writew(d, PCI_COMMAND, cmd);
57 /* return the global irq number corresponding to a given device irq
58 pin. We could also use the bus number to have a more precise
61 pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num)
65 slot_addend = (pci_dev->devfn >> 3) - 1;
67 return (irq_num + slot_addend) & 3;
71 find_bios_table_area(void)
75 for (addr = 0xf0000; addr < 0x100000; addr += 16) {
76 if (*(u32 *)addr == 0xaafb4442) {
77 bios_table_cur_addr = addr + 8;
78 bios_table_end_addr = bios_table_cur_addr + *(u32 *)(addr + 4);
79 BX_INFO("bios_table_addr: 0x%08lx end=0x%08lx\n",
80 bios_table_cur_addr, bios_table_end_addr);
90 bios_shadow_init(PCIDevice *d)
94 if (find_bios_table_area() < 0)
97 /* remap the BIOS to shadow RAM an keep it read/write while we
99 v = pci_config_readb(d, 0x59);
101 pci_config_writeb(d, 0x59, v);
102 memcpy((void *)BIOS_TMP_STORAGE, (void *)0x000f0000, 0x10000);
104 pci_config_writeb(d, 0x59, v);
105 memcpy((void *)0x000f0000, (void *)BIOS_TMP_STORAGE, 0x10000);
110 void bios_lock_shadow_ram(void)
112 PCIDevice *d = &i440_pcidev;
116 v = pci_config_readb(d, 0x59);
117 v = (v & 0x0f) | (0x10);
118 pci_config_writeb(d, 0x59, v);
121 static void pci_bios_init_bridges(PCIDevice *d)
123 u16 vendor_id, device_id;
125 vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
126 device_id = pci_config_readw(d, PCI_DEVICE_ID);
128 if (vendor_id == PCI_VENDOR_ID_INTEL && device_id == PCI_DEVICE_ID_INTEL_82371SB_0) {
135 for (i = 0; i < 4; i++) {
137 /* set to trigger level */
138 elcr[irq >> 3] |= (1 << (irq & 7));
139 /* activate irq remapping in PIIX */
140 pci_config_writeb(d, 0x60 + i, irq);
143 outb(elcr[0], 0x4d0);
144 outb(elcr[1], 0x4d1);
145 BX_INFO("PIIX3 init: elcr=%02x %02x\n", elcr[0], elcr[1]);
147 else if (vendor_id == PCI_VENDOR_ID_INTEL && device_id == PCI_DEVICE_ID_INTEL_82441) {
148 /* i440 PCI bridge */
154 pci_bios_init_device(PCIDevice *d)
158 int i, pin, pic_irq, vendor_id, device_id;
160 class = pci_config_readw(d, PCI_CLASS_DEVICE);
161 vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
162 device_id = pci_config_readw(d, PCI_DEVICE_ID);
163 BX_INFO("PCI: bus=%d devfn=0x%02x: vendor_id=0x%04x device_id=0x%04x\n",
164 d->bus, d->devfn, vendor_id, device_id);
167 if (vendor_id == PCI_VENDOR_ID_INTEL && device_id == PCI_DEVICE_ID_INTEL_82371SB_1) {
169 pci_config_writew(d, 0x40, 0x8000); // enable IDE0
170 pci_config_writew(d, 0x42, 0x8000); // enable IDE1
173 /* IDE: we map it as in ISA mode */
174 pci_set_io_region_addr(d, 0, 0x1f0);
175 pci_set_io_region_addr(d, 1, 0x3f4);
176 pci_set_io_region_addr(d, 2, 0x170);
177 pci_set_io_region_addr(d, 3, 0x374);
181 if (vendor_id != 0x1234)
183 /* VGA: map frame buffer to default Bochs VBE address */
184 pci_set_io_region_addr(d, 0, 0xE0000000);
188 if (vendor_id == PCI_VENDOR_ID_IBM) {
190 if (device_id == 0x0046 || device_id == 0xFFFF) {
192 pci_set_io_region_addr(d, 0, 0x80800000 + 0x00040000);
197 if (vendor_id == PCI_VENDOR_ID_APPLE &&
198 (device_id == 0x0017 || device_id == 0x0022)) {
200 pci_set_io_region_addr(d, 0, 0x80800000);
205 /* default memory mappings */
206 for (i = 0; i < PCI_NUM_REGIONS; i++) {
210 if (i == PCI_ROM_SLOT)
214 pci_config_writel(d, ofs, 0xffffffff);
215 val = pci_config_readl(d, ofs);
217 size = (~(val & ~0xf)) + 1;
218 if (val & PCI_ADDRESS_SPACE_IO)
219 paddr = &pci_bios_io_addr;
220 else if (size >= 0x04000000)
221 paddr = &pci_bios_bigmem_addr;
223 paddr = &pci_bios_mem_addr;
224 *paddr = (*paddr + size - 1) & ~(size - 1);
225 pci_set_io_region_addr(d, i, *paddr);
232 /* map the interrupt */
233 pin = pci_config_readb(d, PCI_INTERRUPT_PIN);
235 pin = pci_slot_get_pirq(d, pin - 1);
236 pic_irq = pci_irqs[pin];
237 pci_config_writeb(d, PCI_INTERRUPT_LINE, pic_irq);
240 if (vendor_id == PCI_VENDOR_ID_INTEL && device_id == PCI_DEVICE_ID_INTEL_82371AB_3) {
241 /* PIIX4 Power Management device (for ACPI) */
242 pm_io_base = PM_IO_BASE;
243 pci_config_writel(d, 0x40, pm_io_base | 1);
244 pci_config_writeb(d, 0x80, 0x01); /* enable PM io space */
245 smb_io_base = SMB_IO_BASE;
246 pci_config_writel(d, 0x90, smb_io_base | 1);
247 pci_config_writeb(d, 0xd2, 0x09); /* enable SMBus io space */
248 pm_sci_int = pci_config_readb(d, PCI_INTERRUPT_LINE);
257 pci_for_each_device(void (*init_func)(PCIDevice *d))
259 PCIDevice d1, *d = &d1;
261 u16 vendor_id, device_id;
263 for (bus = 0; bus < 1; bus++) {
264 for (devfn = 0; devfn < 256; devfn++) {
267 vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
268 device_id = pci_config_readw(d, PCI_DEVICE_ID);
269 if (vendor_id != 0xffff || device_id != 0xffff)
278 pci_bios_bigmem_addr = ram_size;
280 if (pci_bios_bigmem_addr < 0x90000000)
281 pci_bios_bigmem_addr = 0x90000000;
283 pci_for_each_device(pci_bios_init_bridges);
285 pci_for_each_device(pci_bios_init_device);