2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
6 entity pc_communication is
8 sys_clk : in std_logic;
9 sys_res_n : in std_logic;
15 tx_data : out std_logic_vector(7 downto 0);
16 tx_new : out std_logic;
17 tx_done : in std_logic;
20 rx_data : in std_logic_vector(7 downto 0);
21 rx_new : in std_logic;
24 pc_zeile : out hzeile;
25 pc_spalte : out hspalte;
26 pc_get : out std_logic;
27 pc_busy : in std_logic; --signals if the history module actually grants our request.
28 pc_done : in std_logic;
31 end entity pc_communication;
33 architecture beh of pc_communication is
34 signal spalte, spalte_next : integer range 1 to hspalte_max + 1;
35 signal zeile , zeile_next : integer range 1 to hzeile_max + 1;
36 signal get, get_next : std_logic;
37 signal new_i, new_i_next : std_logic;
38 signal tx_done_i, tx_done_i_next : std_logic;
39 signal tx_data_i, tx_data_i_next : std_logic_vector (7 downto 0);
41 type STATE_PC is (IDLE, WAIT_HIST, FETCH, FORWARD, WAIT_UART, UART_DONE);
42 signal state, state_next : STATE_PC ;
47 pc_zeile <= hzeile(std_logic_vector(to_unsigned(zeile,7)));
48 pc_spalte <= hspalte(std_logic_vector(to_unsigned(spalte,7)));
51 tx_done_i_next <= tx_done;
54 sync: process (sys_clk, sys_res_n)
56 if sys_res_n = '0' then
62 tx_data_i <= "00000000";
64 elsif rising_edge(sys_clk) then
65 spalte <= spalte_next;
70 tx_done_i <= tx_done_i_next;
71 tx_data_i <= tx_data_i_next;
75 output_pc : process (state, zeile, spalte, tx_data_i, tx_done_i, pc_char)
80 spalte_next <= spalte;
82 tx_data_i_next <= tx_data_i;
90 tx_data_i_next <= pc_char;
96 if tx_data_i = x"00" or spalte = hspalte_max then
97 tx_data_i_next <= x"0a";
98 zeile_next <= zeile + 1;
100 if zeile = hzeile_max then
104 spalte_next <= spalte + 1;
107 end process output_pc;
109 next_state_pc : process (btn_a, pc_busy, pc_done, rx_new, rx_data, spalte,
110 state, tx_data_i ,tx_done_i, zeile)
115 -- if (rx_new = '1' and rx_data = x"0a") or btn_a = '0' then
116 if (rx_new = '1') or btn_a = '0' then
120 if pc_busy = '1' then
121 state_next <= WAIT_HIST;
126 if (pc_done = '1') then
127 state_next <= FORWARD;
130 state_next <= WAIT_UART;
132 if (tx_done_i = '1') then
133 state_next <= UART_DONE;
136 if (tx_data_i = x"00" or spalte = hspalte_max) and
137 zeile = hzeile_max then
143 end process next_state_pc;
145 end architecture beh;