2 * This file is part of the coreboot project.
4 * Copyright (C) 2009 coresystems GmbH
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #include <pc80/i8259.h>
22 #include <console/console.h>
24 #define MASTER_PIC_ICW1 0x20
25 #define SLAVE_PIC_ICW1 0xa0
26 #define ICW_SELECT (1 << 4)
27 #define OCW_SELECT (0 << 4)
32 #define MASTER_PIC_ICW2 0x21
33 #define SLAVE_PIC_ICW2 0xa1
34 #define INT_VECTOR_MASTER 0x20
37 #define INT_VECTOR_SLAVE 0x28
41 #define MASTER_PIC_ICW3 0x21
42 #define CASCADED_PIC (1 << 2)
44 #define MASTER_PIC_ICW4 0x21
45 #define SLAVE_PIC_ICW4 0xa1
46 #define MICROPROCESSOR_MODE (1 << 0)
48 #define SLAVE_PIC_ICW3 0xa1
51 #define MASTER_PIC_OCW1 0x21
52 #define SLAVE_PIC_OCW1 0xa1
59 void setup_i8259(void)
61 /* A write to ICW1 starts the Interrupt Controller Initialization
62 * Sequence. This implicitly causes the following to happen:
63 * - Interrupt Mask register is cleared
64 * - Priority 7 is assigned to IRQ7 input
65 * - Slave mode address is set to 7
66 * - Special mask mode is cleared
68 * We send the initialization sequence to both the master and
69 * slave i8259 controller.
71 outb(ICW_SELECT|IC4, MASTER_PIC_ICW1);
72 outb(ICW_SELECT|IC4, SLAVE_PIC_ICW1);
74 /* Now the interrupt controller expects us to write to ICW2. */
75 outb(INT_VECTOR_MASTER | IRQ0, MASTER_PIC_ICW2);
76 outb(INT_VECTOR_SLAVE | IRQ8, SLAVE_PIC_ICW2);
78 /* Now the interrupt controller expects us to write to ICW3.
80 * The normal scenario is to set up cascading on IRQ2 on the master
81 * i8259 and assign the slave ID 2 to the slave i8259.
83 outb(CASCADED_PIC, MASTER_PIC_ICW3);
84 outb(SLAVE_ID, SLAVE_PIC_ICW3);
86 /* Now the interrupt controller expects us to write to ICW4.
88 * We switch both i8259 to microprocessor mode because they're
89 * operating as part of an x86 architecture based chipset
91 outb(MICROPROCESSOR_MODE, MASTER_PIC_ICW2);
92 outb(MICROPROCESSOR_MODE, SLAVE_PIC_ICW2);
94 /* Now clear the interrupts through OCW1.
95 * First we mask off all interrupts on the slave interrupt controller
96 * then we mask off all interrupts but interrupt 2 on the master
97 * controller. This way the cascading stays alife.
99 outb(ALL_IRQS, SLAVE_PIC_OCW1);
100 outb(ALL_IRQS & ~IRQ2, MASTER_PIC_OCW1);
104 * @brief Configure IRQ triggering in the i8259 compatible Interrupt Controller.
106 * Switch a certain interrupt to be level / edge triggered.
108 * @param int_num legacy interrupt number (3-7, 9-15)
109 * @param is_level_triggered 1 for level triggered interrupt, 0 for edge
110 * triggered interrupt
112 void i8259_configure_irq_trigger(int int_num, int is_level_triggered)
114 u16 int_bits = inb(ELCR1) | (((u16)inb(ELCR2)) << 8);
116 printk(BIOS_SPEW, "%s: current interrupts are 0x%x\n", __func__, int_bits);
117 if (is_level_triggered)
118 int_bits |= (1 << int_num);
120 int_bits &= ~(1 << int_num);
122 /* Write new values */
123 printk(BIOS_SPEW, "%s: try to set interrupts 0x%x\n", __func__, int_bits);
124 outb((u8)(int_bits & 0xff), ELCR1);
125 outb((u8)(int_bits >> 8), ELCR2);
127 #ifdef PARANOID_IRQ_TRIGGERS
128 /* Try reading back the new values. This seems like an error but is not ... */
129 if (inb(ELCR1) != (int_bits & 0xff)) {
130 printk(BIOS_ERR, "%s: lower order bits are wrong: want 0x%x, got 0x%x\n",
131 __func__, (int_bits & 0xff), inb(ELCR1));
134 if (inb(ELCR2) != (int_bits >> 8)) {
135 printk(BIOS_ERR, "%s: higher order bits are wrong: want 0x%x, got 0x%x\n",
136 __func__, (int_bits>>8), inb(ELCR2));