2 * This file is part of the coreboot project.
4 * Copyright (C) 2009 One Laptop per Child, Association, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #include <console/console.h>
22 #include <device/device.h>
23 #include <device/pci.h>
24 #include <device/pci_ops.h>
25 #include <device/pci_ids.h>
27 #include <pc80/mc146818rtc.h>
28 #include <pc80/keyboard.h>
29 #include <pc80/i8259.h>
33 static const unsigned char pciIrqs[4] = { 0xa, 0x9, 0xb, 0xa };
35 static const unsigned char vgaPins[4] = { 'A', 'B', 'C', 'D' }; //only INTA
37 static const unsigned char slotPins[4] = { 'A', 'A', 'A', 'A' }; //all 4
39 static const unsigned char usbdevicePins[4] = { 'A', 'B', 'C', 'D' }; //only INTA
40 static const unsigned char sdioPins[4] = { 'A', 'B', 'C', 'D' }; //only INTA
41 static const unsigned char sd_ms_ctrl_Pins[4] = { 'B', 'C', 'D', 'A' }; //only INTA
42 static const unsigned char ce_ata_nf_ctrl_Pins[4] = { 'C', 'C', 'D', 'A' }; //only INTA
43 static const unsigned char idePins[4] = { 'B', 'C', 'D', 'A' }; //only INTA
45 static const unsigned char usbPins[4] = { 'A', 'B', 'C', 'D' }; //all 4
47 static const unsigned char hdacaudioPins[4] = { 'B', 'C', 'D', 'A' }; //only INTA
49 static unsigned char *pin_to_irq(const unsigned char *pin)
51 static unsigned char Irqs[4];
53 for (i = 0; i < 4; i++)
54 Irqs[i] = pciIrqs[pin[i] - 'A'];
59 static void pci_routing_fixup(struct device *dev)
61 printk(BIOS_INFO, "%s: dev is %p\n", __FUNCTION__, dev);
63 /* set up PCI IRQ routing */
64 pci_write_config8(dev, 0x55, pciIrqs[0] << 4);
65 pci_write_config8(dev, 0x56, pciIrqs[1] | (pciIrqs[2] << 4));
66 pci_write_config8(dev, 0x57, pciIrqs[3] << 4);
69 printk(BIOS_INFO, "setting vga\n");
70 pci_assign_irqs(0, 0x1, pin_to_irq(vgaPins));
73 printk(BIOS_INFO, "setting pci slot\n");
74 pci_assign_irqs(0, 0x08, pin_to_irq(slotPins));
77 printk(BIOS_INFO, "setting USB Device Controller\n");
78 pci_assign_irqs(0, 0x0b, pin_to_irq(usbdevicePins));
81 printk(BIOS_INFO, "setting SDIO Controller\n");
82 pci_assign_irqs(0, 0x0c, pin_to_irq(sdioPins));
85 printk(BIOS_INFO, "setting SD $ MS Controller\n");
86 pci_assign_irqs(0, 0x0d, pin_to_irq(sd_ms_ctrl_Pins));
89 printk(BIOS_INFO, "setting CE-ATA NF Controller(Card Boot)\n");
90 pci_assign_irqs(0, 0x0e, pin_to_irq(ce_ata_nf_ctrl_Pins));
93 printk(BIOS_INFO, "setting ide\n");
94 //pci_assign_irqs(0, 0x0f, pin_to_irq(idePins));
96 /* Standard usb components */
97 printk(BIOS_INFO, "setting usb1-2\n");
98 // pci_assign_irqs(0, 0x10, pin_to_irq(usbPins));
101 printk(BIOS_INFO, "setting hdac audio\n");
102 pci_assign_irqs(0, 0x14, pin_to_irq(hdacaudioPins));
104 printk(BIOS_SPEW, "%s: DONE\n", __FUNCTION__);
107 static void setup_pm(device_t dev)
110 /* Debounce LID and PWRBTN# Inputs for 16ms. */
111 pci_write_config8(dev, 0x80, 0x20);
113 /* Set ACPI base address to IO VX800_ACPI_IO_BASE */
114 pci_write_config16(dev, 0x88, VX800_ACPI_IO_BASE | 1);
116 /* set ACPI irq to 9 */
117 pci_write_config8(dev, 0x82, 0x49);
119 /* Primary interupt channel, define wake events 0=IRQ0 15=IRQ15 1=en. */
120 // pci_write_config16(dev, 0x84, 0x30f2);
121 pci_write_config16(dev, 0x84, 0x609a); // 0x609a??
123 /* SMI output level to low, 7.5us throttle clock */
124 pci_write_config8(dev, 0x8d, 0x18);
126 /* GP Timer Control 1s */
127 pci_write_config8(dev, 0x93, 0x88);
130 pci_write_config8(dev, 0x94, 0x20); // 0x20??
132 /* 7 = stp to sust delay 1msec
133 * 6 = SUSST# Deasserted Before PWRGD for STD
135 pci_write_config8(dev, 0x95, 0xc0); // 0xc1??
137 /* Disable GP2 & GP3 Timer */
138 pci_write_config8(dev, 0x98, 0);
140 /* GP2 Timer Counter */
141 pci_write_config8(dev, 0x99, 0xfb);
142 /* GP3 Timer Counter */
143 //pci_write_config8(dev, 0x9a, 0x20);
145 /* Multi Function Select 1 */
146 pci_write_config8(dev, 0xe4, 0x00);
147 /* Multi Function Select 2 */
148 pci_write_config8(dev, 0xe5, 0x41); //??
150 /* Enable ACPI access (and setup like award) */
151 pci_write_config8(dev, 0x81, 0x84);
153 /* Clear status events. */
154 outw(0xffff, VX800_ACPI_IO_BASE + 0x00);
155 outw(0xffff, VX800_ACPI_IO_BASE + 0x20);
156 outw(0xffff, VX800_ACPI_IO_BASE + 0x28);
157 outl(0xffffffff, VX800_ACPI_IO_BASE + 0x30);
159 /* Disable SCI on GPIO. */
160 outw(0x0, VX800_ACPI_IO_BASE + 0x22);
162 /* Disable SMI on GPIO. */
163 outw(0x0, VX800_ACPI_IO_BASE + 0x24);
165 /* Disable all global enable SMIs. */
166 outw(0x0, VX800_ACPI_IO_BASE + 0x2a);
168 /* All SMI off, both IDE buses ON, PSON rising edge. */
169 outw(0x0, VX800_ACPI_IO_BASE + 0x2c);
171 /* Primary activity SMI disable. */
172 outl(0x0, VX800_ACPI_IO_BASE + 0x34);
174 /* GP timer reload on none. */
175 outl(0x0, VX800_ACPI_IO_BASE + 0x38);
177 /* Disable extended IO traps. */
178 outb(0x0, VX800_ACPI_IO_BASE + 0x42);
180 tmp = inw(VX800_ACPI_IO_BASE + 0x04);
181 /* SCI is generated for RTC/pwrBtn/slpBtn. */
183 outw(tmp, VX800_ACPI_IO_BASE + 0x04);
185 /* Allow SLP# signal to assert LDTSTOP_L.
186 * Will work for C3 and for FID/VID change.
188 outb(0x1, VX800_ACPI_IO_BASE + 0x11);
196 outl(0xffff7fff, 0x448);
201 static void S3_ps2_kb_ms_wakeup(struct device *dev)
204 enables = pci_read_config8(dev, 0x51);
206 pci_write_config8(dev, 0x51, enables);
209 outb(0x0b, 0x2f); //if 09,then only support kb wakeup
211 outb(0xe1, 0x2e); //set any key scan code can wakeup
214 outb(0xe9, 0x2e); //set any mouse scan code can wakeup
218 pci_write_config8(dev, 0x51, enables);
220 outb(inb(VX800_ACPI_IO_BASE + 0x02) | 0x20, VX800_ACPI_IO_BASE + 0x02); //ACPI golabe enable for sci smi trigger
221 outw(inw(VX800_ACPI_IO_BASE + 0x22) | 0x204, VX800_ACPI_IO_BASE + 0x22); //ACPI SCI on Internal KBC PME and mouse PME
225 static void S3_usb_wakeup(struct device *dev)
227 outw(inw(VX800_ACPI_IO_BASE + 0x22) | 0x4000, VX800_ACPI_IO_BASE + 0x22); //SCI on USB PME
230 static void S3_lid_wakeup(struct device *dev)
232 outw(inw(VX800_ACPI_IO_BASE + 0x22) | 0x800, VX800_ACPI_IO_BASE + 0x22); //SCI on LID PME
235 /* This looks good enough to work, maybe */
236 static void vx800_sb_init(struct device *dev)
238 unsigned char enables;
240 // enable the internal I/O decode
241 enables = pci_read_config8(dev, 0x6C);
243 pci_write_config8(dev, 0x6C, enables);
245 // Map 4MB of FLASH into the address space
246 // pci_write_config8(dev, 0x41, 0x7f);
248 // Set bit 6 of 0x40, because Award does it (IO recovery time)
249 // IMPORTANT FIX - EISA 0x4d0 decoding must be on so that PCI
250 // interrupts can be properly marked as level triggered.
251 enables = pci_read_config8(dev, 0x40);
253 pci_write_config8(dev, 0x40, enables);
255 /* DMA Line buffer control */
256 enables = pci_read_config8(dev, 0x42);
258 pci_write_config8(dev, 0x42, enables);
260 /* I/O recovery time */
261 pci_write_config8(dev, 0x4c, 0x44);
263 /* ROM memory cycles go to LPC. */
264 pci_write_config8(dev, 0x59, 0x80);
266 /* Set 0x5b to 0x01 to match Award */
267 //pci_write_config8(dev, 0x5b, 0x01);
268 enables = pci_read_config8(dev, 0x5b);
270 pci_write_config8(dev, 0x5b, enables);
272 /* Set Read Pass Write Control Enable */
273 pci_write_config8(dev, 0x48, 0x0c);
275 /* Set 0x58 to 0x42 APIC and RTC. */
276 //pci_write_config8(dev, 0x58, 0x42); this cmd cause the irq0 can not be triggerd,since bit 5 was set to 0.
277 enables = pci_read_config8(dev, 0x58);
279 pci_write_config8(dev, 0x58, enables);
281 /* Set bit 3 of 0x4f to match award (use INIT# as cpu reset) */
282 enables = pci_read_config8(dev, 0x4f);
284 pci_write_config8(dev, 0x4f, enables);
286 /* enable serial irq */
287 pci_write_config8(dev, 0x52, 0x9);
290 pci_write_config8(dev, 0x53, 0x00);
292 // Power management setup
295 /* set up isa bus -- i/o recovery time, rom write enable, extend-ale */
296 pci_write_config8(dev, 0x40, 0x54);
302 /* total kludge to get lxb to call our childrens set/enable functions - these are
303 not called unless this device has a resource to set - so set a dummy one */
304 static void vx800_read_resources(device_t dev)
307 struct resource *resource;
308 pci_dev_read_resources(dev);
309 resource = new_resource(dev, 1);
311 IORESOURCE_FIXED | IORESOURCE_ASSIGNED | IORESOURCE_IO |
314 resource->base = 0x2e;
317 static void vx800_set_resources(device_t dev)
319 struct resource *resource;
320 resource = find_resource(dev, 1);
321 resource->flags |= IORESOURCE_STORED;
322 pci_dev_set_resources(dev);
325 static void vx800_enable_resources(device_t dev)
327 /* vx800 is not a pci bridge and has no resources of its own (other than
328 standard PC i/o addresses). however it does control the isa bus and so
329 we need to manually call enable childrens resources on that bus */
330 /* TODO: do we even care about ISA? If so, for what? SuperIO on LPC bus */
331 pci_dev_enable_resources(dev);
332 enable_childrens_resources(dev);
335 static void southbridge_init(struct device *dev)
337 printk(BIOS_DEBUG, "vx800 sb init\n");
339 pci_routing_fixup(dev);
341 setup_i8259(); // make sure interupt controller is configured before keyboard init
343 /* turn on keyboard and RTC, no need to visit this reg twice */
345 printk(BIOS_DEBUG, "ps2 usb lid, you set who can wakeup system from s3 sleep\n");
346 S3_ps2_kb_ms_wakeup(dev);
349 /* enable acpi cpu c3 state. (c2 state need not do anything.)
351 fadt->pm2_cnt_blk = 0x22;//to support cpu-c3
352 fadt->p_lvl2_lat = 0x50; //this is the coreboot source
353 fadt->p_lvl3_lat = 0x320;//
354 fadt->pm2_cnt_len = 1;//to support cpu-c3
356 ssdt? ->every cpu has a P_BLK address. set it to 0x10 (so that "Read Processor Level3 register(PMIORx15<7:0>) to enter C3 state"---VIA vx800 P SPEC )
357 #3 write 0x17 in to PMIO=VX800_ACPI_IO_BASE + 0x26, following the describtion in the P-spec.
358 1 enable SLP# asserts in C3 state PMIORx26<1> =1
359 2 enable CPUSTP# asserts in C3 state; PMIORx26<2> =1
360 3 CLKRUN# is always asserted PMIORx26<3> =0
361 4 Disable PCISTP# When CLKRUN# is asserted
362 1: PCISTP# will not assert When CLKRUN# is asserted
364 5 This bit controls whether the CPU voltage is lowered when in C3/S1 state.
365 VRDSLP will be active in either this bit set in C3 or LVL4 register read
367 6 Read Processor Level3 register(PMIORx15<7:0>) to enter C3 state PMIORx15
369 outb(0x17, VX800_ACPI_IO_BASE + 0x26);
373 static struct device_operations vx800_lpc_ops = {
374 .read_resources = vx800_read_resources,
375 .set_resources = vx800_set_resources,
376 .enable_resources = vx800_enable_resources,
377 .init = &southbridge_init,
378 .scan_bus = scan_static_bus,
381 static const struct pci_driver lpc_driver __pci_driver = {
382 .ops = &vx800_lpc_ops,
383 .vendor = PCI_VENDOR_ID_VIA,
384 .device = PCI_DEVICE_ID_VIA_VX855_LPC,