2 * This file is part of the coreboot project.
4 * Copyright (C) 2009 One Laptop per Child, Association, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
24 static inline void vx800_noop(device_t dev)
38 #define SR_INDEX 0x3c4
40 #define CRTM_INDEX 0x3b4
41 #define CRTM_DATA 0x3b5
42 #define CRTC_INDEX 0x3d4
43 #define CRTC_DATA 0x3d5
45 /* Memory Controller Registers */
46 #define RANK0_END 0x40
47 #define RANK1_END 0x41
48 #define RANK2_END 0x42
49 #define RANK3_END 0x43
50 #define RANK0_START 0x48
51 #define RANK1_START 0x49
52 #define RANK2_START 0x4a
53 #define RANK3_START 0x4b
54 #define DDR_PAGE_CTL 0x69
55 #define DRAM_REFRESH_COUNTER 0x6a
56 #define DRAM_MISC_CTL 0x6b
57 #define CH_A_DQS_OUTPUT_DELAY 0x70
58 #define CH_A_MD_OUTPUT_DELAY 0x71
60 /* RAM Init Commands */
61 #define RAM_COMMAND_NORMAL 0x0
62 #define RAM_COMMAND_NOP 0x1
63 #define RAM_COMMAND_PRECHARGE 0x2
64 #define RAM_COMMAND_MRS 0x3
65 #define RAM_COMMAND_CBR 0x4
67 /* IDE specific bits */
68 #define IDE_MODE_REG 0x09
69 #define IDE0_NATIVE_MODE (1 << 0)
70 #define IDE1_NATIVE_MODE (1 << 2)
72 /* These are default addresses according to Via */
73 #define IDE0_DATA_ADDR 0x1f0
74 #define IDE0_CONTROL_ADDR 0x3f4
75 #define IDE1_DATA_ADDR 0x170
76 #define IDE1_CONTROL_ADDR 0x370
78 /* By Award default, Via default is 0xCC0 */
79 #define BUS_MASTER_ADDR 0xfe00
81 #define CHANNEL_ENABLE_REG 0x40
82 #define ENABLE_IDE0 (1 << 0)
83 #define ENABLE_IDE1 (1 << 1)
85 #define VX800_ACPI_IO_BASE 0x0400
87 #define NB_APIC_REG 0,0,5,
88 #define NB_PXPTRF_REG NB_APIC_REG
89 #define NB_MSGC_REG NB_APIC_REG
90 #define NB_HOST_REG 0,0,2,
91 #define NB_P6IF_REG NB_HOST_REG
93 #define NB_DRAMC_REG 0,0,3,
94 #define NB_PMU_REG 0,0,4,
95 #define NB_VLINK_REG 0,0,7,
96 #define NB_PEG_BRIDGE_REG 0,2, 0,
97 #define NB_D3F0_REG 0,3, 0,
98 #define NB_D3F1_REG 0,3, 1,
100 #define SB_LPC_REG 0,0x11,0,
101 #define SB_VLINK_REG 0,0x11,7,
102 #define SB_SATA_REG 0,0xf, 0,
103 #define SB_IDEC_REG 0,0xf, 0,
104 #define SB_P2PB_REG 0,0x13, 0,
105 #define SB_USB0_REG 0,0x10, 0,
106 #define SB_USB1_REG 0,0x10, 1,
107 #define SB_USB2_REG 0,0x10, 2,
108 #define SB_EHCI_REG 0,0x10, 4,
110 #define VX800SB_APIC_ID 0x4
111 #define VX800SB_APIC_BASE 0xfec00000ULL
112 #define VX800SB_APIC_DATA_OFFSET 0x10
113 #define VX800SB_APIC_ENTRY_NUMBER 0x40
115 #define VX800_D0F5_MMCONFIG_MBAR 0x61