2 * This file is part of the coreboot project.
4 * Copyright (C) 2009 One Laptop per Child, Association, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #ifndef ARCH_I386_PCI_RAWOPS_H
21 # define ARCH_I386_PCI_RAWOPS_H 1
24 #define PCI_RAWDEV(SEGBUS, DEV, FN) ( \
25 (((SEGBUS) & 0xFFF) << 20) | \
26 (((DEV) & 0x1F) << 15) | \
27 (((FN) & 0x07) << 12))
28 struct VIA_PCI_REG_INIT_TABLE {
38 typedef unsigned device_t_raw; /* pci and pci_mmio need to have different ways to have dev */
40 /* FIXME: We need to make the coreboot to run at 64bit mode, So when read/write memory above 4G,
41 * We don't need to set %fs, and %gs anymore
42 * Before that We need to use %gs, and leave %fs to other RAM access
44 uint8_t pci_io_rawread_config8(device_t_raw dev, unsigned where)
47 #if PCI_IO_CFG_EXT == 0
48 addr = (dev>>4) | where;
50 addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); //seg == 0
52 outl(0x80000000 | (addr & ~3), 0xCF8);
53 return inb(0xCFC + (addr & 3));
57 uint8_t pci_mmio_rawread_config8(device_t_raw dev, unsigned where)
64 uint8_t pci_rawread_config8(device_t_raw dev, unsigned where)
67 return pci_mmio_rawread_config8(dev, where);
69 return pci_io_rawread_config8(dev, where);
73 uint16_t pci_io_rawread_config16(device_t_raw dev, unsigned where)
76 #if PCI_IO_CFG_EXT == 0
77 addr = (dev>>4) | where;
79 addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16);
81 outl(0x80000000 | (addr & ~3), 0xCF8);
82 return inw(0xCFC + (addr & 2));
86 uint16_t pci_mmio_rawread_config16(device_t_raw dev, unsigned where)
94 uint16_t pci_rawread_config16(device_t_raw dev, unsigned where)
97 return pci_mmio_rawread_config16(dev, where);
99 return pci_io_rawread_config16(dev, where);
104 uint32_t pci_io_rawread_config32(device_t_raw dev, unsigned where)
107 #if PCI_IO_CFG_EXT == 0
108 addr = (dev>>4) | where;
110 addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16);
112 outl(0x80000000 | (addr & ~3), 0xCF8);
117 uint32_t pci_mmio_rawread_config32(device_t_raw dev, unsigned where)
121 return read32x(addr);
125 uint32_t pci_rawread_config32(device_t_raw dev, unsigned where)
128 return pci_mmio_rawread_config32(dev, where);
130 return pci_io_rawread_config32(dev, where);
134 void pci_io_rawwrite_config8(device_t_raw dev, unsigned where, uint8_t value)
137 #if PCI_IO_CFG_EXT == 0
138 addr = (dev>>4) | where;
140 addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16);
142 outl(0x80000000 | (addr & ~3), 0xCF8);
143 outb(value, 0xCFC + (addr & 3));
147 void pci_mmio_rawwrite_config8(device_t_raw dev, unsigned where, uint8_t value)
151 write8x(addr, value);
155 void pci_rawwrite_config8(device_t_raw dev, unsigned where, uint8_t value)
158 pci_mmio_rawwrite_config8(dev, where, value);
160 pci_io_rawwrite_config8(dev, where, value);
165 void pci_io_rawwrite_config16(device_t_raw dev, unsigned where, uint16_t value)
168 #if PCI_IO_CFG_EXT == 0
169 addr = (dev>>4) | where;
171 addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16);
173 outl(0x80000000 | (addr & ~3), 0xCF8);
174 outw(value, 0xCFC + (addr & 2));
178 void pci_mmio_rawwrite_config16(device_t_raw dev, unsigned where, uint16_t value)
182 write16x(addr, value);
186 void pci_rawwrite_config16(device_t_raw dev, unsigned where, uint16_t value)
189 pci_mmio_rawwrite_config16(dev, where, value);
191 pci_io_rawwrite_config16(dev, where, value);
196 void pci_io_rawwrite_config32(device_t_raw dev, unsigned where, uint32_t value)
199 #if PCI_IO_CFG_EXT == 0
200 addr = (dev>>4) | where;
202 addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16);
204 outl(0x80000000 | (addr & ~3), 0xCF8);
209 void pci_mmio_rawwrite_config32(device_t_raw dev, unsigned where, uint32_t value)
213 write32x(addr, value);
217 void pci_rawwrite_config32(device_t_raw dev, unsigned where, uint32_t value)
220 pci_mmio_rawwrite_config32(dev, where, value);
222 pci_io_rawwrite_config32(dev, where, value);
227 void pci_rawmodify_config8(device_t_raw dev, unsigned where, u8 orval,u8 mask)
228 { u8 data=pci_rawread_config8(dev,where);
231 pci_rawwrite_config8(dev,where,data);
233 void pci_rawmodify_config16(device_t_raw dev, unsigned where, uint16_t orval,uint16_t mask)
234 { uint16_t data=pci_rawread_config16(dev,where);
237 pci_rawwrite_config16(dev,where,data);
239 void pci_rawmodify_config32(device_t_raw dev, unsigned where, uint32_t orval,uint32_t mask)
240 { uint32_t data=pci_rawread_config32(dev,where);
243 pci_rawwrite_config32(dev,where,data);
246 void io_rawmodify_config8(u16 where, uint8_t orval,uint8_t mask)
254 void via_pci_inittable(u8 chipversion,struct VIA_PCI_REG_INIT_TABLE* initdata)
257 device_t_raw devbxdxfx;
259 if((initdata[i].Mask==0)&&(initdata[i].Value==0)&&(initdata[i].Bus==0)&&(initdata[i].ChipRevisionEnd==0xff)&&(initdata[i].ChipRevisionStart==0)&&(initdata[i].Device==0)&&(initdata[i].Function==0)&&(initdata[i].Register==0))
261 if((chipversion>=initdata[i].ChipRevisionStart)&&(chipversion<=initdata[i].ChipRevisionEnd)){
262 devbxdxfx=PCI_RAWDEV(initdata[i].Bus,initdata[i].Device,initdata[i].Function);
263 pci_rawmodify_config8(devbxdxfx, initdata[i].Register,initdata[i].Value,initdata[i].Mask);