src/northbridge/via/vx800/final_setting.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2009 One Laptop per Child, Association, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18  */
  19
  20 static const u8 RefreshCounter[7][2] = {
  21         //Non_256Mbit, 256Mbit
  22         {0xCA, 0xA8},           // DRAM400
  23         {0xCA, 0xA8},           // DRAM333
  24         {0xCA, 0x86},           // DRAM266
  25         {0xCA, 0x65},           // DRAM200
  26         {0xA8, 0x54},           // DRAM166
  27         {0x86, 0x43},           // DRAM133
  28         {0x65, 0x32}            // DRAM100
  29 };
  30
  31 void DRAMRefreshCounter(DRAM_SYS_ATTR * DramAttr)
  32 {
  33         u8 Data;
  34         u8 Freq = 5, i, Dram_256_Mb;
  35         if (DramAttr->DramFreq == DIMMFREQ_800)
  36                 Freq = 0;
  37         else if (DramAttr->DramFreq == DIMMFREQ_667)
  38                 Freq = 1;
  39         else if (DramAttr->DramFreq == DIMMFREQ_533)
  40                 Freq = 2;
  41         else if (DramAttr->DramFreq == DIMMFREQ_400)
  42                 Freq = 3;
  43         else if (DramAttr->DramFreq == DIMMFREQ_333)
  44                 Freq = 4;
  45         else if (DramAttr->DramFreq == DIMMFREQ_266)
  46                 Freq = 5;
  47         else if (DramAttr->DramFreq == DIMMFREQ_200)
  48                 Freq = 6;
  49         else
  50                 Freq = 6;
  51
  52         Dram_256_Mb = 0;
  53         for (i = 0; i < MAX_SOCKETS; i++) {
  54                 if (DramAttr->DimmInfo[i].SPDDataBuf[SPD_SDRAM_ROW_ADDR] == 13) {
  55                         Dram_256_Mb = 1;
  56                         break;
  57                 }
  58         }
  59
  60         Data = RefreshCounter[Freq][Dram_256_Mb];
  61
  62         pci_write_config8(MEMCTRL, 0x6a, Data);
  63 }
  64
  65 /*===================================================================
  66 Function   : DRAMRegFinalValue()
  67 Precondition :
  68 Input      :
  69                    DramAttr:  pointer point to  DRAM_SYS_ATTR  which consist the DDR and Dimm information
  70                                     in MotherBoard
  71 Output     : Void
  72 Purpose   : Chipset Performance UP and other setting after DRAM Sizing
  73                  Turn on register directly to promote performance
  74 ===================================================================*/
  75
  76 //--------------------------------------------------------------------------
  77 //        register       AND   OR
  78 //--------------------------------------------------------------------------
  79 #define DRAM_table_item         9
  80 static const u8 DRAM_table[DRAM_table_item][3] = {
  81         {0x60, 0xff, 0xD0},
  82         {0x66, 0xcf, 0x80},     // DRAMC queue > 2
  83         {0x69, 0xff, 0x07},     // Enable multiple page
  84         {0x95, 0x00, 0x0D},
  85         {0x96, 0x0F, 0xA0},
  86         {0xFB, 0x00, 0x3E},
  87         {0xFD, 0x00, 0xA9},
  88         {0xFE, 0x00, 0x0f},
  89         {0xFF, 0x00, 0x3D}
  90 };
  91
  92 #define PM_table_item           5
  93 static const u8 PM_table[PM_table_item][3] = {
  94         {0xA0, 0x0F, 0xF0},
  95         {0xA1, 0x1F, 0xE0},
  96         {0xA2, 0x00, 0xFE},
  97         {0xA3, 0x7F, 0x80},
  98         {0xA5, 0x7E, 0x81},
  99 };
 100
 101 void DRAMRegFinalValue(DRAM_SYS_ATTR * DramAttr)
 102 {
 103         u8 Data;
 104         u8 i;
 105
 106         for (i = 0; i < DRAM_table_item; i++) {
 107                 Data = pci_read_config8(MEMCTRL, DRAM_table[i][0]);
 108                 Data = (u8) ((Data & DRAM_table[i][1]) | DRAM_table[i][2]);
 109                 pci_write_config8(MEMCTRL, DRAM_table[i][0], Data);
 110         }
 111
 112         //enable dram By-Rank self refresh
 113         Data = pci_read_config8(MEMCTRL, 0x96);
 114         Data &= 0xF0;
 115         for (i = 0x01; i < 0x10; i = i << 1) {
 116                 if ((DramAttr->RankPresentMap & i) != 0x00)
 117                         Data |= i;
 118         }
 119         pci_write_config8(MEMCTRL, 0x96, Data);
 120
 121         for (i = 0; i < PM_table_item; i++) {
 122                 Data = pci_read_config8(PCI_DEV(0, 0, 4), PM_table[i][0]);
 123                 Data = (u8) ((Data & PM_table[i][1]) | PM_table[i][2]);
 124                 pci_write_config8(PCI_DEV(0, 0, 4), PM_table[i][0], Data);
 125         }
 126
 127 }