src/northbridge/via/vx800/driving_clk_phase_data.h

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2009 One Laptop per Child, Association, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18  */
  19
  20 #ifndef DRIVINGCLKPHASEDATA_H
  21 #define DRIVINGCLKPHASEDATA_H
  22
  23 //extern u8 DDR2_DQSA_Driving_Table[4] ;
  24 //extern u8 DDR2_DQSB_Driving_Table[2] ;
  25
  26 //extern u8 DDR2_DQA_Driving_Table[4] ;
  27 //extern u8 DDR2_DQB_Driving_Table[2] ;
  28
  29 //extern u8 DDR2_CSA_Driving_Table_x8[4] ;
  30 //extern u8 DDR2_CSB_Driving_Table_x8[2] ;
  31 //extern u8 DDR2_CSA_Driving_Table_x16[4];
  32 //extern u8 DDR2_CSB_Driving_Table_x16[2];
  33
  34 #define  MA_Table   3
  35 //extern u8 DDR2_MAA_Driving_Table[MA_Table][4];
  36 //extern u8 DDR2_MAB_Driving_Table[MA_Table][2];
  37
  38 //extern u8 DDR2_DCLKA_Driving_Table[4] ;
  39 //extern u8 DDR2_DCLKB_Driving_Table[4];
  40
  41 #define DUTY_CYCLE_FREQ_NUM   6
  42 #define DUTY_CYCLE_REG_NUM     3
  43 //extern u8 ChA_Duty_Control_DDR2[DUTY_CYCLE_REG_NUM][DUTY_CYCLE_FREQ_NUM];
  44 //extern u8 ChB_Duty_Control_DDR2[DUTY_CYCLE_REG_NUM][DUTY_CYCLE_FREQ_NUM];
  45
  46 #define Clk_Phase_Table_DDR2_Width        6
  47 //extern u8 DDR2_ChA_Clk_Phase_Table_1R[3][Clk_Phase_Table_DDR2_Width];
  48 //extern u8 DDR2_ChB_Clk_Phase_Table_1R[3][Clk_Phase_Table_DDR2_Width];
  49 //extern u8 DDR2_ChA_Clk_Phase_Table_2R[3][Clk_Phase_Table_DDR2_Width];
  50
  51 #define WrtData_REG_NUM        4
  52 #define WrtData_FREQ_NUM      6
  53 //extern u8 DDR2_ChA_WrtData_Phase_Table[WrtData_REG_NUM ][WrtData_FREQ_NUM];
  54 //extern u8 DDR2_ChB_WrtData_Phase_Table[WrtData_REG_NUM ][WrtData_FREQ_NUM];
  55
  56 #define DQ_DQS_Delay_Table_Width  4
  57 //extern u8 DDR2_CHA_DQ_DQS_Delay_Table[4][DQ_DQS_Delay_Table_Width];
  58 //extern u8 DDR2_CHB_DQ_DQS_Delay_Table[4][DQ_DQS_Delay_Table_Width];
  59
  60 #define DQS_INPUT_CAPTURE_REG_NUM            3
  61 #define DQS_INPUT_CAPTURE_FREQ_NUM             6
  62 //extern u8 DDR2_ChA_DQS_Input_Capture_Tbl[DQS_INPUT_CAPTURE_REG_NUM ][DQS_INPUT_CAPTURE_FREQ_NUM];
  63 //extern u8 DDR2_ChB_DQS_Input_Capture_Tbl[DQS_INPUT_CAPTURE_REG_NUM ][DQS_INPUT_CAPTURE_FREQ_NUM];
  64
  65 //extern u8 Fixed_DQSA_1_2_Rank_Table[4][2];
  66 //extern u8 Fixed_DQSA_3_4_Rank_Table[4][2];
  67
  68 //extern u8 Fixed_DQSB_1_2_Rank_Table[4][2];
  69 //extern u8 Fixed_DQSB_3_4_Rank_Table[4][2];
  70 #endif /* DRIVINGCLKPHASEDATA_H */