src/northbridge/via/vx800/drdy_bl.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2009 One Laptop per Child, Association, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18  */
  19
  20 // Set P6IF DRDY Timing
  21 // Because there are 1.5T & 2.5T CAS latency in DDR1 mode, we need to use RDELAYMD-0
  22 //
  23 //      Entry:
  24 //        EBP[29:25] = DRAM Speed, Dual_Channel
  25 //        VIA_NB2HOST_REG54[7:5]        Host Frequency
  26 //        VIA_NB3DRAM_REG62[2:0]        CAS Latency
  27 //
  28 //      Modify NB_Reg:
  29 //        VIA_NB2HOST_REG54[3,1]
  30 //        VIA_NB2HOST_REG55[1]
  31 //        VIA_NB2HOST_REG60
  32 //        VIA_NB2HOST_REG61
  33 //        VIA_NB2HOST_REG62[3:0]
  34 //        VIA_NB2HOST_REG63
  35 //        VIA_NB2HOST_REG64
  36 //        VIA_NB2HOST_REG65[3:0]
  37 //        VIA_NB2HOST_REG66
  38 //        VIA_NB2HOST_REG67[5:4]
  39 //
  40 // Processing:
  41 //--------------------------------------------------------------------------
  42 // P6IF DRDY Timing Control:
  43 // *Following algorithm to set DRDY timing
  44 // Set P6IF DRDY Timing by the following 3      conditions:
  45 // 1. RDELAYMD
  46 //    a.RDRPH(MD        input internal timing control)
  47 //    b.CAS Latency
  48 //    RDELAYMD(1bit) = bit0 of (CL + RDRPH)
  49 //    for example: RDRPH=10b, CL3 -> F3_Rx56[5:4]=11b, 10b + 11b        = 101b, RDELAYMD=1 (bit0)
  50 //                RDRPH=00b, CL2.5 -> F3_Rx56[5:4]=10b, 00b + 10b = 010b, RDELAYMD=0 (bit0)
  51 // 2. CPU Frequency
  52 // 3. DRAM Frequency
  53 //
  54 // According to above conditions, we create different tables:
  55 // 1. RDELAYMD=0        : for integer CAS latency(ex. CL=3)
  56 // 2. RDELAYMD=1        : for non-integer CAS latency(ex. CL=2.5)
  57 // 3. Normal performance
  58 // 4. Top performance :
  59 //                     Using phase0 to a case has better performance.
  60 //
  61 // Note: The setting are        related to performance and maybe affect DRAM initialize.
  62 //      Turn OFF(F2_Rx51[7]=0) this feature at csDRAMRegInitValueJ procedure.
  63 //      Turn ON(F2_Rx51[7]=1) this feature at csDRAMRegFinalValueJ procedure.
  64 //
  65 // If F2_Rx51[7]=0, then        CPU always wait 8QW, a slower but most stable way
  66 // If F2_Rx51[7]=1, then        the timing will refer to F2_Rx60 ~ F2_Rx67,
  67 // a fast way but may cause the system to be unstable.
  68 //
  69 // Coding:
  70 // 1. RDELAYMD and user's option        for performance can determine which table
  71 // 2. CPU Frequency can get block offset        of table
  72 // 3. DRAM Frequency can        get row offset of block
  73 // 4. Set value
  74 //
  75 // PS: Fun2 Rx62, Rx65, Rx67 are        don't care bits in 3296, CPU 266MHz doesn't be supported by 3296,
  76 //     but I still keep these bits in table to avoid the        usage in future
  77 //     and do the fewest        modification for code.
  78 //
  79
  80 // Early 3T
  81 // Early 3T
  82 #define P6IF_Misc_RFASTH                0x08
  83 #define P6IF_Misc2_RRRDYH3E             0x10
  84 #define P6IF_Misc2_RHTSEL               0x02
  85
  86 #define Rx54E3T                 P6IF_Misc_RFASTH
  87 #define Rx55E3T                 P6IF_Misc2_RRRDYH3E
  88
  89 // Early 2T
  90 #define Rx54E2T                 0x00
  91 #define Rx55E2T                 P6IF_Misc2_RRRDYH3E
  92
  93 // Early 1T
  94 #define Rx54E1T                 0x00
  95 #define Rx55E1T                 0x00
  96
  97 // Early 0T
  98 #define Rx54E0T                 P6IF_Misc_RFASTH
  99 #define Rx55E0T                 P6IF_Misc2_RRRDYH3E + P6IF_Misc2_RHTSEL
 100
 101 // Latter       1T
 102 #define Rx54L1T                 P6IF_Misc_RFASTH
 103 #define Rx55L1T                 P6IF_Misc2_RHTSEL
 104
 105 #define PH0_0_0_0       0x00
 106 #define PH0_0_0_1       0x01
 107 #define PH0_0_0_2       0x02
 108 #define PH0_0_0_3       0x03
 109 #define PH0_0_1_0       0x04
 110 #define PH0_0_1_1       0x05
 111 #define PH0_0_1_2       0x06
 112 #define PH0_0_2_1       0x09
 113 #define PH0_0_2_2       0x0a
 114 #define PH0_0_2_3       0x0b
 115 #define PH0_0_3_2       0x0e
 116 #define PH0_0_3_3       0x0f
 117 #define PH0_1_1_0       0x14
 118 #define PH0_1_1_1       0x15
 119 #define PH0_2_1_2       0x26
 120 #define PH0_2_2_1       0x29
 121 #define PH0_2_2_2       0x2a
 122 #define PH0_2_2_3       0x2b
 123 #define PH0_2_3_2       0x2e
 124 #define PH0_2_3_3       0x2f
 125 #define PH0_3_2_2       0x3a
 126 #define PH0_3_3_3       0x3f
 127 #define PH1_0_0_0       0x40
 128 #define PH1_0_0_1       0x41
 129 #define PH1_0_1_1       0x45
 130 #define PH1_1_1_1       0x55
 131 #define PH1_2_1_1       0x65
 132 #define PH1_2_2_1       0x69
 133 #define PH2_1_1_1       0x95
 134 #define PH2_1_2_1       0x99
 135 #define PH2_1_2_2       0x9a
 136 #define PH2_2_1_2       0xa6
 137 #define PH2_2_2_1       0xa9
 138 #define PH2_2_2_2       0xaa
 139 #define PH2_2_3_2       0xae
 140 #define PH2_2_3_3       0xaf
 141 #define PH2_3_2_2       0xba
 142 #define PH2_3_2_3       0xbb
 143 #define PH2_3_3_2       0xbe
 144 #define PH3_2_2_3       0xeb
 145 #define PH3_2_3_2       0xee
 146 #define PH3_2_3_3       0xef
 147 #define PH3_3_3_3       0xff
 148
 149 #define PT894_RDRDY_TBL_Width           10
 150 #define PT894_RDRDY_TBL_Block           60
 151
 152 static const u8 PT894_128bit_DELAYMD0_RCONV0[6][6][PT894_RDRDY_TBL_Width] =
 153 //    -----------------------------------------------------------------------------------------------------------------
 154 //    RX60           RX61           RX62            RX63           RX64       RX65           RX66  RX67   RX54[3,1]  RX55[3,1]    CPU/DRAM
 155 //    LN4:1          LN8:5          LN10:9          QW4:1          QW8:5      QW10:9     WS8:1 WS10:9 RFASTH     RRRDYH3E
 156 //                                                                                                                            RCONV          RHTSEL
 157 //    -----------------------------------------------------------------------------------------------------------------
 158 {
 159 // cpu100
 160         {
 161          {PH0_1_1_1, PH0_0_0_0, PH0_0_0_0, PH0_1_1_1, PH0_0_0_0, PH0_0_0_0, 0x00, 0x00, Rx54E3T, Rx55E3T},      // 100/100
 162          {PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x00, 0x00, Rx54E3T, Rx55E3T},      // 100/133
 163          {PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x00, 0x00, Rx54E3T, Rx55E3T},      // 100/166
 164          {PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x00, 0x00, Rx54E3T, Rx55E3T},      // 100/200
 165          {PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x00, 0x00, Rx54E3T, Rx55E3T},      // 100/266
 166          {PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x00, 0x00, Rx54E3T, Rx55E3T}       // 100/333
 167          },
 168 // cpu133
 169         {
 170          {PH0_2_2_1, PH0_0_0_0, PH0_0_0_0, PH0_2_2_1, PH0_0_0_0, PH0_0_0_0, 0x01, 0x00, Rx54E3T, Rx55E3T},      // 133/100
 171          {PH1_1_1_1, PH0_0_0_0, PH0_0_0_0, PH1_1_1_1, PH0_0_0_0, PH0_0_0_0, 0x00, 0x00, Rx54E3T, Rx55E3T},      // 133/133
 172          {PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x00, 0x00, Rx54E3T, Rx55E3T},      // 133/166
 173          {PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x00, 0x00, Rx54E3T, Rx55E3T},      // 133/200
 174          {PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x00, 0x00, Rx54E3T, Rx55E3T},      // 133/266
 175          {PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x00, 0x00, Rx54E3T, Rx55E3T}       // 133/333
 176          },
 177 // cpu200
 178         {
 179          {PH0_3_3_3, PH0_0_0_0, PH0_0_0_0, PH0_2_2_2, PH0_0_0_0, PH0_0_0_0, 0x07, 0x00, Rx54E2T, Rx55E2T},      // 200/100
 180          {PH2_3_2_3, PH0_0_0_0, PH0_0_0_0, PH2_3_2_3, PH0_0_0_0, PH0_0_0_0, 0x0a, 0x00, Rx54E3T, Rx55E3T},      // 200/133
 181          {PH1_2_2_1, PH0_0_0_1, PH0_0_0_0, PH1_2_2_1, PH0_0_0_1, PH0_0_0_0, 0x01, 0x00, Rx54E3T, Rx55E3T},      // 200/166
 182          {PH1_1_1_1, PH0_0_1_1, PH0_0_0_0, PH1_1_1_1, PH0_0_1_1, PH0_0_0_0, 0x00, 0x00, Rx54E3T, Rx55E3T},      // 200/200
 183          {PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x00, 0x00, Rx54E3T, Rx55E3T},      // 200/266
 184          {PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x00, 0x00, Rx54E3T, Rx55E3T}       // 200/333
 185          },
 186 // cpu166
 187         {
 188          {PH0_2_3_3, PH0_0_0_0, PH0_0_0_0, PH0_2_2_3, PH0_0_0_0, PH0_0_0_0, 0x05, 0x00, Rx54E3T, Rx55E3T},      // 166/100
 189          {PH1_2_2_1, PH0_0_0_0, PH0_0_0_0, PH1_2_2_1, PH0_0_0_0, PH0_0_0_0, 0x01, 0x00, Rx54E3T, Rx55E3T},      // 166/133
 190          {PH1_1_1_1, PH0_0_0_1, PH0_0_0_0, PH1_1_1_1, PH0_0_0_1, PH0_0_0_0, 0x00, 0x00, Rx54E3T, Rx55E3T},      // 166/166
 191          {PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x00, 0x00, Rx54E3T, Rx55E3T},      // 166/200
 192          {PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x00, 0x00, Rx54E3T, Rx55E3T},      // 166/266
 193          {PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x00, 0x00, Rx54E3T, Rx55E3T}       // 166/333
 194          },
 195 // cpu266
 196         {
 197          {PH0_2_2_3, PH0_0_0_0, PH0_0_0_0, PH0_0_1_1, PH0_0_0_0, PH0_0_0_0, 0x07, 0x00, Rx54E1T, Rx55E1T},      // 266/100
 198          {PH3_3_3_3, PH0_0_0_0, PH0_0_0_0, PH2_2_2_2, PH0_0_0_0, PH0_0_0_0, 0x0f, 0x00, Rx54E2T, Rx55E2T},      // 266/133
 199          {PH3_2_3_3, PH0_0_0_3, PH0_0_0_0, PH3_2_3_3, PH0_0_0_2, PH0_0_0_0, 0x0d, 0x00, Rx54E3T, Rx55E3T},      // 266/166
 200          {PH2_2_2_2, PH0_0_2_2, PH0_0_0_0, PH2_1_2_2, PH0_0_1_2, PH0_0_0_0, 0x12, 0x00, Rx54E3T, Rx55E3T},      // 266/200
 201          {PH1_1_1_1, PH1_1_1_1, PH0_0_0_0, PH1_1_1_1, PH1_1_1_1, PH0_0_0_0, 0x00, 0x00, Rx54E3T, Rx55E3T},      // 266/266
 202          {PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x00, 0x00, Rx54E3T, Rx55E3T}       // 266/333
 203          },
 204 // cpu333
 205         {
 206          {PH0_1_1_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x07, 0x00, Rx54E0T, Rx55E0T},      // 333/100
 207          {PH1_1_1_1, PH0_0_0_0, PH0_0_0_0, PH1_1_1_1, PH0_0_0_0, PH0_0_0_0, 0x0f, 0x00, Rx54E1T, Rx55E1T},      // 333/133
 208          {PH3_3_3_3, PH0_0_0_3, PH0_0_0_0, PH3_3_3_3, PH0_0_0_3, PH0_0_0_0, 0x1f, 0x00, Rx54E2T, Rx55E2T},      // 333/166
 209          {PH2_2_1_2, PH0_0_2_1, PH0_0_0_0, PH1_2_1_1, PH0_0_2_1, PH0_0_0_0, 0x36, 0x00, Rx54E2T, Rx55E2T},      // 333/200
 210          {PH2_1_1_1, PH2_1_1_1, PH0_0_0_0, PH2_1_1_1, PH2_1_1_1, PH0_0_0_0, 0x44, 0x00, Rx54E3T, Rx55E3T},      // 333/266
 211          {PH2_2_2_2, PH2_2_2_2, PH0_0_2_2, PH2_2_2_2, PH2_2_2_2, PH0_0_2_2, 0x00, 0x00, Rx54E3T, Rx55E3T}       // 333/333
 212          }
 213 };
 214
 215 static const u8 PT894_128bit_DELAYMD1_RCONV0[6][6][PT894_RDRDY_TBL_Width] =
 216 //    -----------------------------------------------------------------------------------------------------------------
 217 //    RX60           RX61           RX62            RX63           RX64       RX65           RX66  RX67   RX54[3,1]  RX55[3,1]    CPU/DRAM
 218 //    LN4:1          LN8:5          LN10:9          QW4:1          QW8:5      QW10:9     WS8:1 WS10:9 RFASTH     RRRDYH3E
 219 //                                                                                                                            RCONV          RHTSEL
 220 //    -----------------------------------------------------------------------------------------------------------------
 221 {
 222 // cpu100
 223         {
 224          {PH0_1_1_1, PH0_0_0_0, PH0_0_0_0, PH0_1_1_1, PH0_0_0_0, PH0_0_0_0, 0x00, 0x00, Rx54E3T, Rx55E3T},      // 100/100
 225          {PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x00, 0x00, Rx54E3T, Rx55E3T},      // 100/133
 226          {PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x00, 0x00, Rx54E3T, Rx55E3T},      // 100/166
 227          {PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x00, 0x00, Rx54E3T, Rx55E3T},      // 100/200
 228          {PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x00, 0x00, Rx54E3T, Rx55E3T},      // 100/266
 229          {PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x00, 0x00, Rx54E3T, Rx55E3T}       // 100/333
 230          },
 231 // cpu133
 232         {
 233          {PH0_3_2_2, PH0_0_0_0, PH0_0_0_0, PH0_3_2_2, PH0_0_0_0, PH0_0_0_0, 0x02, 0x00, Rx54E3T, Rx55E3T},      // 133/100
 234          {PH1_1_1_1, PH0_0_0_0, PH0_0_0_0, PH1_1_1_1, PH0_0_0_0, PH0_0_0_0, 0x00, 0x00, Rx54E3T, Rx55E3T},      // 133/133
 235          {PH1_0_0_0, PH0_0_0_0, PH0_0_0_0, PH1_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x00, 0x00, Rx54E3T, Rx55E3T},      // 133/166
 236          {PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x00, 0x00, Rx54E3T, Rx55E3T},      // 133/200
 237          {PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x00, 0x00, Rx54E3T, Rx55E3T},      // 133/266
 238          {PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x00, 0x00, Rx54E3T, Rx55E3T}       // 133/333
 239          },
 240 // cpu200
 241         {
 242          {PH0_2_2_2, PH0_0_0_0, PH0_0_0_0, PH0_1_1_1, PH0_0_0_0, PH0_0_0_0, 0x07, 0x00, Rx54E1T, Rx55E1T},      // 200/100
 243          {PH2_2_2_2, PH0_0_0_0, PH0_0_0_0, PH2_1_2_1, PH0_0_0_0, PH0_0_0_0, 0x0a, 0x00, Rx54E2T, Rx55E2T},      // 200/133
 244          {PH2_2_2_2, PH0_0_0_2, PH0_0_0_0, PH2_2_2_2, PH0_0_0_2, PH0_0_0_0, 0x04, 0x00, Rx54E3T, Rx55E3T},      // 200/166
 245          {PH2_2_2_2, PH0_0_2_2, PH0_0_0_0, PH2_2_2_2, PH0_0_2_2, PH0_0_0_0, 0x00, 0x00, Rx54E3T, Rx55E3T},      // 200/200
 246          {PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x00, 0x00, Rx54E3T, Rx55E3T},      // 200/266
 247          {PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x00, 0x00, Rx54E3T, Rx55E3T}       // 200/333
 248          },
 249 // cpu166
 250         {
 251          {PH0_2_2_2, PH0_0_0_0, PH0_0_0_0, PH0_2_1_2, PH0_0_0_0, PH0_0_0_0, 0x05, 0x00, Rx54E2T, Rx55E2T},      // 166/100
 252          {PH2_3_2_2, PH0_0_0_0, PH0_0_0_0, PH2_2_2_2, PH0_0_0_0, PH0_0_0_0, 0x02, 0x00, Rx54E3T, Rx55E3T},      // 166/133
 253          {PH2_2_2_2, PH0_0_0_2, PH0_0_0_0, PH2_2_2_2, PH0_0_0_2, PH0_0_0_0, 0x00, 0x00, Rx54E3T, Rx55E3T},      // 166/166
 254          {PH1_0_0_0, PH0_0_0_1, PH0_0_0_0, PH1_0_0_0, PH0_0_0_1, PH0_0_0_0, 0x00, 0x00, Rx54E3T, Rx55E3T},      // 166/200
 255          {PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x00, 0x00, Rx54E3T, Rx55E3T},      // 166/266
 256          {PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x00, 0x00, Rx54E3T, Rx55E3T}       // 166/333
 257          },
 258 // cpu266
 259         {
 260          {PH0_1_1_1, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x07, 0x00, Rx54E0T, Rx55E0T},      // 266/100
 261          {PH2_2_2_2, PH0_0_0_0, PH0_0_0_0, PH1_1_1_1, PH0_0_0_0, PH0_0_0_0, 0x0f, 0x00, Rx54E1T, Rx55E1T},      // 266/133
 262          {PH2_2_2_2, PH0_0_0_2, PH0_0_0_0, PH2_2_1_2, PH0_0_0_2, PH0_0_0_0, 0x15, 0x00, Rx54E2T, Rx55E2T},      // 266/166
 263          {PH3_2_3_3, PH0_0_2_3, PH0_0_0_0, PH2_2_3_2, PH0_0_2_3, PH0_0_0_0, 0x24, 0x00, Rx54E3T, Rx55E3T},      // 266/200
 264          {PH2_2_2_2, PH2_2_2_2, PH0_0_0_0, PH2_2_2_2, PH2_2_2_2, PH0_0_0_0, 0x00, 0x00, Rx54E3T, Rx55E3T},      // 266/266
 265          {PH0_0_0_1, PH0_0_1_1, PH0_0_1_0, PH0_0_0_1, PH0_0_1_1, PH0_0_1_0, 0x00, 0x00, Rx54E3T, Rx55E3T}       // 266/333
 266          },
 267 // cpu333
 268         {
 269          {PH0_3_2_2, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x07, 0x00, Rx54E0T, Rx55E0T},      // 333/100
 270          {PH1_1_1_1, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x0f, 0x00, Rx54E0T, Rx55E0T},      // 333/133
 271          {PH2_2_2_2, PH0_0_0_2, PH0_0_0_0, PH2_2_2_2, PH0_0_0_2, PH0_0_0_0, 0x1f, 0x00, Rx54E1T, Rx55E1T},      // 333/166
 272          {PH2_3_2_2, PH0_0_3_2, PH0_0_0_0, PH2_2_2_2, PH0_0_2_2, PH0_0_0_0, 0x1b, 0x00, Rx54E2T, Rx55E2T},      // 333/200
 273          {PH2_2_2_2, PH2_2_2_2, PH0_0_0_0, PH2_2_2_1, PH2_2_2_1, PH0_0_0_0, 0x88, 0x00, Rx54E3T, Rx55E3T},      // 333/266
 274          {PH2_2_2_2, PH2_2_2_2, PH0_0_2_2, PH2_2_2_2, PH2_2_2_2, PH0_0_2_2, 0x00, 0x00, Rx54E3T, Rx55E3T}       // 333/333
 275          }
 276 };
 277
 278 static const u8 PT894_64bit_DELAYMD0_RCONV0[6][6][PT894_RDRDY_TBL_Width] =
 279 //    -----------------------------------------------------------------------------------------------------------------
 280 //    RX60           RX61           RX62            RX63           RX64       RX65           RX66  RX67   RX54[3,1]  RX55[3,1]    CPU/DRAM
 281 //    LN4:1          LN8:5          LN10:9          QW4:1          QW8:5      QW10:9     WS8:1 WS10:9 RFASTH     RRRDYH3E
 282 //                                                                                                                            RCONV          RHTSEL
 283 //    -----------------------------------------------------------------------------------------------------------------
 284 {
 285 // cpu100
 286         {
 287          {PH0_2_2_2, PH0_0_0_0, PH0_0_0_0, PH0_1_1_1, PH0_0_0_0, PH0_0_0_0, 0x07, 0x00, Rx54E3T, Rx55E3T},      // 100/100
 288          {PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x09, 0x00, Rx54E3T, Rx55E3T},      // 100/133
 289          {PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x00, 0x00, Rx54E3T, Rx55E3T},      // 100/166
 290          {PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x00, 0x00, Rx54E3T, Rx55E3T},      // 100/200
 291          {PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x00, 0x00, Rx54E3T, Rx55E3T},      // 100/266
 292          {PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x00, 0x00, Rx54E3T, Rx55E3T}       // 100/333
 293          },
 294 // cpu133
 295         {
 296          {PH0_2_3_2, PH0_0_0_0, PH0_0_0_0, PH0_0_1_0, PH0_0_0_0, PH0_0_0_0, 0x07, 0x00, Rx54E2T, Rx55E2T},      // 133/100
 297          {PH2_2_2_2, PH0_0_0_0, PH0_0_0_0, PH1_1_1_1, PH0_0_0_0, PH0_0_0_0, 0x0f, 0x00, Rx54E3T, Rx55E3T},      // 133/133
 298          {PH1_0_0_0, PH0_0_0_1, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x07, 0x00, Rx54E3T, Rx55E3T},      // 133/166
 299          {PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x00, 0x00, Rx54E3T, Rx55E3T},      // 133/200
 300          {PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x00, 0x00, Rx54E3T, Rx55E3T},      // 133/266
 301          {PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x00, 0x00, Rx54E3T, Rx55E3T}       // 133/333
 302          },
 303 // cpu200
 304         {
 305          {PH0_3_3_3, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x07, 0x00, Rx54E0T, Rx55E0T},      // 200/100
 306          {PH2_2_2_2, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x0f, 0x00, Rx54E1T, Rx55E1T},      // 200/133
 307          {PH3_3_3_3, PH0_0_0_3, PH0_0_0_0, PH1_2_2_1, PH0_0_0_1, PH0_0_0_0, 0x1f, 0x00, Rx54E3T, Rx55E3T},      // 200/166
 308          {PH2_2_2_2, PH0_0_2_2, PH0_0_0_0, PH1_1_1_1, PH0_0_1_1, PH0_0_0_0, 0x3f, 0x00, Rx54E3T, Rx55E3T},      // 200/200
 309          {PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x00, 0x00, Rx54E1T, Rx55E1T},      // 200/266
 310          {PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x00, 0x00, Rx54E3T, Rx55E3T}       // 200/333
 311 // DDR2 Both E3T and E2T Fail, need set to E1T,  db     PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0,       00110011b, 00000000b, Rx54E3T,  Rx55E3T  ;200/266
 312          },
 313 // cpu166
 314         {
 315          {PH0_2_3_2, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x07, 0x00, Rx54E1T, Rx55E1T},      // 166/100
 316          {PH2_2_2_2, PH0_0_0_0, PH0_0_0_0, PH0_0_1_0, PH0_0_0_0, PH0_0_0_0, 0x0f, 0x00, Rx54E2T, Rx55E2T},      // 166/133
 317          {PH2_2_2_2, PH0_0_0_2, PH0_0_0_0, PH1_1_1_1, PH0_0_0_1, PH0_0_0_0, 0x1f, 0x00, Rx54E3T, Rx55E3T},      // 166/166
 318          {PH1_0_0_1, PH0_0_1_1, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x1e, 0x00, Rx54E3T, Rx55E3T},      // 166/200
 319          {PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x00, 0x00, Rx54E3T, Rx55E3T},      // 166/266
 320          {PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x00, 0x00, Rx54E3T, Rx55E3T}       // 166/333
 321          },
 322 // cpu266
 323         {
 324          {PH0_2_2_2, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x07, 0x00, Rx54L1T, Rx55L1T},      // 266/100
 325          {PH1_1_1_1, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x0f, 0x00, Rx54L1T, Rx55L1T},      // 266/133
 326          {PH3_2_3_2, PH0_0_0_2, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x1f, 0x00, Rx54E1T, Rx55E1T},      // 266/166
 327          {PH3_2_2_3, PH0_0_2_2, PH0_0_0_0, PH1_0_0_1, PH0_0_0_0, PH0_0_0_0, 0x3f, 0x00, Rx54E2T, Rx55E2T},      // 266/200
 328          {PH2_2_2_2, PH2_2_2_2, PH0_0_0_0, PH1_1_1_1, PH1_1_1_1, PH0_0_0_0, 0xff, 0x00, Rx54E3T, Rx55E3T},      // 266/266
 329          {PH0_0_1_1, PH0_1_1_1, PH0_0_1_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x9c, 0x03, Rx54E3T, Rx55E3T}       // 266/333
 330          },
 331 // cpu333
 332         {
 333          {PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x00, 0x00, Rx54L1T, Rx55L1T},      // 333/100  ;DO NOT Support
 334          {PH2_2_2_2, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x0f, 0x00, Rx54L1T, Rx55L1T},      // 333/133
 335          {PH3_3_3_3, PH0_0_0_3, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x1f, 0x00, Rx54E0T, Rx55E0T},      // 333/166
 336          {PH2_3_3_2, PH0_0_3_3, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x3f, 0x00, Rx54E1T, Rx55E1T},      // 333/200
 337          {PH3_3_3_3, PH3_3_3_3, PH0_0_0_0, PH2_1_1_1, PH2_1_1_1, PH0_0_0_0, 0xff, 0x00, Rx54E3T, Rx55E3T},      // 333/266
 338          {PH2_2_2_2, PH2_2_2_2, PH0_0_2_2, PH2_2_2_2, PH2_2_2_2, PH0_0_2_2, 0xff, 0x03, Rx54E3T, Rx55E3T}       // 333/333
 339          }
 340 };
 341
 342 static const u8 PT894_64bit_DELAYMD1_RCONV0[6][6][PT894_RDRDY_TBL_Width] =
 343 //    -----------------------------------------------------------------------------------------------------------------
 344 //    RX60           RX61           RX62            RX63           RX64       RX65           RX66  RX67   RX54[3,1]  RX55[3,1]    CPU/DRAM
 345 //    LN4:1          LN8:5          LN10:9          QW4:1          QW8:5      QW10:9     WS8:1 WS10:9 RFASTH     RRRDYH3E
 346 //                                                                                                                            RCONV          RHTSEL
 347 //    -----------------------------------------------------------------------------------------------------------------
 348 {
 349 // cpu100
 350         {
 351          {PH0_2_2_2, PH0_0_0_0, PH0_0_0_0, PH0_1_1_1, PH0_0_0_0, PH0_0_0_0, 0x07, 0x00, Rx54E3T, Rx55E3T},      // 100/100
 352          {PH1_0_0_1, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x06, 0x00, Rx54E3T, Rx55E3T},      // 100/133
 353          {PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x00, 0x00, Rx54E3T, Rx55E3T},      // 100/166
 354          {PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x00, 0x00, Rx54E3T, Rx55E3T},      // 100/200
 355          {PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x00, 0x00, Rx54E3T, Rx55E3T},      // ;100/266
 356          {PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x00, 0x00, Rx54E3T, Rx55E3T}       // 100/333
 357          },
 358 // cpu133
 359         {
 360          {PH0_3_3_3, PH0_0_0_0, PH0_0_0_0, PH0_1_1_1, PH0_0_0_0, PH0_0_0_0, 0x07, 0x00, Rx54E2T, Rx55E2T},      // 133/100
 361          {PH2_2_2_2, PH0_0_0_0, PH0_0_0_0, PH1_1_1_1, PH0_0_0_0, PH0_0_0_0, 0x0f, 0x00, Rx54E3T, Rx55E3T},      // 133/133
 362          {PH1_0_1_1, PH0_0_0_1, PH0_0_0_0, PH1_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x1c, 0x00, Rx54E3T, Rx55E3T},      // 133/166
 363          {PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x09, 0x00, Rx54E3T, Rx55E3T},      // 133/200
 364          {PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x00, 0x00, Rx54E3T, Rx55E3T},      // 133/266
 365          {PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x00, 0x00, Rx54E3T, Rx55E3T}       // 133/333
 366          },
 367 // cpu200
 368         {
 369          {PH0_2_2_2, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x07, 0x00, Rx54L1T, Rx55L1T},      // 200/100
 370          {PH3_3_3_3, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x0f, 0x00, Rx54E1T, Rx55E1T},      // 200/133
 371          {PH2_2_3_3, PH0_0_0_2, PH0_0_0_0, PH1_0_1_1, PH0_0_0_1, PH0_0_0_0, 0x1f, 0x00, Rx54E2T, Rx55E2T},      // 200/166
 372          {PH3_3_3_3, PH0_0_3_3, PH0_0_0_0, PH2_2_2_2, PH0_0_2_2, PH0_0_0_0, 0x3f, 0x00, Rx54E3T, Rx55E3T},      // 200/200
 373          {PH0_0_1_1, PH0_0_1_1, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0xcc, 0x00, Rx54E3T, Rx55E3T},      // 200/266
 374          {PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x00, 0x00, Rx54E3T, Rx55E3T}       // 200/333
 375          },
 376 // cpu166
 377         {
 378          {PH0_3_3_3, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x07, 0x00, Rx54E1T, Rx55E1T},      // 166/100
 379          {PH2_2_3_3, PH0_0_0_0, PH0_0_0_0, PH1_0_1_1, PH0_0_0_0, PH0_0_0_0, 0x0f, 0x00, Rx54E2T, Rx55E2T},      // 166/133
 380          {PH2_2_2_2, PH0_0_0_2, PH0_0_0_0, PH2_2_2_2, PH0_0_0_2, PH0_0_0_0, 0x1f, 0x00, Rx54E3T, Rx55E3T},      // 166/166
 381          {PH1_1_1_1, PH0_0_1_1, PH0_0_0_0, PH1_0_0_0, PH0_0_0_1, PH0_0_0_0, 0x39, 0x00, Rx54E3T, Rx55E3T},      // 166/200
 382          {PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x00, 0x00, Rx54E3T, Rx55E3T},      // 166/266
 383          {PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x00, 0x00, Rx54E3T, Rx55E3T}       // 166/333
 384          },
 385 // cpu266
 386         {
 387          {PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x00, 0x00, Rx54L1T, Rx55L1T},      // 266/100  ;DO NOT Support
 388          {PH2_2_2_2, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x0f, 0x00, Rx54L1T, Rx55L1T},      // 266/133
 389          {PH2_2_1_2, PH0_0_0_1, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x1f, 0x00, Rx54E0T, Rx55E0T},      // 266/166
 390          {PH3_3_3_3, PH0_0_3_3, PH0_0_0_0, PH1_1_1_1, PH0_0_1_1, PH0_0_0_0, 0x3f, 0x00, Rx54E2T, Rx55E2T},      // 266/200
 391          {PH3_3_3_3, PH3_3_3_3, PH0_0_0_0, PH2_2_2_2, PH2_2_2_2, PH0_0_0_0, 0xff, 0x00, Rx54E3T, Rx55E3T},      // 266/266
 392          {PH1_1_1_1, PH1_1_1_1, PH0_0_1_1, PH0_0_0_1, PH0_0_1_1, PH0_0_1_0, 0x73, 0x02, Rx54E3T, Rx55E3T}       // 266/333
 393          },
 394 // cpu333
 395         {
 396          {PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x00, 0x00, Rx54L1T, Rx55L1T},      // 333/100  ;DO NOT Support
 397          {PH3_3_3_3, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x0f, 0x00, Rx54L1T, Rx55L1T},      // 333/133
 398          {PH2_2_2_2, PH0_0_0_2, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x1f, 0x00, Rx54L1T, Rx55L1T},      // 333/166
 399          {PH2_2_2_2, PH0_0_2_2, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x3f, 0x00, Rx54E1T, Rx55E1T},      // 333/200
 400          {PH2_3_2_2, PH2_3_2_2, PH0_0_0_0, PH0_1_1_0, PH0_1_1_0, PH0_0_0_0, 0xff, 0x00, Rx54E2T, Rx55E2T},      // 333/266
 401          {PH3_3_3_3, PH3_3_3_3, PH0_0_3_3, PH2_2_2_2, PH2_2_2_2, PH0_0_2_2, 0xff, 0x03, Rx54E3T, Rx55E3T}       // 333/333
 402          }
 403 };
 404
 405 void DRAMDRDYSetting(DRAM_SYS_ATTR * DramAttr)
 406 {
 407         u8 Data, CL, RDRPH;
 408         u8 CpuFreq, DramFreq;
 409         u8 ProgData[PT894_RDRDY_TBL_Width];
 410         u8 DelayMode;
 411         u8 DrdyMode;
 412         u8 Index;
 413
 414         /*
 415            this function has 3 switchs, correspond to 3 level of Drdy setting.
 416            0:Slowest, 1:Default, 2:Optimize
 417            you can only open one switch
 418          */
 419 #if 1                           //this is slowest
 420         //  0 -> Slowest
 421         //Write slowest value to register
 422
 423         Data = 0xAA;
 424         pci_write_config8(PCI_DEV(0, 0, 2), 0x60, Data);
 425
 426         Data = 0x0A;
 427         pci_write_config8(PCI_DEV(0, 0, 2), 0x61, Data);
 428
 429         Data = 0x00;
 430         pci_write_config8(PCI_DEV(0, 0, 2), 0x62, Data);
 431
 432         Data = 0xAA;
 433         pci_write_config8(PCI_DEV(0, 0, 2), 0x63, Data);
 434
 435         Data = 0x0A;
 436         pci_write_config8(PCI_DEV(0, 0, 2), 0x64, Data);
 437
 438         Data = 0x00;
 439         pci_write_config8(PCI_DEV(0, 0, 2), 0x65, Data);
 440
 441         Data = 0x00;
 442         pci_write_config8(PCI_DEV(0, 0, 2), 0x66, Data);
 443
 444         Data = 0x00;
 445         pci_write_config8(PCI_DEV(0, 0, 2), 0x67, Data);
 446
 447         Data = pci_read_config8(PCI_DEV(0, 0, 2), 0x54);
 448         Data = Data & 0xF5;
 449         Data |= 0x08;
 450         pci_write_config8(PCI_DEV(0, 0, 2), 0x54, Data);
 451
 452         //Data=pci_read_config8(PCI_DEV(0,0,2), 0x55);
 453         //Data = Data & (~0x20);
 454         //pci_write_config8(PCI_DEV(0,0,2), 0x55, Data);
 455
 456         //enable drdy timing
 457         Data = pci_read_config8(PCI_DEV(0, 0, 2), 0x51);
 458         Data = Data | 0x80;
 459         pci_write_config8(PCI_DEV(0, 0, 2), 0x51, Data);
 460 #endif
 461 #if 0                           //default
 462         {
 463                 //disable drdy timing
 464                 Data = pci_read_config8(PCI_DEV(0, 0, 2), 0x51);
 465                 Data = Data & 0x7F;
 466                 pci_write_config8(PCI_DEV(0, 0, 2), 0x51, Data);
 467         }
 468 #endif
 469 #if 0                           //  2:Optimize
 470         //CL :reg6x[2:0]
 471         Data = pci_read_config8(MEMCTRL, 0x62);
 472         CL = Data & 0x07;
 473
 474         //RDRPH: reg7B[6:4]
 475         Data = pci_read_config8(MEMCTRL, 0x7B);
 476         RDRPH = (Data & 0x70) >> 4;
 477
 478         //CpuFreq: F2Reg54[7:5]
 479         Data = pci_read_config8(PCI_DEV(0, 0, 2), 0x54);
 480         CpuFreq = (Data & 0xE0) >> 5;
 481
 482         //DramFreq:F3Reg90[2:0]
 483         Data = pci_read_config8(MEMCTRL, 0x90);
 484         DramFreq = Data & 0x07;
 485
 486         DelayMode = CL + RDRPH; // RDELAYMD = bit0 of (CAS Latency + RDRPH)
 487         DelayMode &= 0x01;
 488
 489         //In 364, there is no 128 bit
 490         if (DelayMode == 1) {   // DelayMode 1
 491                 for (Index = 0; Index < PT894_RDRDY_TBL_Width; Index++)
 492                         ProgData[Index] =
 493                             PT894_64bit_DELAYMD1_RCONV0[CpuFreq][DramFreq]
 494                             [Index];
 495         } else {                // DelayMode 0
 496                 for (Index = 0; Index < PT894_RDRDY_TBL_Width; Index++)
 497                         ProgData[Index] =
 498                             PT894_64bit_DELAYMD0_RCONV0[CpuFreq][DramFreq]
 499                             [Index];
 500         }
 501
 502         Data = ProgData[0];
 503         pci_write_config8(PCI_DEV(0, 0, 2), 0x60, Data);
 504
 505         Data = ProgData[1];
 506         pci_write_config8(PCI_DEV(0, 0, 2), 0x61, Data);
 507
 508         Data = ProgData[2];
 509         pci_write_config8(PCI_DEV(0, 0, 2), 0x62, Data);
 510
 511         Data = ProgData[3];
 512         pci_write_config8(PCI_DEV(0, 0, 2), 0x63, Data);
 513
 514         Data = ProgData[4];
 515         pci_write_config8(PCI_DEV(0, 0, 2), 0x64, Data);
 516
 517         Data = ProgData[5];
 518         pci_write_config8(PCI_DEV(0, 0, 2), 0x65, Data);
 519
 520         Data = ProgData[6];
 521         pci_write_config8(PCI_DEV(0, 0, 2), 0x66, Data);
 522
 523         Data = ProgData[7];
 524         pci_write_config8(PCI_DEV(0, 0, 2), 0x67, Data);
 525
 526         Data = pci_read_config8(PCI_DEV(0, 0, 2), 0x54);
 527         Data = (Data & 0xF5) | ProgData[8];
 528         pci_write_config8(PCI_DEV(0, 0, 2), 0x54, Data);
 529
 530         Data = pci_read_config8(PCI_DEV(0, 0, 2), 0x55);
 531         Data = Data & (~0x22) | ProgData[9];
 532         pci_write_config8(PCI_DEV(0, 0, 2), 0x62, Data);
 533
 534         //enable drdy timing
 535         Data = pci_read_config8(PCI_DEV(0, 0, 2), 0x51);
 536         Data = Data | 0x80;
 537         pci_write_config8(PCI_DEV(0, 0, 2), 0x51, Data);
 538 #endif
 539 }
 540
 541 /*This routine process the ability for North Bridge side burst functionality
 542 There are 3 variances that are valid:
 543         1. DIMM BL=8, chipset BL=8
 544         2. DIMM BL=4, chipset BL=4
 545         3. DIMM BL=4, chipset BL=8 (only happened on Dual channel)
 546      Device 0 function 2 HOST:REG54[4] must be 1 when 128-bit mode.
 547 Since DIMM will be initialized  in each rank individually,
 548         1.If all DIMM BL=4, DIMM will initialize BL=4 first,
 549           then check dual_channel flag to enable VIA_NB2HOST_REG54[4].
 550         2.If all DIMM BL=8, DIMM will initialize BL=8 first,
 551           then check dual_channel flag for re-initialize DIMM BL=4.
 552           also VIA_NB2HOST_REG54[4] need        to be enabled.
 553 Chipset_BL8==>chipset side can  set burst length=8
 554 two register need to set
 555  1. Device 0 function 2 HOST:REG54[4]
 556  2. Device 0 function 3 DRAM:REG6C[3]
 557 */
 558 void DRAMBurstLength(DRAM_SYS_ATTR * DramAttr)
 559 {
 560         u8 Data, BL;
 561         u8 Sockets;
 562         /*SPD byte16 bit3,2 describes the burst length supported. bit3=1 support BL=8 bit2=1 support BL=4 */
 563         BL = 0x0c;
 564         for (Sockets = 0; Sockets < 2; Sockets++) {
 565                 if (DramAttr->DimmInfo[Sockets].bPresence) {
 566                         BL &=
 567                             (DramAttr->
 568                              DimmInfo[Sockets].SPDDataBuf
 569                              [SPD_SDRAM_BURSTLENGTH]);
 570                 }
 571         }
 572
 573         /*D0F3Rx6c bit3 CHA SDRAM effective burst length, for 64bit mode ranks =0 BL=4 ; =1 BL=8 */
 574
 575         if (BL & 0x08)          /*All Assembly support BL=8 */
 576                 BL = 0x8;       /*set bit3 */
 577         else
 578                 BL = 0x00;      /*clear bit3 */
 579
 580         Data = pci_read_config8(MEMCTRL, 0x6c);
 581         Data = (u8) ((Data & 0xf7) | BL);
 582
 583 #if ENABLE_CHB
 584         if (DramAttr->RankNumChB > 0) {
 585                 BL = DramAttr->DimmInfo[2].SPDDataBuf[SPD_SDRAM_BURSTLENGTH];
 586                 //Rx6c[1], CHB burst length
 587                 if (BL & 0x08)  /*CHB support BL=8 */
 588                         BL = 0x2;       /*set bit1 */
 589                 else
 590                         BL = 0x00;      /*clear bit1 */
 591
 592                 Data = (Data & 0xFD) | BL;
 593         }
 594 #endif
 595         pci_write_config8(MEMCTRL, 0x6c, Data);
 596 }