src/northbridge/via/vt8623/raminit.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2005 Nick Barker <nick.barker9@btinternet.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  19  */
  20
  21 /*
  22   Automatically detect and set up ddr dram on the CLE266 chipset.
  23   Assumes DDR memory, though chipset also supports SDRAM
  24   Assumes at least 266Mhz memory as no attempt is made to clock
  25   the chipset down if slower memory is installed.
  26   So far tested on:
  27         256 Mb 266Mhz 1 Bank (i.e. single sided)
  28         256 Mb 266Mhz 2 Bank (i.e. double sided)
  29         512 Mb 266Mhz 2 Bank (i.e. double sided)
  30 */
  31 /* ported and enhanced from assembler level code in coreboot v1 */
  32
  33 #include <spd.h>
  34 #include <cpu/x86/mtrr.h>
  35 #include "raminit.h"
  36
  37
  38
  39 void dimm_read(unsigned long bank,unsigned long x)
  40 {
  41         //unsigned long eax;
  42         volatile unsigned long y;
  43         //eax =  x;
  44         y = * (volatile unsigned long *) (x+ bank) ;
  45
  46 }
  47
  48
  49 void
  50 dumpnorth(device_t north)
  51 {
  52         uint16_t r, c;
  53         for(r = 0; r < 256; r += 16) {
  54                 print_debug_hex8(r);
  55                 print_debug(":");
  56                 for(c = 0; c < 16; c++) {
  57                         print_debug_hex8(pci_read_config8(north, r+c));
  58                         print_debug(" ");
  59                 }
  60                 print_debug("\n");
  61   }
  62 }
  63 void print_val(char *str, int val)
  64 {
  65         print_debug(str);
  66         print_debug_hex8(val);
  67 }
  68
  69 static void ddr_ram_setup(const struct mem_controller *ctrl)
  70 {
  71         device_t north = (device_t) 0;
  72         uint8_t b, c, bank;
  73         uint16_t i;
  74         unsigned long bank_address;
  75
  76         print_debug("vt8623 init starting\n");
  77         north = pci_locate_device(PCI_ID(0x1106, 0x3123), 0);
  78         north = 0;
  79
  80
  81         pci_write_config8(north,0x75,0x08);
  82
  83         /* setup cpu */
  84         pci_write_config8(north,0x50,0xc8);
  85         pci_write_config8(north,0x51,0xde);
  86         pci_write_config8(north,0x52,0xcf);
  87         pci_write_config8(north,0x53,0x88);
  88         pci_write_config8(north,0x55,0x04);
  89
  90 /*
  91     DRAM MA Map Type  Device 0  Offset 58
  92
  93     Determine memory addressing based on the module's memory technology and
  94     arrangement.  See Table 4-9 of Intel's 82443GX datasheet for details.
  95
  96     Bank 1/0 MA map type   58[7-5]
  97     Bank 1/0 command rate  58[4]
  98     Bank 3/2 MA map type   58[3-1]
  99     Bank 3/2 command rate  58[0]
 100
 101
 102     Read SPD byte 17, Number of banks on SDRAM device.
 103 */
 104         c = 0;
 105         b = smbus_read_byte(DIMM0,17);
 106         print_val("Detecting Memory\nNumber of Banks ",b);
 107
 108         if( b != 2 ){            // not 16 Mb type
 109
 110 /*
 111     Read SPD byte 3, Number of row addresses.
 112 */
 113                 b = smbus_read_byte(DIMM0,3);
 114                 print_val("\nNumber of Rows ",b);
 115                 if( b >= 0x0d ){        // not 64/128Mb (rows <=12)
 116
 117 /*
 118     Read SPD byte 13, Primary DRAM width.
 119 */
 120                         b = smbus_read_byte(DIMM0,13);
 121                         print_val("\nPriamry DRAM width",b);
 122                         if( b != 4 )   // mot 64/128Mb (x4)
 123                                 c = 0x80;  // 256Mb
 124                 }
 125
 126 /*
 127     64/128Mb chip
 128
 129     Read SPD byte 4, Number of column addresses.
 130 */
 131                 b = smbus_read_byte(DIMM0,4);
 132                 print_val("\nNo Columns ",b);
 133                 if( b == 10 || b == 11 ) c |= 0x60;   // 10/11 bit col addr
 134                 if( b == 9 ) c |= 0x40;           // 9 bit col addr
 135                 if( b == 8 ) c |= 0x20;           // 8 bit col addr
 136
 137         }
 138         print_val("\nMA type ",c);
 139         pci_write_config8(north,0x58,c);
 140
 141 /*
 142     DRAM bank size.  See 4.3.1 pg 35
 143
 144     5a->5d  set to end address for each bank.  1 bit == 16MB
 145     5a = bank 0
 146     5b = bank 0 + b1
 147     5c = bank 0 + b1 + b2
 148     5d = bank 0 + b1 + b2 + b3
 149 */
 150
 151 // Read SPD byte 31 Module bank density
 152         c = 0;
 153         b = smbus_read_byte(DIMM0,31);
 154         if( b & 0x02 ) c = 0x80;         // 2GB
 155         else if( b & 0x01) c = 0x40;     // 1GB
 156         else if( b & 0x80) c = 0x20;     // 512Mb
 157         else if( b & 0x40) c = 0x10;     // 256Mb
 158         else if( b & 0x20) c = 0x08;     // 128Mb
 159         else if( b & 0x10) c = 0x04;     // 64Mb
 160         else if( b & 0x08) c = 0x02;     // 32Mb
 161         else if( b & 0x04) c = 0x01;     // 16Mb / 4Gb
 162         else c = 0x01;                   // Error, use default
 163
 164
 165         print_val("\nBank 0 (*16 Mb) ",c);
 166
 167         // set bank zero size
 168         pci_write_config8(north,0x5a,c);
 169         // SPD byte 5  # of physical banks
 170         b = smbus_read_byte(DIMM0,5);
 171
 172         print_val("\nNo Physical Banks ",b);
 173         if( b == 2)
 174                 c <<=1;
 175
 176         print_val("\nTotal Memory (*16 Mb) ",c);
 177         // set banks 1,2,3
 178         pci_write_config8(north,0x5b,c);
 179         pci_write_config8(north,0x5c,c);
 180         pci_write_config8(north,0x5d,c);
 181
 182
 183         /* Read SPD byte 18 CAS Latency */
 184         b = smbus_read_byte(DIMM0,18);
 185         print_debug("\nCAS Supported ");
 186         if(b & 0x04)
 187                 print_debug("2 ");
 188         if(b & 0x08)
 189                 print_debug("2.5 ");
 190         if(b & 0x10)
 191                 print_debug("3");
 192         print_val("\nCycle time at CL X     (nS)",smbus_read_byte(DIMM0,9));
 193         print_val("\nCycle time at CL X-0.5 (nS)",smbus_read_byte(DIMM0,23));
 194         print_val("\nCycle time at CL X-1   (nS)",smbus_read_byte(DIMM0,25));
 195
 196
 197         if( b & 0x10 ){             // DDR offering optional CAS 3
 198                 print_debug("\nStarting at CAS 3");
 199                 c = 0x30;
 200                 /* see if we can better it */
 201                 if( b & 0x08 ){     // DDR mandatory CAS 2.5
 202                         if( smbus_read_byte(DIMM0,23) <= 0x75 ){ // we can manage 133Mhz at CAS 2.5
 203                                 print_debug("\nWe can do CAS 2.5");
 204                                 c = 0x20;
 205                         }
 206                 }
 207                 if( b & 0x04 ){     // DDR mandatory CAS 2
 208                         if( smbus_read_byte(DIMM0,25) <= 0x75 ){ // we can manage 133Mhz at CAS 2
 209                                 print_debug("\nWe can do CAS 2");
 210                                 c = 0x10;
 211                         }
 212                 }
 213         }else{                     // no optional CAS values just 2 & 2.5
 214                 print_debug("\nStarting at CAS 2.5");
 215                 c = 0x20;          // assume CAS 2.5
 216                 if( b & 0x04){      // Should always happen
 217                         if( smbus_read_byte(DIMM0,23) <= 0x75){ // we can manage 133Mhz at CAS 2
 218                                 print_debug("\nWe can do CAS 2");
 219                                 c = 0x10;
 220                         }
 221                 }
 222         }
 223
 224
 225
 226 /*
 227     DRAM Timing  Device 0  Offset 64
 228
 229     Row pre-charge  64[7]
 230     RAS Pulse width 64[6]
 231     CAS Latency     64[5,4]
 232
 233          SDR  DDR
 234       00  1T   -
 235       01  2T   2T
 236       10  3T   2.5T
 237       11  -    3T
 238
 239     RAS/CAS delay   64[2]
 240     Bank Interleave 64[1,0]
 241
 242
 243     Determine row pre-charge time (tRP)
 244
 245     T    nS    SPD*4   SPD
 246     1T   7.5   0x1e
 247     2T   15    0x3c
 248     3T   22.5  0x5a
 249     4T   30            0x1e
 250     5T   37.5          0x25 .5?
 251     6T   45            0x2d
 252
 253
 254     Read SPD byte 27, min row pre-charge time.
 255 */
 256
 257         b = smbus_read_byte(DIMM0,27);
 258         print_val("\ntRP ",b);
 259         if( b > 0x3c )           // set tRP = 3T
 260                 c |= 0x80;
 261
 262
 263 /*
 264     Determine RAS to CAS delay (tRCD)
 265
 266     Read SPD byte 29, min row pre-charge time.
 267 */
 268
 269         b = smbus_read_byte(DIMM0,29);
 270         print_val("\ntRCD ",b);
 271         if( b > 0x3c )           // set tRCD = 3T
 272                 c |= 0x04;
 273
 274 /*
 275     Determine RAS pulse width (tRAS)
 276
 277
 278     Read SPD byte 30, device min active to pre-charge time.
 279 */
 280
 281         b = smbus_read_byte(DIMM0,30);
 282         print_val("\ntRAS ",b);
 283         if( b > 0x25 )           // set tRAS = 6T
 284                 c |= 0x40;
 285
 286
 287 /*
 288     Determine bank interleave
 289
 290     Read SPD byte 17, Number of banks on SDRAM device.
 291 */
 292         b = smbus_read_byte(DIMM0,17);
 293         if( b == 4) c |= 0x02;
 294         else if (b == 2) c |= 0x01;
 295
 296
 297         /* set DRAM timing for all banks */
 298         pci_write_config8(north,0x64,c);
 299
 300         /* set DRAM type to DDR */
 301         pci_write_config8(north,0x60,0x02);
 302
 303
 304         /* DRAM arbitration timer */
 305         pci_write_config8(north,0x65,0x32);
 306
 307
 308 /*
 309     CPU Frequency  Device 0 Offset 54
 310
 311     CPU Frequency          54[7,6]  bootstraps at 0xc0 (133Mhz)
 312     DRAM burst length = 8  54[5]
 313 */
 314         pci_write_config8(north,0x54,0xe0);
 315
 316
 317 /*
 318     DRAM Clock  Device 0 Offset 69
 319
 320     DRAM/CPU speed      69[7,6]  (leave at default 00 == CPU)
 321     Controller que > 2  69[5]
 322     Controller que != 4 69[4]
 323     DRAM 8k page size   69[3]
 324     DRAM 4k page size   69[2]
 325     Multiple page mode  69[0]
 326 */
 327
 328         pci_write_config8(north,0x69,0x2d);
 329
 330         /* Delay >= 100ns after DRAM Frequency adjust, See 4.1.1.3 pg 15 */
 331         udelay(200);
 332
 333
 334         /* Enable CKE */
 335         pci_write_config8(north,0x6b,0x10);
 336         udelay(200);
 337
 338         /* Disable DRAM refresh */
 339         pci_write_config8(north,0x6a,0x0);
 340
 341
 342         /* Set drive for 1 bank DDR  (Table 4.4.2, pg 40) */
 343         pci_write_config8(north,0x6d,0x044);
 344         pci_write_config8(north,0x67,0x3a);
 345
 346         b = smbus_read_byte(DIMM0,5); // SPD byte 5  # of physical banks
 347         if( b > 1) {
 348                 // Increase drive control when there is more than 1 physical bank
 349                 pci_write_config8(north,0x6c,0x84);   // Drive control: MA, DQS, MD/CKE
 350                 pci_write_config8(north,0x6d,0x55);   // DC: Early clock select, DQM, CS#, MD
 351         }
 352         /* place frame buffer on last bank */
 353         if( !b) b++;     // make sure at least 1 bank reported
 354         pci_write_config8(north,0xe3,b-1);
 355
 356         for( bank = 0 , bank_address=0; bank < b ; bank++){
 357 /*
 358     DDR init described in Via BIOS Porting Guide.  Pg 28 (4.2.3.1)
 359 */
 360
 361
 362                 /* NOP command enable */
 363                 pci_write_config8(north,0x6b,0x11);
 364
 365                 /* read a double word from any address of the dimm */
 366                 dimm_read(bank_address,0x1f000);
 367                 //udelay(200);
 368
 369                 /* All bank precharge Command Enable */
 370                 pci_write_config8(north,0x6b,0x12);
 371                 dimm_read(bank_address,0x1f000);
 372
 373
 374                 /* MSR Enable */
 375                 pci_write_config8(north,0x6b,0x13);
 376                 dimm_read(bank_address,0x2000);
 377                 udelay(1);
 378                 dimm_read(bank_address,0x800);
 379                 udelay(1);
 380
 381                 /* All banks precharge Command Enable */
 382                 pci_write_config8(north,0x6b,0x12);
 383                 dimm_read(bank_address,0x1f200);
 384
 385                 /* CBR Cycle Enable */
 386                 pci_write_config8(north,0x6b,0x14);
 387
 388                 /* Read 8 times */
 389                 dimm_read(bank_address,0x1f300);
 390                 udelay(100);
 391                 dimm_read(bank_address,0x1f400);
 392                 udelay(100);
 393                 dimm_read(bank_address,0x1f500);
 394                 udelay(100);
 395                 dimm_read(bank_address,0x1f600);
 396                 udelay(100);
 397                 dimm_read(bank_address,0x1f700);
 398                 udelay(100);
 399                 dimm_read(bank_address,0x1f800);
 400                 udelay(100);
 401                 dimm_read(bank_address,0x1f900);
 402                 udelay(100);
 403                 dimm_read(bank_address,0x1fa00);
 404                 udelay(100);
 405
 406                 /* MSR Enable */
 407                 pci_write_config8(north,0x6b,0x13);
 408
 409 /*
 410     Mode Register Definition
 411     with adjustement so that address calculation is correct - 64 bit technology, therefore
 412     a0-a2 refer to byte within a 64 bit long word, and a3 is the first address line presented
 413     to DIMM as a row or column address.
 414
 415     MR[9-7]   CAS Latency
 416     MR[6]     Burst Type 0 = sequential, 1 = interleaved
 417     MR[5-3]   burst length 001 = 2, 010 = 4, 011 = 8, others reserved
 418     MR[0-2]   dont care
 419
 420     CAS Latency
 421     000       reserved
 422     001       reserved
 423     010       2
 424     011       3
 425     100       reserved
 426     101       1.5
 427     110       2.5
 428     111       reserved
 429
 430     CAS 2     0101011000 = 0x158
 431     CAS 2.5   1101011000 = 0x358
 432     CAS 3     0111011000 = 0x1d8
 433
 434 */
 435                 c = pci_read_config8(north,0x64);
 436                 if( (c & 0x30) == 0x10 )
 437                         dimm_read(bank_address,0x150);
 438                 else if((c & 0x30) == 0x20 )
 439                         dimm_read(bank_address,0x350);
 440                 else
 441                         dimm_read(bank_address,0x1d0);
 442
 443                 //dimm_read(bank_address,0x350);
 444
 445                 /* Normal SDRAM Mode */
 446                 pci_write_config8(north,0x6b,0x58 );
 447
 448
 449                 bank_address = pci_read_config8(north,0x5a+bank) * 0x1000000;
 450         } // end of for each bank
 451
 452         /* Adjust DQS (data strobe output delay). See 4.2.3.2 pg 29 */
 453         pci_write_config8(north,0x66,0x41);
 454
 455         /* determine low bond */
 456         if( b == 2)
 457                 bank_address = pci_read_config8(north,0x5a) * 0x1000000;
 458         else
 459                 bank_address = 0;
 460
 461         for(i = 0 ; i < 0x0ff; i++){
 462                 c = i ^ (i>>1);                 // convert to gray code
 463                 pci_write_config8(north,0x68,c);
 464                 // clear
 465                 *(volatile unsigned long*)(0x4000) = 0;
 466                 *(volatile unsigned long*)(0x4100+bank_address) = 0;
 467                 *(volatile unsigned long*)(0x4200) = 0;
 468                 *(volatile unsigned long*)(0x4300+bank_address) = 0;
 469                 *(volatile unsigned long*)(0x4400) = 0;
 470                 *(volatile unsigned long*)(0x4500+bank_address) = 0;
 471
 472
 473                 // fill
 474                 *(volatile unsigned long*)(0x4000) = 0x12345678;
 475                 *(volatile unsigned long*)(0x4100+bank_address) = 0x81234567;
 476                 *(volatile unsigned long*)(0x4200) = 0x78123456;
 477                 *(volatile unsigned long*)(0x4300+bank_address) = 0x67812345;
 478                 *(volatile unsigned long*)(0x4400) = 0x56781234;
 479                 *(volatile unsigned long*)(0x4500+bank_address) = 0x45678123;
 480
 481                         // verify
 482                 if( *(volatile unsigned long*)(0x4000) != 0x12345678)
 483                         continue;
 484
 485                 if( *(volatile unsigned long*)(0x4100+bank_address) != 0x81234567)
 486                         continue;
 487
 488                 if( *(volatile unsigned long*)(0x4200) != 0x78123456)
 489                         continue;
 490
 491                 if( *(volatile unsigned long*)(0x4300+bank_address) != 0x67812345)
 492                         continue;
 493
 494                 if( *(volatile unsigned long*)(0x4400) != 0x56781234)
 495                         continue;
 496
 497                 if( *(volatile unsigned long*)(0x4500+bank_address) != 0x45678123)
 498                         continue;
 499
 500                 // if everything verified then found low bond
 501                 break;
 502
 503         }
 504         print_val("\nLow Bond ",i);
 505         if( i < 0xff ){
 506                 c = i++;
 507                 for(  ; i <0xff ; i++){
 508                         pci_write_config8(north,0x68,i ^ (i>>1) );
 509
 510                         // clear
 511                         *(volatile unsigned long*)(0x8000) = 0;
 512                         *(volatile unsigned long*)(0x8100+bank_address) = 0;
 513                         *(volatile unsigned long*)(0x8200) = 0x0;
 514                         *(volatile unsigned long*)(0x8300+bank_address) = 0;
 515                         *(volatile unsigned long*)(0x8400) = 0x0;
 516                         *(volatile unsigned long*)(0x8500+bank_address) = 0;
 517
 518                         // fill
 519                         *(volatile unsigned long*)(0x8000) = 0x12345678;
 520                         *(volatile unsigned long*)(0x8100+bank_address) = 0x81234567;
 521                         *(volatile unsigned long*)(0x8200) = 0x78123456;
 522                         *(volatile unsigned long*)(0x8300+bank_address) = 0x67812345;
 523                         *(volatile unsigned long*)(0x8400) = 0x56781234;
 524                         *(volatile unsigned long*)(0x8500+bank_address) = 0x45678123;
 525
 526                         // verify
 527                         if( *(volatile unsigned long*)(0x8000) != 0x12345678)
 528                                 break;
 529
 530                         if( *(volatile unsigned long*)(0x8100+bank_address) != 0x81234567)
 531                                 break;
 532
 533                         if( *(volatile unsigned long*)(0x8200) != 0x78123456)
 534                                 break;
 535
 536                         if( *(volatile unsigned long*)(0x8300+bank_address) != 0x67812345)
 537                                 break;
 538
 539                         if( *(volatile unsigned long*)(0x8400) != 0x56781234)
 540                                 break;
 541
 542                         if( *(volatile unsigned long*)(0x8500+bank_address) != 0x45678123)
 543                                 break;
 544
 545                 }
 546                 print_val("  High Bond",i);
 547                 c = ((i - c)<<1)/3 +c;
 548                 print_val("  Setting DQS delay",c);
 549                 c = c ^ (c>>1);         // convert to gray code
 550                 pci_write_config8(north,0x68,c);
 551                 pci_write_config8(north,0x68,0x42);
 552         }else{
 553                 print_debug("Unable to determine low bond - Setting default\n");
 554                 pci_write_config8(north,0x68,0x59);
 555         }
 556
 557
 558         pci_write_config8(north,0x66,0x01);
 559         pci_write_config8(north,0x55,0x07);
 560
 561
 562
 563 /*
 564     DRAM refresh rate  Device 0 Offset 6a
 565
 566     Units of 16 DRAM clock cycles.  (See 4.4.1 pg 39)
 567
 568     Rx69 (DRAM freq)  Rx58 (chip tech)  Rx6a
 569
 570     133Mhz            64/128Mb          0x86
 571     133Mhz            256/512Mb         0x43
 572     100Mhz            64/128Mb          0x65
 573     100Mhz            256/512Mb         0x32
 574 */
 575
 576         b = pci_read_config8(north,0x58);
 577         if( b < 0x80 )   // 256 tech
 578                 pci_write_config8(north,0x6a,0x86);
 579         else
 580                 pci_write_config8(north,0x6a,0x43);
 581
 582         pci_write_config8(north,0x61,0xff);
 583         //pci_write_config8(north,0x67,0x22);
 584
 585         /* pci */
 586         pci_write_config8(north,0x70,0x82);
 587         pci_write_config8(north,0x73,0x01);
 588         pci_write_config8(north,0x76,0x50);
 589
 590
 591         pci_write_config8(north,0x71,0xc8);
 592
 593
 594         /* graphics aperture base */
 595
 596         pci_write_config8(north,0x13,0xd0);
 597
 598         //pci_write_config8(north,0xe1,0xdf);
 599         //pci_write_config8(north,0xe2,0x42);
 600         pci_write_config8(north,0xe0,0x00);
 601
 602         pci_write_config8(north,0x84,0x80);
 603         pci_write_config16(north,0x80,0x610f);
 604         pci_write_config32(north,0x88,0x00000002);
 605
 606
 607
 608         pci_write_config8(north,0xa8,0x04);
 609         pci_write_config8(north,0xac,0x2f);
 610         pci_write_config8(north,0xae,0x04);
 611
 612         print_debug("vt8623 done\n");
 613         dumpnorth(north);
 614
 615         print_debug("AGP\n");
 616         north = pci_locate_device(PCI_ID(0x1106, 0xb091), 0);
 617         pci_write_config32(north,0x20,0xddf0dc00);
 618         pci_write_config32(north,0x24,0xdbf0d800);
 619         pci_write_config8(north,0x3e,0x0c);
 620         //dumpnorth(north);
 621
 622         //print_err("VGA\n");
 623         //north = pci_locate_device(PCI_ID(0x1106, 0x3122), 0);
 624         //pci_write_config32(north,0x10,0xd8000008);
 625         //pci_write_config32(north,0x14,0xdc000000);
 626         //dumpnorth(north);
 627
 628 }