src/northbridge/via/vt8623/northbridge.c

   1 #include <console/console.h>
   2 #include <arch/io.h>
   3 #include <stdint.h>
   4 #include <device/device.h>
   5 #include <device/pci.h>
   6 #include <device/hypertransport.h>
   7 #include <device/pci_ids.h>
   8 #include <stdlib.h>
   9 #include <string.h>
  10 #include <bitops.h>
  11 #include <cpu/p6/mtrr.h>
  12 #include "chip.h"
  13 #include "northbridge.h"
  14
  15 /*
  16  * This fixup is based on capturing values from an Award bios.  Without
  17  * this fixup the DMA write performance is awful (i.e. hdparm -t /dev/hda is 20x
  18  * slower than normal, ethernet drops packets).
  19  * Apparently these registers govern some sort of bus master behavior.
  20  */
  21 static void norhbrige_init(device_t dev)
  22 {
  23         device_t fb_dev;
  24         unsigned long fb;
  25         unsigned char c;
  26
  27         printk_debug("VT8623 random fixup ...\n");
  28         pci_write_config8(dev,  0x0d, 0x08);
  29         pci_write_config8(dev,  0x70, 0x82);
  30         pci_write_config8(dev,  0x71, 0xc8);
  31         pci_write_config8(dev,  0x72, 0x00);
  32         pci_write_config8(dev,  0x73, 0x01);
  33         pci_write_config8(dev,  0x74, 0x01);
  34         pci_write_config8(dev,  0x75, 0x08);
  35         pci_write_config8(dev,  0x76, 0x52);
  36         pci_write_config8(dev,  0x13, 0xd0);
  37         pci_write_config8(dev,  0x84, 0x80);
  38         pci_write_config16(dev, 0x80, 0x610f);
  39         pci_write_config32(dev, 0x88, 0x00000002);
  40
  41         fb_dev = dev_find_device(PCI_VENDOR_ID_VIA, 0x3122, 0);
  42         if (fb_dev) {
  43                 /* Fixup GART and framebuffer addresses properly.
  44                  * First setup frame buffer properly.
  45                  */
  46                 fb = pci_read_config32(dev, 0x10);       /* Base addres of framebuffer */
  47                 printk_debug("Frame buffer at %8x\n",fb);
  48
  49                 c = pci_read_config8(dev, 0xe1) & 0xf0;  /* size of vga */
  50                 c |= fb>>28;  /* upper nibble of frame buffer address */
  51                 pci_write_config8(dev, 0xe1, c);
  52                 c = (fb>>20) | 1;                        /* enable framebuffer */
  53                 pci_write_config8(dev, 0xe0, c);
  54                 pci_write_config8(dev, 0xe2, 0x42);      /* 'cos award does */
  55         }
  56 }
  57
  58
  59 static struct device_operations northbridge_operations = {
  60         .read_resources   = pci_dev_read_resources,
  61         .set_resources    = pci_dev_set_resources,
  62         .enable_resources = pci_dev_enable_resources,
  63         .init             = northbridge_init,
  64         .scan_bus         = pci_scan_bridge,
  65         .ops_pci          = 0,
  66 };
  67
  68 static struct pci_driver northbridge_driver __pci_driver = {
  69         .ops = &northbridge_ops,
  70         .vendor = PCI_VENDOR_ID_VIA,
  71         .device = 0x3123,
  72 };
  73
  74 static void agp_init(device_t dev)
  75 {
  76         printk_debug("VT8623 AGP random fixup ...\n");
  77
  78         pci_write_config8(dev, 0x3e, 0x0c);
  79         pci_write_config8(dev, 0x40, 0x83);
  80         pci_write_config8(dev, 0x41, 0xc5);
  81         pci_write_config8(dev, 0x43, 0x44);
  82         pci_write_config8(dev, 0x44, 0x34);
  83         pci_write_config8(dev, 0x83, 0x02);
  84 }
  85
  86 static struct device_operations agp_operations = {
  87         .read_resources   = pci_bus_read_resources,
  88         .set_resources    = pci_dev_set_resources,
  89         .enable_resources = pci_bus_enable_resources,
  90         .init             = agp_init,
  91         .scan_bus         = pci_scan_bridge,
  92         .ops_pci          = 0,
  93 };
  94
  95 static struct pci_driver agp_driver __pci_driver = {
  96         .ops = &agp_ops,
  97         .vendor = PCI_VENDOR_ID_VIA,
  98         .device = 0xb091,
  99 };
 100
 101 static void vga_init(device_t dev)
 102 {
 103         unsigned long fb;
 104
 105         printk_debug("VGA random fixup ...\n");
 106         pci_write_config8(dev, 0x04, 0x07);
 107         pci_write_config8(dev, 0x0d, 0x20);
 108
 109         /* Set the vga mtrrs */
 110         add_var_mtrr( 0xd0000000 >> 10, 0x08000000>>10, MTRR_TYPE_WRCOMB);
 111         fb = pci_read_config32(dev,0x10); // get the fb address
 112         add_var_mtrr( fb>>10, 8192, MTRR_TYPE_WRCOMB);
 113 }
 114
 115 static struct device_operations vga_operations = {
 116         .read_resources   = pci_dev_read_resources,
 117         .set_resources    = pci_dev_set_resources,
 118         .enable_resources = pci_dev_enable_resources,
 119         .init             = vga_init,
 120         .ops_pci          = 0,
 121 };
 122
 123 static struct pci_driver vga_driver __pci_driver = {
 124         .ops = &vga_ops,
 125         .vendor = PCI_VENDOR_ID_VIA,
 126         .device = 0x3122,
 127 };
 128
 129
 130 #define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM)
 131
 132 static void pci_domain_read_resources(device_t dev)
 133 {
 134         struct resource *resource;
 135         unsigned reg;
 136
 137         /* Initialize the system wide io space constraints */
 138         resource = new_resource(dev, 0);
 139         resource->base  = 0x400;
 140         resource->limit = 0xffffUL;
 141         resource->flags = IORESOURCE_IO;
 142         compute_allocate_resource(&dev->link[0], resource,
 143                 IORESOURCE_IO, IORESOURCE_IO);
 144
 145         /* Initialize the system wide memory resources constraints */
 146         resource = new_resource(dev, 1);
 147         resource->limit = 0xffffffffULL;
 148         resource->flags = IORESOURCE_MEM;
 149         compute_allocate_resource(&dev->link[0], resource,
 150                 IORESOURCE_MEM, IORESOURCE_MEM);
 151 }
 152
 153 static void ram_resource(device_t dev, unsigned long index,
 154         unsigned long basek, unsigned long sizek)
 155 {
 156         struct resource *resource;
 157
 158         if (!sizek) {
 159                 return;
 160         }
 161         resource = new_resource(dev, index);
 162         resource->base  = ((resource_t)basek) << 10;
 163         resource->size  = ((resource_t)sizek) << 10;
 164         resource->flags =  IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
 165                 IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
 166 }
 167
 168 static const uint8_t ramregs[] = {0x5a, 0x5b, 0x5c, 0x5d };
 169
 170 static void pci_domain_set_resources(device_t dev)
 171 {
 172         struct resource *resource, *last;
 173         device_t mc_dev;
 174         uint32_t pci_tolm;
 175
 176         pci_tolm = 0xffffffffUL;
 177         last = &dev->resource[dev->resources];
 178         for(resource = &dev->resource[0]; resource < last; resource++)
 179         {
 180                 compute_allocate_resource(&dev->link[0], resource,
 181                         BRIDGE_IO_MASK, resource->flags & BRIDGE_IO_MASK);
 182
 183                 resource->flags |= IORESOURCE_STORED;
 184                 report_resource_stored(dev, resource, "");
 185
 186                 if ((resource->flags & IORESOURCE_MEM) &&
 187                         (pci_tolm > resource->base))
 188                 {
 189                         pci_tolm = resource->base;
 190                 }
 191         }
 192
 193         mc_dev = dev->link[0].children;
 194         if (mc_dev) {
 195                 unsigned long tomk, tolmk;
 196                 unsigned char rambits;
 197                 int i, idx;
 198
 199                 for(rambits = 0, i = 0; i < sizeof(ramregs)/sizeof(ramregs[0]); i++) {
 200                         unsigned char reg;
 201                         reg = pci_read_config8(mc_dev, ramregs[i]);
 202                         /* these are ENDING addresses, not sizes.
 203                          * if there is memory in this slot, then reg will be > rambits.
 204                          * So we just take the max, that gives us total.
 205                          * We take the highest one to cover for once and future linuxbios
 206                          * bugs. We warn about bugs.
 207                          */
 208                         if (reg > rambits)
 209                                 rambits = reg;
 210                         if (reg < rambits)
 211                                 printk_err("ERROR! register 0x%x is not set!\n",
 212                                         ramregs[i]);
 213                 }
 214                 printk_debug("I would set ram size to 0x%x Kbytes\n", (rambits)*16*1024);
 215                 tomk = ramreg*16*1024 - 32768;
 216                 /* Compute the top of Low memory */
 217                 tolmk = pci_tolm >> 10;
 218                 if (tolmk >= tomk) {
 219                         /* The PCI hole does does not overlap the memory.
 220                          */
 221                         tolmk = tomk;
 222                 }
 223                 /* Report the memory regions */
 224                 idx = 10;
 225                 ram_resource(dev, idx++, 0, 640);               /* first 640k */
 226                 ram_resource(dev, idx++, 768, tolmk - 768);     /* leave a hole for vga */
 227         }
 228         assign_resources(&dev->link[0]);
 229 }
 230
 231 static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
 232 {
 233         max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
 234         return max;
 235 }
 236
 237 static struct device_operations pci_domain_ops = {
 238         .read_resources   = pci_domain_read_resources,
 239         .set_resources    = pci_domain_set_resources,
 240         .enable_resources = enable_childrens_resources,
 241         .init             = 0,
 242         .scan_bus         = pci_domain_scan_bus,
 243 };
 244
 245 static void cpu_bus_init(device_t dev)
 246 {
 247         initialize_cpus(&dev->link[0]);
 248 }
 249
 250 static void cpu_bus_noop(device_t dev)
 251 {
 252 }
 253
 254 static struct device_operations cpu_bus_ops = {
 255         .read_resources   = cpu_bus_noop,
 256         .set_resources    = cpu_bus_noop,
 257         .enable_resources = cpu_bus_noop,
 258         .init             = cpu_bus_init,
 259         .scan_bus         = 0,
 260 };
 261
 262 static void enable_dev(struct device *dev)
 263 {
 264         struct device_path path;
 265
 266         /* Set the operations if it is a special bus type */
 267         if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
 268                 dev->ops = &pci_domain_ops;
 269         }
 270         else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
 271                 dev->ops = &cpu_bus_ops;
 272         }
 273 }
 274
 275 struct chip_operations northbridge_via_vt8623_control = {
 276         .enable_dev = enable_dev,
 277         .name       = "VIA vt8623 Northbridge",
 278 };