src/northbridge/via/vt8623/northbridge.c

   1 #include <console/console.h>
   2 #include <arch/io.h>
   3 #include <stdint.h>
   4 #include <device/device.h>
   5 #include <device/pci.h>
   6 #include <device/hypertransport.h>
   7 #include <device/pci_ids.h>
   8 #include <stdlib.h>
   9 #include <string.h>
  10 #include <bitops.h>
  11 #include <cpu/cpu.h>
  12 #include <cpu/x86/mtrr.h>
  13 #include <cpu/x86/msr.h>
  14 #include "chip.h"
  15 #include "northbridge.h"
  16
  17 /*
  18  * This fixup is based on capturing values from an Award bios.  Without
  19  * this fixup the DMA write performance is awful (i.e. hdparm -t /dev/hda is 20x
  20  * slower than normal, ethernet drops packets).
  21  * Apparently these registers govern some sort of bus master behavior.
  22  */
  23 static void dump_dev(device_t dev)
  24 {
  25         int i,j;
  26
  27         for(i = 0; i < 256; i += 16) {
  28                 printk_debug("0x%x: ", i);
  29                 for(j = 0; j < 16; j++) {
  30                         printk_debug("%02x ", pci_read_config8(dev, i+j));
  31                 }
  32                 printk_debug("\n");
  33         }
  34 }
  35 static void northbridge_init(device_t dev)
  36 {
  37         device_t fb_dev;
  38         unsigned long fb;
  39         unsigned char c;
  40
  41         printk_debug("VT8623 random fixup ...\n");
  42         pci_write_config8(dev,  0x0d, 0x08);
  43         pci_write_config8(dev,  0x70, 0x82);
  44         pci_write_config8(dev,  0x71, 0xc8);
  45         pci_write_config8(dev,  0x72, 0x00);
  46         pci_write_config8(dev,  0x73, 0x01);
  47         pci_write_config8(dev,  0x74, 0x01);
  48         pci_write_config8(dev,  0x75, 0x08);
  49         pci_write_config8(dev,  0x76, 0x52);
  50         pci_write_config8(dev,  0x13, 0xd0);
  51         pci_write_config8(dev,  0x84, 0x80);
  52         pci_write_config16(dev, 0x80, 0x610f);
  53         pci_write_config32(dev, 0x88, 0x00000002);
  54
  55         fb_dev = dev_find_device(PCI_VENDOR_ID_VIA, 0x3122, 0);
  56         if (fb_dev) {
  57                 /* Fixup GART and framebuffer addresses properly.
  58                  * First setup frame buffer properly.
  59                  */
  60                 //fb = pci_read_config32(dev, 0x10);       /* Base addres of framebuffer */
  61                 fb = 0xd0000000;
  62                 printk_debug("Frame buffer at %8x\n",fb);
  63
  64                 c = pci_read_config8(dev, 0xe1) & 0xf0;  /* size of vga */
  65                 c |= fb>>28;  /* upper nibble of frame buffer address */
  66                 c = 0xdd;
  67                 pci_write_config8(dev, 0xe1, c);
  68                 c = 0x81;                                /* enable framebuffer */
  69                 pci_write_config8(dev, 0xe0, c);
  70                 pci_write_config8(dev, 0xe2, 0x42);      /* 'cos award does */
  71         }
  72         //dump_dev(dev);
  73 }
  74
  75 static void nullfunc(){}
  76
  77 static struct device_operations northbridge_operations = {
  78         .read_resources   = nullfunc,
  79         .set_resources    = pci_dev_set_resources,
  80         .enable_resources = pci_dev_enable_resources,
  81         .init             = northbridge_init
  82 };
  83
  84 static struct pci_driver northbridge_driver __pci_driver = {
  85         .ops = &northbridge_operations,
  86         .vendor = PCI_VENDOR_ID_VIA,
  87         .device = PCI_DEVICE_ID_VIA_8623,
  88 };
  89
  90 static void agp_init(device_t dev)
  91 {
  92         printk_debug("VT8623 AGP random fixup ...\n");
  93
  94         pci_write_config8(dev, 0x3e, 0x0c);
  95         pci_write_config8(dev, 0x40, 0x83);
  96         pci_write_config8(dev, 0x41, 0xc5);
  97         pci_write_config8(dev, 0x43, 0x44);
  98         pci_write_config8(dev, 0x44, 0x34);
  99         pci_write_config8(dev, 0x83, 0x02);
 100         //dump_dev(dev);
 101 }
 102
 103 static struct device_operations agp_operations = {
 104         .read_resources   = nullfunc,
 105         .set_resources    = pci_dev_set_resources,
 106         .enable_resources = pci_bus_enable_resources,
 107         .init             = agp_init,
 108         .scan_bus         = pci_scan_bridge,
 109         .ops_pci          = 0,
 110 };
 111
 112 static struct pci_driver agp_driver __pci_driver = {
 113         .ops = &agp_operations,
 114         .vendor = PCI_VENDOR_ID_VIA,
 115         .device = PCI_DEVICE_ID_VIA_8633_1,
 116 };
 117
 118 static void vga_init(device_t dev)
 119 {
 120 //      unsigned long fb;
 121         msr_t clocks1,clocks2,instructions,setup;
 122
 123         printk_debug("VGA random fixup ...\n");
 124         pci_write_config8(dev, 0x04, 0x07);
 125         pci_write_config8(dev, 0x0d, 0x20);
 126         pci_write_config32(dev,0x10,0xd8000008);
 127         pci_write_config32(dev,0x14,0xdc000000);
 128
 129         //dump_dev(dev);
 130
 131         // set up performnce counters for debugging vga init sequence
 132         //setup.lo = 0x1c0; // count instructions
 133         //wrmsr(0x187,setup);
 134         //instructions.hi = 0;
 135         //instructions.lo = 0;
 136         //wrmsr(0xc2,instructions);
 137         //clocks1 = rdmsr(0x10);
 138
 139
 140 #if 0
 141         /* code to make vga init go through the emulator - as of yet this does not workfor the epia-m */
 142         dev->on_mainboard=1;
 143         dev->rom_address = (void *)0xfffc0000;
 144
 145         pci_dev_init(dev);
 146
 147         call_bios_interrupt(0x10,0x4f1f,0x8003,1,0);
 148
 149         //clocks2 = rdmsr(0x10);
 150         //instructions = rdmsr(0xc2);
 151
 152         printk_debug("Clocks 1 = %08x:%08x\n",clocks1.hi,clocks1.lo);
 153         printk_debug("Clocks 2 = %08x:%08x\n",clocks2.hi,clocks2.lo);
 154         printk_debug("Instructions = %08x:%08x\n",instructions.hi,instructions.lo);
 155
 156 #else
 157
 158         /* code to make vga init run in real mode - does work but against the current Linuxbios philosophy */
 159         printk_debug("INSTALL REAL-MODE IDT\n");
 160         setup_realmode_idt();
 161         printk_debug("DO THE VGA BIOS\n");
 162         do_vgabios();
 163
 164         //clocks2 = rdmsr(0x10);
 165         //instructions = rdmsr(0xc2);
 166
 167         //printk_debug("Clocks 1 = %08x:%08x\n",clocks1.hi,clocks1.lo);
 168         //printk_debug("Clocks 2 = %08x:%08x\n",clocks2.hi,clocks2.lo);
 169         //printk_debug("Instructions = %08x:%08x\n",instructions.hi,instructions.lo);
 170
 171         vga_enable_console();
 172
 173 #endif
 174
 175
 176         pci_write_config32(dev,0x30,0);
 177
 178         /* Set the vga mtrrs - disable for the moment as the add_var_mtrr function has vapourised */
 179 #if 0
 180         add_var_mtrr( 0xd0000000 >> 10, 0x08000000>>10, MTRR_TYPE_WRCOMB);
 181         fb = pci_read_config32(dev,0x10); // get the fb address
 182         add_var_mtrr( fb>>10, 8192, MTRR_TYPE_WRCOMB);
 183 #endif
 184 }
 185
 186 static void vga_read_resources(device_t dev)
 187 {
 188
 189         dev->rom_address = (void *)0xfffc0000;
 190         dev->on_mainboard=1;
 191         pci_dev_read_resources(dev);
 192
 193 }
 194
 195 static struct device_operations vga_operations = {
 196         .read_resources   = vga_read_resources,
 197         .set_resources    = pci_dev_set_resources,
 198         .enable_resources = pci_dev_enable_resources,
 199         .init             = vga_init,
 200         .ops_pci          = 0,
 201 };
 202
 203 static struct pci_driver vga_driver __pci_driver = {
 204         .ops = &vga_operations,
 205         .vendor = PCI_VENDOR_ID_VIA,
 206         .device = 0x3122,
 207 };
 208
 209
 210 #define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM)
 211
 212 static void pci_domain_read_resources(device_t dev)
 213 {
 214         struct resource *resource;
 215
 216         printk_spew("Entering vt8623 pci_domain_read_resources.\n");
 217
 218         /* Initialize the system wide io space constraints */
 219         resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0));
 220         resource->limit = 0xffffUL;
 221         resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
 222                 IORESOURCE_ASSIGNED;
 223
 224         /* Initialize the system wide memory resources constraints */
 225         resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0));
 226         resource->limit = 0xffffffffULL;
 227         resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
 228                 IORESOURCE_ASSIGNED;
 229
 230         printk_spew("Leaving vt8623 pci_domain_read_resources.\n");
 231 }
 232
 233 static void ram_resource(device_t dev, unsigned long index,
 234         unsigned long basek, unsigned long sizek)
 235 {
 236         struct resource *resource;
 237
 238         if (!sizek) {
 239                 return;
 240         }
 241         resource = new_resource(dev, index);
 242         resource->base  = ((resource_t)basek) << 10;
 243         resource->size  = ((resource_t)sizek) << 10;
 244         resource->flags =  IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
 245                 IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
 246 }
 247
 248 static void tolm_test(void *gp, struct device *dev, struct resource *new)
 249 {
 250         struct resource **best_p = gp;
 251         struct resource *best;
 252         best = *best_p;
 253         if (!best || (best->base > new->base)) {
 254                 best = new;
 255         }
 256         *best_p = best;
 257 }
 258
 259 static uint32_t find_pci_tolm(struct bus *bus)
 260 {
 261         struct resource *min;
 262         uint32_t tolm;
 263         min = 0;
 264         search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min);
 265         tolm = 0xffffffffUL;
 266         if (min && tolm > min->base) {
 267                 tolm = min->base;
 268         }
 269         return tolm;
 270 }
 271
 272 static void pci_domain_set_resources(device_t dev)
 273 {
 274         static const uint8_t ramregs[] = {0x5a, 0x5b, 0x5c, 0x5d };
 275         device_t mc_dev;
 276         uint32_t pci_tolm;
 277
 278         printk_spew("Entering vt8623 pci_domain_set_resources.\n");
 279
 280         pci_tolm = find_pci_tolm(&dev->link[0]);
 281         mc_dev = dev->link[0].children;
 282         if (mc_dev) {
 283                 unsigned long tomk, tolmk;
 284                 unsigned char rambits;
 285                 int i, idx;
 286
 287                 for(rambits = 0, i = 0; i < sizeof(ramregs)/sizeof(ramregs[0]); i++) {
 288                         unsigned char reg;
 289                         reg = pci_read_config8(mc_dev, ramregs[i]);
 290                         /* these are ENDING addresses, not sizes.
 291                          * if there is memory in this slot, then reg will be > rambits.
 292                          * So we just take the max, that gives us total.
 293                          * We take the highest one to cover for once and future linuxbios
 294                          * bugs. We warn about bugs.
 295                          */
 296                         if (reg > rambits)
 297                                 rambits = reg;
 298                         if (reg < rambits)
 299                                 printk_err("ERROR! register 0x%x is not set!\n",
 300                                         ramregs[i]);
 301                 }
 302                 printk_debug("I would set ram size to 0x%x Kbytes\n", (rambits)*16*1024);
 303                 tomk = rambits*16*1024 - 32768;
 304                 /* Compute the top of Low memory */
 305                 tolmk = pci_tolm >> 10;
 306                 if (tolmk >= tomk) {
 307                         /* The PCI hole does does not overlap the memory.
 308                          */
 309                         tolmk = tomk;
 310                 }
 311                 /* Report the memory regions */
 312                 idx = 10;
 313                 ram_resource(dev, idx++, 0, 640);               /* first 640k */
 314                 ram_resource(dev, idx++, 768, tolmk - 768);     /* leave a hole for vga */
 315         }
 316         assign_resources(&dev->link[0]);
 317 }
 318
 319 static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
 320 {
 321         printk_spew("Entering vt8623 pci_domain_scan_bus.\n");
 322
 323         max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
 324         return max;
 325 }
 326
 327 static struct device_operations pci_domain_ops = {
 328         .read_resources   = pci_domain_read_resources,
 329         .set_resources    = pci_domain_set_resources,
 330         .enable_resources = enable_childrens_resources,
 331         .init             = 0,
 332         .scan_bus         = pci_domain_scan_bus,
 333 };
 334
 335 static void cpu_bus_init(device_t dev)
 336 {
 337         initialize_cpus(&dev->link[0]);
 338 }
 339
 340 static void cpu_bus_noop(device_t dev)
 341 {
 342 }
 343
 344 static struct device_operations cpu_bus_ops = {
 345         .read_resources   = cpu_bus_noop,
 346         .set_resources    = cpu_bus_noop,
 347         .enable_resources = cpu_bus_noop,
 348         .init             = cpu_bus_init,
 349         .scan_bus         = 0,
 350 };
 351
 352 static void enable_dev(struct device *dev)
 353 {
 354         printk_spew("In vt8623 enable_dev for device %s.\n", dev_path(dev));
 355
 356         /* Set the operations if it is a special bus type */
 357         if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
 358                 dev->ops = &pci_domain_ops;
 359                 pci_set_method(dev);
 360         }
 361         else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
 362                 dev->ops = &cpu_bus_ops;
 363         }
 364 }
 365
 366 struct chip_operations northbridge_via_vt8623_ops = {
 367         CHIP_NAME("VIA vt8623 Northbridge")
 368         .enable_dev = enable_dev,
 369 };