src/northbridge/via/vt8623/northbridge.c

   1 #include <console/console.h>
   2 #include <arch/io.h>
   3 #include <stdint.h>
   4 #include <device/device.h>
   5 #include <device/pci.h>
   6 #include <device/hypertransport.h>
   7 #include <device/pci_ids.h>
   8 #include <stdlib.h>
   9 #include <string.h>
  10 #include <bitops.h>
  11 #include <cpu/cpu.h>
  12 #include <cpu/x86/mtrr.h>
  13 #include <cpu/x86/msr.h>
  14 #include "chip.h"
  15 #include "northbridge.h"
  16
  17 /*
  18  * This fixup is based on capturing values from an Award BIOS.  Without
  19  * this fixup the DMA write performance is awful (i.e. hdparm -t /dev/hda is 20x
  20  * slower than normal, ethernet drops packets).
  21  * Apparently these registers govern some sort of bus master behavior.
  22  */
  23
  24 static void northbridge_init(device_t dev)
  25 {
  26         device_t fb_dev;
  27         unsigned long fb;
  28         unsigned char c;
  29
  30         printk(BIOS_DEBUG, "VT8623 random fixup ...\n");
  31         pci_write_config8(dev,  0x0d, 0x08);
  32         pci_write_config8(dev,  0x70, 0x82);
  33         pci_write_config8(dev,  0x71, 0xc8);
  34         pci_write_config8(dev,  0x72, 0x00);
  35         pci_write_config8(dev,  0x73, 0x01);
  36         pci_write_config8(dev,  0x74, 0x01);
  37         pci_write_config8(dev,  0x75, 0x08);
  38         pci_write_config8(dev,  0x76, 0x52);
  39         pci_write_config8(dev,  0x13, 0xd0);
  40         pci_write_config8(dev,  0x84, 0x80);
  41         pci_write_config16(dev, 0x80, 0x610f);
  42         pci_write_config32(dev, 0x88, 0x00000002);
  43
  44         fb_dev = dev_find_device(PCI_VENDOR_ID_VIA, 0x3122, 0);
  45         if (fb_dev) {
  46                 /* Fixup GART and framebuffer addresses properly.
  47                  * First setup frame buffer properly.
  48                  */
  49                 //fb = pci_read_config32(dev, 0x10);       /* Base addres of framebuffer */
  50                 fb = 0xd0000000;
  51                 printk(BIOS_DEBUG, "Frame buffer at %8lx\n",fb);
  52
  53                 c = pci_read_config8(dev, 0xe1) & 0xf0;  /* size of vga */
  54                 c |= fb>>28;  /* upper nibble of frame buffer address */
  55                 c = 0xdd;
  56                 pci_write_config8(dev, 0xe1, c);
  57                 c = 0x81;                                /* enable framebuffer */
  58                 pci_write_config8(dev, 0xe0, c);
  59                 pci_write_config8(dev, 0xe2, 0x42);      /* 'cos award does */
  60         }
  61 }
  62
  63 static void nullfunc(device_t dev)
  64 {
  65         /* Nothing to do */
  66 }
  67
  68 static struct device_operations northbridge_operations = {
  69         .read_resources   = nullfunc,
  70         .set_resources    = pci_dev_set_resources,
  71         .enable_resources = pci_dev_enable_resources,
  72         .init             = northbridge_init
  73 };
  74
  75 static const struct pci_driver northbridge_driver __pci_driver = {
  76         .ops = &northbridge_operations,
  77         .vendor = PCI_VENDOR_ID_VIA,
  78         .device = PCI_DEVICE_ID_VIA_8623,
  79 };
  80
  81 static void agp_init(device_t dev)
  82 {
  83         printk(BIOS_DEBUG, "VT8623 AGP random fixup ...\n");
  84
  85         pci_write_config8(dev, 0x3e, 0x0c);
  86         pci_write_config8(dev, 0x40, 0x83);
  87         pci_write_config8(dev, 0x41, 0xc5);
  88         pci_write_config8(dev, 0x43, 0x44);
  89         pci_write_config8(dev, 0x44, 0x34);
  90         pci_write_config8(dev, 0x83, 0x02);
  91 }
  92
  93 static struct device_operations agp_operations = {
  94         .read_resources   = nullfunc,
  95         .set_resources    = pci_dev_set_resources,
  96         .enable_resources = pci_bus_enable_resources,
  97         .init             = agp_init,
  98         .scan_bus         = pci_scan_bridge,
  99         .ops_pci          = 0,
 100 };
 101
 102 static const struct pci_driver agp_driver __pci_driver = {
 103         .ops = &agp_operations,
 104         .vendor = PCI_VENDOR_ID_VIA,
 105         .device = PCI_DEVICE_ID_VIA_8633_1,
 106 };
 107
 108 static void vga_init(device_t dev)
 109 {
 110         //unsigned long fb;
 111         //msr_t clocks1,clocks2,instructions,setup;
 112
 113         printk(BIOS_DEBUG, "VGA random fixup ...\n");
 114         pci_write_config8(dev, 0x04, 0x07);
 115         pci_write_config8(dev, 0x0d, 0x20);
 116         pci_write_config32(dev,0x10,0xd8000008);
 117         pci_write_config32(dev,0x14,0xdc000000);
 118
 119         // set up performnce counters for debugging vga init sequence
 120         //setup.lo = 0x1c0; // count instructions
 121         //wrmsr(0x187,setup);
 122         //instructions.hi = 0;
 123         //instructions.lo = 0;
 124         //wrmsr(0xc2,instructions);
 125         //clocks1 = rdmsr(0x10);
 126
 127
 128 #if 0
 129         /* code to make vga init go through the emulator - as of yet this does not workfor the epia-m */
 130         pci_dev_init(dev);
 131
 132         call_bios_interrupt(0x10,0x4f1f,0x8003,1,0);
 133
 134         //clocks2 = rdmsr(0x10);
 135         //instructions = rdmsr(0xc2);
 136
 137         printk(BIOS_DEBUG, "Clocks 1 = %08x:%08x\n",clocks1.hi,clocks1.lo);
 138         printk(BIOS_DEBUG, "Clocks 2 = %08x:%08x\n",clocks2.hi,clocks2.lo);
 139         printk(BIOS_DEBUG, "Instructions = %08x:%08x\n",instructions.hi,instructions.lo);
 140
 141 #else
 142
 143         /* code to make vga init run in real mode - does work but against the current coreboot philosophy */
 144         printk(BIOS_DEBUG, "INSTALL REAL-MODE IDT\n");
 145         setup_realmode_idt();
 146         printk(BIOS_DEBUG, "DO THE VGA BIOS\n");
 147         do_vgabios();
 148
 149         //clocks2 = rdmsr(0x10);
 150         //instructions = rdmsr(0xc2);
 151
 152         //printk(BIOS_DEBUG, "Clocks 1 = %08x:%08x\n",clocks1.hi,clocks1.lo);
 153         //printk(BIOS_DEBUG, "Clocks 2 = %08x:%08x\n",clocks2.hi,clocks2.lo);
 154         //printk(BIOS_DEBUG, "Instructions = %08x:%08x\n",instructions.hi,instructions.lo);
 155
 156         vga_enable_console();
 157
 158 #endif
 159
 160         pci_write_config32(dev,0x30,0);
 161
 162         /* Set the vga mtrrs - disable for the moment as the add_var_mtrr function has vapourised */
 163 #if 0
 164         add_var_mtrr( 0xd0000000 >> 10, 0x08000000>>10, MTRR_TYPE_WRCOMB);
 165         fb = pci_read_config32(dev,0x10); // get the fb address
 166         add_var_mtrr( fb>>10, 8192, MTRR_TYPE_WRCOMB);
 167 #endif
 168 }
 169
 170 static struct device_operations vga_operations = {
 171         .read_resources   = pci_dev_read_resources,
 172         .set_resources    = pci_dev_set_resources,
 173         .enable_resources = pci_dev_enable_resources,
 174         .init             = vga_init,
 175         .ops_pci          = 0,
 176 };
 177
 178 static const struct pci_driver vga_driver __pci_driver = {
 179         .ops = &vga_operations,
 180         .vendor = PCI_VENDOR_ID_VIA,
 181         .device = 0x3122,
 182 };
 183
 184 static void ram_resource(device_t dev, unsigned long index,
 185         unsigned long basek, unsigned long sizek)
 186 {
 187         struct resource *resource;
 188
 189         if (!sizek) {
 190                 return;
 191         }
 192         resource = new_resource(dev, index);
 193         resource->base  = ((resource_t)basek) << 10;
 194         resource->size  = ((resource_t)sizek) << 10;
 195         resource->flags =  IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
 196                 IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
 197 }
 198
 199 static void tolm_test(void *gp, struct device *dev, struct resource *new)
 200 {
 201         struct resource **best_p = gp;
 202         struct resource *best;
 203         best = *best_p;
 204         if (!best || (best->base > new->base)) {
 205                 best = new;
 206         }
 207         *best_p = best;
 208 }
 209
 210 static uint32_t find_pci_tolm(struct bus *bus)
 211 {
 212         struct resource *min;
 213         uint32_t tolm;
 214         min = 0;
 215         search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min);
 216         tolm = 0xffffffffUL;
 217         if (min && tolm > min->base) {
 218                 tolm = min->base;
 219         }
 220         return tolm;
 221 }
 222
 223 #if CONFIG_WRITE_HIGH_TABLES==1
 224 /* maximum size of high tables in KB */
 225 #define HIGH_TABLES_SIZE 64
 226 extern uint64_t high_tables_base, high_tables_size;
 227 #endif
 228
 229 static void pci_domain_set_resources(device_t dev)
 230 {
 231         static const uint8_t ramregs[] = {0x5a, 0x5b, 0x5c, 0x5d };
 232         device_t mc_dev;
 233         uint32_t pci_tolm;
 234
 235         printk(BIOS_SPEW, "Entering vt8623 pci_domain_set_resources.\n");
 236
 237         pci_tolm = find_pci_tolm(&dev->link[0]);
 238         mc_dev = dev->link[0].children;
 239         if (mc_dev) {
 240                 unsigned long tomk, tolmk;
 241                 unsigned char rambits;
 242                 int i, idx;
 243
 244                 for(rambits = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) {
 245                         unsigned char reg;
 246                         reg = pci_read_config8(mc_dev, ramregs[i]);
 247                         /* these are ENDING addresses, not sizes.
 248                          * if there is memory in this slot, then reg will be > rambits.
 249                          * So we just take the max, that gives us total.
 250                          * We take the highest one to cover for once and future coreboot
 251                          * bugs. We warn about bugs.
 252                          */
 253                         if (reg > rambits)
 254                                 rambits = reg;
 255                         if (reg < rambits)
 256                                 printk(BIOS_ERR, "ERROR! register 0x%x is not set!\n",
 257                                         ramregs[i]);
 258                 }
 259                 printk(BIOS_DEBUG, "I would set ram size to 0x%x Kbytes\n", (rambits)*16*1024);
 260                 tomk = rambits*16*1024 - 32768;
 261                 /* Compute the top of Low memory */
 262                 tolmk = pci_tolm >> 10;
 263                 if (tolmk >= tomk) {
 264                         /* The PCI hole does does not overlap the memory.
 265                          */
 266                         tolmk = tomk;
 267                 }
 268
 269 #if CONFIG_WRITE_HIGH_TABLES == 1
 270                 high_tables_base = (tolmk - HIGH_TABLES_SIZE) * 1024;
 271                 high_tables_size = HIGH_TABLES_SIZE* 1024;
 272                 printk(BIOS_DEBUG, "tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", tomk*1024, high_tables_base, high_tables_size);
 273 #endif
 274
 275                 /* Report the memory regions */
 276                 idx = 10;
 277                 ram_resource(dev, idx++, 0, 640);               /* first 640k */
 278                 ram_resource(dev, idx++, 768, tolmk - 768);     /* leave a hole for vga */
 279         }
 280         assign_resources(&dev->link[0]);
 281 }
 282
 283 static struct device_operations pci_domain_ops = {
 284         .read_resources   = pci_domain_read_resources,
 285         .set_resources    = pci_domain_set_resources,
 286         .enable_resources = enable_childrens_resources,
 287         .init             = 0,
 288         .scan_bus         = pci_domain_scan_bus,
 289 };
 290
 291 static void cpu_bus_init(device_t dev)
 292 {
 293         initialize_cpus(&dev->link[0]);
 294 }
 295
 296 static void cpu_bus_noop(device_t dev)
 297 {
 298 }
 299
 300 static struct device_operations cpu_bus_ops = {
 301         .read_resources   = cpu_bus_noop,
 302         .set_resources    = cpu_bus_noop,
 303         .enable_resources = cpu_bus_noop,
 304         .init             = cpu_bus_init,
 305         .scan_bus         = 0,
 306 };
 307
 308 static void enable_dev(struct device *dev)
 309 {
 310         printk(BIOS_SPEW, "In vt8623 enable_dev for device %s.\n", dev_path(dev));
 311
 312         /* Set the operations if it is a special bus type */
 313         if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
 314                 dev->ops = &pci_domain_ops;
 315                 pci_set_method(dev);
 316         }
 317         else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
 318                 dev->ops = &cpu_bus_ops;
 319         }
 320 }
 321
 322 struct chip_operations northbridge_via_vt8623_ops = {
 323         CHIP_NAME("VIA VT8623 Northbridge")
 324         .enable_dev = enable_dev,
 325 };