src/northbridge/via/vt8601/northbridge.c

   1 #include <console/console.h>
   2 #include <arch/io.h>
   3 #include <stdint.h>
   4 #include <device/device.h>
   5 #include <device/pci.h>
   6 #include <device/hypertransport.h>
   7 #include <stdlib.h>
   8 #include <string.h>
   9 #include <bitops.h>
  10 #include "chip.h"
  11 #include "northbridge.h"
  12
  13 /*
  14  * This fixup is based on capturing values from an Award bios.  Without
  15  * this fixup the DMA write performance is awful (i.e. hdparm -t /dev/hda is 20x
  16  * slower than normal, ethernet drops packets).
  17  * Apparently these registers govern some sort of bus master behavior.
  18  */
  19 static void northbridge_init(device_t dev)
  20 {
  21         printk_spew("VT8601 random fixup ...\n");
  22         pci_write_config8(dev, 0x70, 0xc0);
  23         pci_write_config8(dev, 0x71, 0x88);
  24         pci_write_config8(dev, 0x72, 0xec);
  25         pci_write_config8(dev, 0x73, 0x0c);
  26         pci_write_config8(dev, 0x74, 0x0e);
  27         pci_write_config8(dev, 0x75, 0x81);
  28         pci_write_config8(dev, 0x76, 0x52);
  29 }
  30
  31
  32
  33 static struct device_operations northbridge_operations = {
  34         .read_resources   = pci_dev_read_resources,
  35         .set_resources    = pci_dev_set_resources,
  36         .enable_resources = pci_dev_enable_resources,
  37         .init             = northbridge_init,
  38         .enable           = 0,
  39         .ops_pci          = 0,
  40 };
  41
  42 static struct pci_driver northbridge_driver __pci_driver = {
  43         .ops = &northbridge_operations,
  44         .vendor = PCI_VENDOR_ID_VIA,
  45         .device = 0x0601, /* 0x8601 is the AGP bridge? */
  46 };
  47
  48
  49
  50 #define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM)
  51
  52 static void pci_domain_read_resources(device_t dev)
  53 {
  54         struct resource *resource;
  55         unsigned reg;
  56
  57         /* Initialize the system wide io space constraints */
  58         resource = new_resource(dev, 0);
  59         resource->base  = 0x400;
  60         resource->limit = 0xffffUL;
  61         resource->flags = IORESOURCE_IO;
  62         compute_allocate_resource(&dev->link[0], resource,
  63                 IORESOURCE_IO, IORESOURCE_IO);
  64
  65         /* Initialize the system wide memory resources constraints */
  66         resource = new_resource(dev, 1);
  67         resource->limit = 0xffffffffULL;
  68         resource->flags = IORESOURCE_MEM;
  69         compute_allocate_resource(&dev->link[0], resource,
  70                 IORESOURCE_MEM, IORESOURCE_MEM);
  71 }
  72
  73 static void ram_resource(device_t dev, unsigned long index,
  74         unsigned long basek, unsigned long sizek)
  75 {
  76         struct resource *resource;
  77
  78         if (!sizek) {
  79                 return;
  80         }
  81         resource = new_resource(dev, index);
  82         resource->base  = ((resource_t)basek) << 10;
  83         resource->size  = ((resource_t)sizek) << 10;
  84         resource->flags =  IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
  85                 IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
  86 }
  87
  88 static const uint8_t ramregs[] = {0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f,
  89                                         0x56, 0x57};
  90
  91 static void pci_domain_set_resources(device_t dev)
  92 {
  93         struct resource *resource, *last;
  94         device_t mc_dev;
  95         uint32_t pci_tolm;
  96
  97         pci_tolm = 0xffffffffUL;
  98         last = &dev->resource[dev->resources];
  99         for(resource = &dev->resource[0]; resource < last; resource++)
 100         {
 101                 compute_allocate_resource(&dev->link[0], resource,
 102                         BRIDGE_IO_MASK, resource->flags & BRIDGE_IO_MASK);
 103
 104                 resource->flags |= IORESOURCE_STORED;
 105                 report_resource_stored(dev, resource, "");
 106
 107                 if ((resource->flags & IORESOURCE_MEM) &&
 108                         (pci_tolm > resource->base))
 109                 {
 110                         pci_tolm = resource->base;
 111                 }
 112         }
 113
 114         mc_dev = dev->link[0].children;
 115         if (mc_dev) {
 116                 unsigned long tomk, tolmk;
 117                 unsigned char rambits;
 118                 int i, idx;
 119
 120                 for(rambits = 0, i = 0; i < sizeof(ramregs)/sizeof(ramregs[0]); i++) {
 121                         unsigned char reg;
 122                         reg = pci_read_config8(mc_dev, ramregs[i]);
 123                         /* these are ENDING addresses, not sizes.
 124                          * if there is memory in this slot, then reg will be > rambits.
 125                          * So we just take the max, that gives us total.
 126                          * We take the highest one to cover for once and future linuxbios
 127                          * bugs. We warn about bugs.
 128                          */
 129                         if (reg > rambits)
 130                                 rambits = reg;
 131                         if (reg < rambits)
 132                                 printk_err("ERROR! register 0x%x is not set!\n",
 133                                         ramregs[i]);
 134                 }
 135                 printk_debug("I would set ram size to 0x%x Kbytes\n", (rambits)*8*1024);
 136                 tomk = ramreg*8*1024;
 137                 /* Compute the top of Low memory */
 138                 tolmk = pci_tolm >> 10;
 139                 if (tolmk >= tomk) {
 140                         /* The PCI hole does does not overlap the memory.
 141                          */
 142                         tolmk = tomk;
 143                 }
 144                 /* Report the memory regions */
 145                 idx = 10;
 146                 ram_resource(dev, idx++, 0, tolmk);
 147         }
 148         assign_resources(&dev->link[0]);
 149 }
 150
 151 static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
 152 {
 153         max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
 154         return max;
 155 }
 156
 157 static struct device_operations pci_domain_ops = {
 158         .read_resources   = pci_domain_read_resources,
 159         .set_resources    = pci_domain_set_resources,
 160         .enable_resources = enable_childrens_resources,
 161         .init             = 0,
 162         .scan_bus         = pci_domain_scan_bus,
 163 };
 164
 165 static void cpu_bus_init(device_t dev)
 166 {
 167         initialize_cpus(&dev->link[0]);
 168 }
 169
 170 static void cpu_bus_noop(device_t dev)
 171 {
 172 }
 173
 174 static struct device_operations cpu_bus_ops = {
 175         .read_resources   = cpu_bus_noop,
 176         .set_resources    = cpu_bus_noop,
 177         .enable_resources = cpu_bus_noop,
 178         .init             = cpu_bus_init,
 179         .scan_bus         = 0,
 180 };
 181
 182 static void enable_dev(struct device *dev)
 183 {
 184         struct device_path path;
 185
 186         /* Set the operations if it is a special bus type */
 187         if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
 188                 dev->ops = &pci_domain_ops;
 189         }
 190         else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
 191                 dev->ops = &cpu_bus_ops;
 192         }
 193 }
 194
 195 struct chip_operations northbridge_via_vt8601_control = {
 196         .enable_dev = enable_dev,
 197         .name      = "VIA vt8601 Northbridge",
 198 };