src/northbridge/via/vt8601/northbridge.c

   1 #include <console/console.h>
   2 #include <arch/io.h>
   3 #include <stdint.h>
   4 #include <device/device.h>
   5 #include <device/pci.h>
   6 #include <device/pci_ids.h>
   7 #include <device/hypertransport.h>
   8 #include <stdlib.h>
   9 #include <string.h>
  10 #include <bitops.h>
  11 #include "chip.h"
  12 #include "northbridge.h"
  13
  14 /*
  15  * This fixup is based on capturing values from an Award bios.  Without
  16  * this fixup the DMA write performance is awful (i.e. hdparm -t /dev/hda is 20x
  17  * slower than normal, ethernet drops packets).
  18  * Apparently these registers govern some sort of bus master behavior.
  19  */
  20 static void northbridge_init(device_t dev)
  21 {
  22         printk_spew("VT8601 random fixup ...\n");
  23         pci_write_config8(dev, 0x70, 0xc0);
  24         pci_write_config8(dev, 0x71, 0x88);
  25         pci_write_config8(dev, 0x72, 0xec);
  26         pci_write_config8(dev, 0x73, 0x0c);
  27         pci_write_config8(dev, 0x74, 0x0e);
  28         pci_write_config8(dev, 0x75, 0x81);
  29         pci_write_config8(dev, 0x76, 0x52);
  30 }
  31
  32
  33
  34 static struct device_operations northbridge_operations = {
  35         .read_resources   = pci_dev_read_resources,
  36         .set_resources    = pci_dev_set_resources,
  37         .enable_resources = pci_dev_enable_resources,
  38         .init             = northbridge_init,
  39         .enable           = 0,
  40         .ops_pci          = 0,
  41 };
  42
  43 static struct pci_driver northbridge_driver __pci_driver = {
  44         .ops = &northbridge_operations,
  45         .vendor = PCI_VENDOR_ID_VIA,
  46         .device = 0x0601, /* 0x8601 is the AGP bridge? */
  47 };
  48
  49
  50
  51 #define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM)
  52
  53 static void pci_domain_read_resources(device_t dev)
  54 {
  55         struct resource *resource;
  56
  57         /* Initialize the system wide io space constraints */
  58         resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0));
  59         resource->limit = 0xffffUL;
  60         resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
  61
  62         /* Initialize the system wide memory resources constraints */
  63         resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0));
  64         resource->limit = 0xffffffffULL;
  65         resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
  66 }
  67
  68 static void ram_resource(device_t dev, unsigned long index,
  69         unsigned long basek, unsigned long sizek)
  70 {
  71         struct resource *resource;
  72
  73         if (!sizek) {
  74                 return;
  75         }
  76         resource = new_resource(dev, index);
  77         resource->base  = ((resource_t)basek) << 10;
  78         resource->size  = ((resource_t)sizek) << 10;
  79         resource->flags =  IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
  80                 IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
  81 }
  82
  83 static void tolm_test(void *gp, struct device *dev, struct resource *new)
  84 {
  85         struct resource **best_p = gp;
  86         struct resource *best;
  87         best = *best_p;
  88         if (!best || (best->base > new->base)) {
  89                 best = new;
  90         }
  91         *best_p = best;
  92 }
  93
  94 static uint32_t find_pci_tolm(struct bus *bus)
  95 {
  96         struct resource *min;
  97         uint32_t tolm;
  98         min = 0;
  99         search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min);
 100         tolm = 0xffffffffUL;
 101         if (min && tolm > min->base) {
 102                 tolm = min->base;
 103         }
 104         return tolm;
 105 }
 106
 107 static void pci_domain_set_resources(device_t dev)
 108 {
 109         static const uint8_t ramregs[] = {
 110                 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f, 0x56, 0x57
 111         };
 112         device_t mc_dev;
 113         uint32_t pci_tolm;
 114
 115         pci_tolm = find_pci_tolm(&dev->link[0]);
 116         mc_dev = dev->link[0].children;
 117         if (mc_dev) {
 118                 unsigned long tomk, tolmk;
 119                 unsigned char rambits;
 120                 int i, idx;
 121
 122                 for(rambits = 0, i = 0; i < sizeof(ramregs)/sizeof(ramregs[0]); i++) {
 123                         unsigned char reg;
 124                         reg = pci_read_config8(mc_dev, ramregs[i]);
 125                         /* these are ENDING addresses, not sizes.
 126                          * if there is memory in this slot, then reg will be > rambits.
 127                          * So we just take the max, that gives us total.
 128                          * We take the highest one to cover for once and future linuxbios
 129                          * bugs. We warn about bugs.
 130                          */
 131                         if (reg > rambits)
 132                                 rambits = reg;
 133                         if (reg < rambits)
 134                                 printk_err("ERROR! register 0x%x is not set!\n",
 135                                         ramregs[i]);
 136                 }
 137                 printk_debug("I would set ram size to 0x%x Kbytes\n", (rambits)*8*1024);
 138                 tomk = rambits*8*1024;
 139                 /* Compute the top of Low memory */
 140                 tolmk = pci_tolm >> 10;
 141                 if (tolmk >= tomk) {
 142                         /* The PCI hole does does not overlap the memory.
 143                          */
 144                         tolmk = tomk;
 145                 }
 146                 /* Report the memory regions */
 147                 idx = 10;
 148                 ram_resource(dev, idx++, 0, tolmk);
 149         }
 150         assign_resources(&dev->link[0]);
 151 }
 152
 153 static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
 154 {
 155         max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
 156         return max;
 157 }
 158
 159 static struct device_operations pci_domain_ops = {
 160         .read_resources   = pci_domain_read_resources,
 161         .set_resources    = pci_domain_set_resources,
 162         .enable_resources = enable_childrens_resources,
 163         .init             = 0,
 164         .scan_bus         = pci_domain_scan_bus,
 165 };
 166
 167 static void cpu_bus_init(device_t dev)
 168 {
 169         initialize_cpus(&dev->link[0]);
 170 }
 171
 172 static void cpu_bus_noop(device_t dev)
 173 {
 174 }
 175
 176 static struct device_operations cpu_bus_ops = {
 177         .read_resources   = cpu_bus_noop,
 178         .set_resources    = cpu_bus_noop,
 179         .enable_resources = cpu_bus_noop,
 180         .init             = cpu_bus_init,
 181         .scan_bus         = 0,
 182 };
 183
 184 static void enable_dev(struct device *dev)
 185 {
 186         /* Set the operations if it is a special bus type */
 187         if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
 188                 dev->ops = &pci_domain_ops;
 189                 pci_set_method(dev);
 190         }
 191         else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
 192                 dev->ops = &cpu_bus_ops;
 193         }
 194 }
 195
 196 struct chip_operations northbridge_via_vt8601_ops = {
 197         CHIP_NAME("VIA vt8601 Northbridge")
 198         .enable_dev = enable_dev,
 199 };