src/northbridge/via/cx700/raminit.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007-2009 coresystems GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18  */
  19
  20 #include <types.h>
  21 #include <spd.h>
  22 #include <spd_ddr2.h>
  23 #include <sdram_mode.h>
  24 #include <delay.h>
  25 #include "cx700_registers.h"
  26
  27 // #define DEBUG_RAM_SETUP 1
  28
  29 /* Debugging macros. */
  30 #if defined(DEBUG_RAM_SETUP)
  31 #define PRINTK_DEBUG(x...)      printk_debug(x)
  32 #else
  33 #define PRINTK_DEBUG(x...)
  34 #endif
  35
  36 #define RAM_COMMAND_NORMAL      0x0
  37 #define RAM_COMMAND_NOP         0x1
  38 #define RAM_COMMAND_PRECHARGE   0x2
  39 #define RAM_COMMAND_MRS         0x3
  40 #define RAM_COMMAND_CBR         0x4
  41
  42 #define HOSTCTRL                PCI_DEV(0, 0, 2)
  43 #define MEMCTRL                 PCI_DEV(0, 0, 3)
  44
  45 #define DDRII_666       0x5
  46 #define DDRII_533       0x4
  47 #define DDRII_400       0x3
  48 #define DDRII_333       0x2
  49 #define DDRII_266       0x1
  50 #define DDRII_200       0x0
  51
  52 #define OHM_150 1
  53
  54 #ifdef  MEM_WIDTH_32BIT_MODE
  55 #define SDRAM1X_RA_14           30
  56 #define SDRAM1X_RA_13           29
  57 #define SDRAM1X_RA_12           28
  58 #define SDRAM1X_RA_12_8bk       26
  59 #define SDRAM1X_CA_12           15
  60 #define SDRAM1X_CA_11           14
  61 #define SDRAM1X_CA_09           11
  62 #define SDRAM1X_CA_09_8bk       11
  63 #define SDRAM1X_BA1             13
  64 #define SDRAM1X_BA2_8bk         14
  65 #define SDRAM1X_BA1_8bk         13
  66 #else
  67 #define SDRAM1X_RA_14           31
  68 #define SDRAM1X_RA_13           30
  69 #define SDRAM1X_RA_12           29
  70 #define SDRAM1X_RA_12_8bk       27
  71 #define SDRAM1X_CA_12           16
  72 #define SDRAM1X_CA_11           15
  73 #define SDRAM1X_CA_09           12
  74 #define SDRAM1X_CA_09_8bk       12
  75 #define SDRAM1X_BA1             14
  76 #define SDRAM1X_BA2_8bk         15
  77 #define SDRAM1X_BA1_8bk         14
  78 #endif
  79
  80 #define MA_Column       0x06
  81 #define MA_Bank         0x08
  82 #define MA_Row          0x30
  83 #define MA_4_Bank       0x00
  84 #define MA_8_Bank       0x08
  85 #define MA_12_Row       0x00
  86 #define MA_13_Row       0x10
  87 #define MA_14_Row       0x20
  88 #define MA_15_Row       0x30
  89 #define MA_9_Column     0x00
  90 #define MA_10_Column    0x02
  91 #define MA_11_Column    0x04
  92 #define MA_12_Column    0x06
  93
  94 #define GET_SPD(i, val, tmp, reg)                                                               \
  95         do{                                                                                     \
  96                 val = 0;                                                                        \
  97                 tmp = 0;                                                                        \
  98                 for(i = 0; i < 2; i++)  {                                                       \
  99                         if(pci_read_config8(PCI_DEV(0, 0, 4), (SCRATCH_REG_BASE + (i << 1)))) { \
 100                                 tmp = get_spd_data(ctrl, i, reg);                               \
 101                                 if(tmp > val)                                                   \
 102                                         val = tmp;                                              \
 103                         }                                                                       \
 104                 }                                                                               \
 105         } while ( 0 )
 106
 107 #define REGISTERPRESET(bus,dev,fun,bdfspec) \
 108         { u8 i, reg; \
 109                 for (i=0; i<(sizeof((bdfspec))/sizeof(struct regmask)); i++) { \
 110                         printk_debug("Writing bus " #bus " dev " #dev " fun " #fun " register "); \
 111                         printk_debug("%02x", (bdfspec)[i].reg); \
 112                         printk_debug("\n"); \
 113                         reg = pci_read_config8(PCI_DEV((bus), (dev), (fun)), (bdfspec)[i].reg); \
 114                         reg &= (bdfspec)[i].mask; \
 115                         reg |= (bdfspec)[i].val; \
 116                         pci_write_config8(PCI_DEV((bus), (dev), (fun)), (bdfspec)[i].reg, reg); \
 117                 } \
 118         }
 119
 120
 121 static void do_ram_command(const struct mem_controller *ctrl, u8 command)
 122 {
 123         u8 reg;
 124
 125         reg = pci_read_config8(MEMCTRL, 0x6b);
 126         reg &= 0xf8;            /* Clear bits 2-0. */
 127         reg |= command;
 128         pci_write_config8(MEMCTRL, 0x6b, reg);
 129
 130         PRINTK_DEBUG("    Sending RAM command 0x%02x\n", reg);
 131 }
 132
 133 // TODO factor out to another file
 134 static void c7_cpu_setup(const struct mem_controller *ctrl)
 135 {
 136         u8 size, i;
 137         size = sizeof(Reg_Val) / sizeof(Reg_Val[0]);
 138         for (i = 0; i < size; i += 2)
 139                 pci_write_config8(HOSTCTRL, Reg_Val[i], Reg_Val[i + 1]);
 140 }
 141
 142 static void ddr_detect(const struct mem_controller *ctrl)
 143 {
 144         /* FIXME: Only supports 2 ranks per DIMM */
 145         u8 val, rsize, dimm;
 146         u8 nrank = 0;
 147         u8 ndimm = 0;
 148         u8 rmap = 0;
 149         for (dimm = 0; dimm < DIMM_SOCKETS; dimm++) {
 150                 val = get_spd_data(ctrl, dimm, 0);
 151                 if ((val == 0x80) || (val == 0xff)) {
 152                         ndimm++;
 153                         rsize = get_spd_data(ctrl, dimm, SPD_RANK_SIZE);
 154                         /* unit is 128M */
 155                         rsize = (rsize << 3) | (rsize >> 5);
 156                         val =
 157                             get_spd_data(ctrl, dimm,
 158                                          SPD_MOD_ATTRIB_RANK) & SPD_MOD_ATTRIB_RANK_NUM_MASK;
 159                         switch (val) {
 160                         case 1:
 161                                 pci_write_config8(PCI_DEV(0, 0, 4), (SCRATCH_RANK_1 + (dimm << 1)),
 162                                                   rsize);
 163                                 rmap |= (1 << ((dimm << 1) + 1));
 164                                 nrank++;
 165                         case 0:
 166                                 pci_write_config8(PCI_DEV(0, 0, 4), (SCRATCH_RANK_0 + (dimm << 1)),
 167                                                   rsize);
 168                                 rmap |= (1 << (dimm << 1));
 169                                 nrank++;
 170                         }
 171                 }
 172         }
 173         pci_write_config8(PCI_DEV(0, 0, 4), SCRATCH_DIMM_NUM, ndimm);
 174         pci_write_config8(PCI_DEV(0, 0, 4), SCRATCH_RANK_NUM, nrank);
 175         pci_write_config8(PCI_DEV(0, 0, 4), SCRATCH_RANK_MAP, rmap);
 176 }
 177
 178 static void sdram_set_safe_values(const struct mem_controller *ctrl)
 179 {
 180         /* The purpose of this function is to set initial values for the dram
 181          * size and timings. It will be replaced with the SPD based function
 182          * once the RAM commands are working with these values.
 183          */
 184         u8 regs, val, t, dimm;
 185         u32 spds, tmp;
 186
 187         regs = pci_read_config8(MEMCTRL, 0x6c);
 188         if (regs & (1 << 6))
 189                 printk_debug("DDR2 Detected.\n");
 190         else
 191                 die("ERROR: DDR1 memory detected but not supported by coreboot.\n");
 192
 193         /* Enable DDR2 */
 194         regs |= (1 << 7);
 195         pci_write_config8(MEMCTRL, 0x6c, regs);
 196
 197         /* SPD 5 # of ranks */
 198         pci_write_config8(MEMCTRL, 0x6d, 0xc0);
 199
 200         /**********************************************/
 201         /*          Set DRAM Freq (DDR2 533)          */
 202         /**********************************************/
 203         /* SPD 9 SDRAM Cycle Time */
 204         GET_SPD(dimm, spds, regs, 9);
 205
 206         printk_debug("\nDDRII ");
 207         if (spds <= 0x3d) {
 208                 printk_debug("533");
 209                 val = DDRII_533;
 210                 t = 38;
 211         } else if (spds <= 0x50) {
 212                 printk_debug("400");
 213                 val = DDRII_400;
 214                 t = 50;
 215         } else if (spds <= 0x60) {
 216                 printk_debug("333");
 217                 val = DDRII_333;
 218                 t = 60;
 219         } else if (spds <= 0x75) {
 220                 printk_debug("266");
 221                 val = DDRII_266;
 222                 t = 75;
 223         } else {
 224                 printk_debug("200");
 225                 val = DDRII_200;
 226                 t = 100;
 227         }
 228         /* To store DDRII frequence */
 229         pci_write_config8(PCI_DEV(0, 0, 4), SCRATCH_DRAM_FREQ, val);
 230
 231         /* Manual reset and adjust DLL when DRAM change frequency
 232          * This is a necessary sequence.
 233          */
 234         udelay(2000);
 235         regs = pci_read_config8(MEMCTRL, 0x90);
 236         regs |= 0x7;
 237         pci_write_config8(MEMCTRL, 0x90, regs);
 238         udelay(2000);
 239         regs = pci_read_config8(MEMCTRL, 0x90);
 240         regs &= ~0x7;
 241         regs |= val;
 242         pci_write_config8(MEMCTRL, 0x90, regs);
 243         udelay(2000);
 244         regs = pci_read_config8(MEMCTRL, 0x6b);
 245         regs |= 0xc0;
 246         regs &= ~0x10;
 247         pci_write_config8(MEMCTRL, 0x6b, regs);
 248         udelay(1);
 249         regs |= 0x10;
 250         pci_write_config8(MEMCTRL, 0x6b, regs);
 251         udelay(1);
 252         regs &= ~0xc0;
 253         pci_write_config8(MEMCTRL, 0x6b, regs);
 254         regs = pci_read_config8(MEMCTRL, 0x6f);
 255         regs |= 0x1;
 256         pci_write_config8(MEMCTRL, 0x6f, regs);
 257
 258         /**********************************************/
 259         /*      Set DRAM Timing Setting (DDR2 533)    */
 260         /**********************************************/
 261         /* SPD 9 18 23 25 CAS Latency NB3DRAM_REG62[2:0] */
 262         /* Read SPD byte 18 CAS Latency */
 263         GET_SPD(dimm, spds, regs, SPD_CAS_LAT);
 264         printk_debug("\nCAS Supported ");
 265         if (spds & SPD_CAS_LAT_2)
 266                 printk_debug("2 ");
 267         if (spds & SPD_CAS_LAT_3)
 268                 printk_debug("3 ");
 269         if (spds & SPD_CAS_LAT_4)
 270                 printk_debug("4 ");
 271         if (spds & SPD_CAS_LAT_5)
 272                 printk_debug("5 ");
 273         if (spds & SPD_CAS_LAT_6)
 274                 printk_debug("6");
 275
 276         /* We don't consider CAS = 6, because CX700 doesn't support it */
 277         printk_debug("\n CAS:");
 278         if (spds & SPD_CAS_LAT_5) {
 279                 printk_debug("Starting at CL5");
 280                 val = 0x3;
 281                 /* See whether we can improve it */
 282                 GET_SPD(dimm, tmp, regs, SPD_CAS_LAT_MIN_X_1);
 283                 if ((spds & SPD_CAS_LAT_4) && (tmp < 0x50)) {
 284                         printk_debug("\n... going to CL4");
 285                         val = 0x2;
 286                 }
 287                 GET_SPD(dimm, tmp, regs, SPD_CAS_LAT_MIN_X_2);
 288                 if ((spds & SPD_CAS_LAT_3) && (tmp < 0x50)) {
 289                         printk_debug("\n... going to CL3");
 290                         val = 0x1;
 291                 }
 292         } else {
 293                 printk_debug("Starting at CL4");
 294                 val = 0x2;
 295                 GET_SPD(dimm, tmp, regs, SPD_CAS_LAT_MIN_X_1);
 296                 if ((spds & SPD_CAS_LAT_3) && (tmp < 0x50)) {
 297                         printk_debug("\n... going to CL3");
 298                         val = 0x1;
 299                 }
 300                 GET_SPD(dimm, tmp, regs, SPD_CAS_LAT_MIN_X_2);
 301                 if ((spds & SPD_CAS_LAT_2) && (tmp < 0x50)) {
 302                         printk_debug("\n... going to CL2");
 303                         val = 0x0;
 304                 }
 305         }
 306         regs = pci_read_config8(MEMCTRL, 0x62);
 307         regs &= ~0x7;
 308         regs |= val;
 309         pci_write_config8(MEMCTRL, 0x62, regs);
 310
 311         /* SPD 27 Trp NB3DRAM_REG64[3:2] */
 312         GET_SPD(dimm, spds, regs, SPD_TRP);
 313         printk_debug("\nTrp %d", spds);
 314         spds >>= 2;
 315         for (val = 2; val <= 5; val++) {
 316                 if (spds <= (val * t / 10)) {
 317                         val = val - 2;
 318                         break;
 319                 }
 320         }
 321         val <<= 2;
 322         regs = pci_read_config8(MEMCTRL, 0x64);
 323         regs &= ~0xc;
 324         regs |= val;
 325         pci_write_config8(MEMCTRL, 0x64, regs);
 326
 327         /* SPD 29 Trcd NB3DRAM_REG64[7:6] */
 328         GET_SPD(dimm, spds, regs, SPD_TRCD);
 329         printk_debug("\nTrcd %d", spds);
 330         spds >>= 2;
 331         for (val = 2; val <= 5; val++) {
 332                 if (spds <= (val * t / 10)) {
 333                         val = val - 2;
 334                         break;
 335                 }
 336         }
 337         val <<= 6;
 338         regs = pci_read_config8(MEMCTRL, 0x64);
 339         regs &= ~0xc0;
 340         regs |= val;
 341         pci_write_config8(MEMCTRL, 0x64, regs);
 342
 343         /* SPD 30 Tras NB3DRAM_REG62[7:4] */
 344         GET_SPD(dimm, spds, regs, SPD_TRAS);
 345         printk_debug("\nTras %d", spds);
 346         for (val = 5; val <= 20; val++) {
 347                 if (spds <= (val * t / 10)) {
 348                         val = val - 5;
 349                         break;
 350                 }
 351         }
 352         val <<= 4;
 353         regs = pci_read_config8(MEMCTRL, 0x62);
 354         regs &= ~0xf0;
 355         regs |= val;
 356         pci_write_config8(MEMCTRL, 0x62, regs);
 357
 358         /* SPD 42 SPD 40 Trfc NB3DRAM_REG61[5:0] */
 359         GET_SPD(dimm, spds, regs, SPD_TRFC);
 360         printk_debug("\nTrfc %d", spds);
 361         tmp = spds;
 362         GET_SPD(dimm, spds, regs, SPD_EX_TRC_TRFC);
 363         if (spds & 0x1)
 364                 tmp += 256;
 365         if (spds & 0xe)
 366                 tmp++;
 367         for (val = 8; val <= 71; val++) {
 368                 if (tmp <= (val * t / 10)) {
 369                         val = val - 8;
 370                         break;
 371                 }
 372         }
 373         regs = pci_read_config8(MEMCTRL, 0x61);
 374         regs &= ~0x3f;
 375         regs |= val;
 376         pci_write_config8(MEMCTRL, 0x61, regs);
 377
 378         /* SPD 28 Trrd NB3DRAM_REG63[7:6] */
 379         GET_SPD(dimm, spds, regs, SPD_TRRD);
 380         for (val = 2; val <= 5; val++) {
 381                 if (spds <= (val * t / 10)) {
 382                         val = val - 2;
 383                         break;
 384                 }
 385         }
 386         val <<= 6;
 387         printk_debug("\nTrrd val = 0x%x", val);
 388         regs = pci_read_config8(MEMCTRL, 0x63);
 389         regs &= ~0xc0;
 390         regs |= val;
 391         pci_write_config8(MEMCTRL, 0x63, regs);
 392
 393         /* SPD 36 Twr NB3DRAM_REG61[7:6] */
 394         GET_SPD(dimm, spds, regs, SPD_TWR);
 395         for (val = 2; val <= 5; val++) {
 396                 if (spds <= (val * t / 10)) {
 397                         val = val - 2;
 398                         break;
 399                 }
 400         }
 401         val <<= 6;
 402         printk_debug("\nTwr val = 0x%x", val);
 403
 404         regs = pci_read_config8(MEMCTRL, 0x61);
 405         regs &= ~0xc0;
 406         regs |= val;
 407         pci_write_config8(MEMCTRL, 0x61, regs);
 408
 409         /* SPD 37 Twtr NB3DRAM_REG63[1] */
 410         GET_SPD(dimm, spds, regs, SPD_TWTR);
 411         spds >>= 2;
 412         printk_debug("\nTwtr 0x%x", spds);
 413         if (spds <= (t * 2 / 10))
 414                 val = 0;
 415         else
 416                 val = 1;
 417         val <<= 1;
 418         printk_debug("\nTwtr val = 0x%x", val);
 419
 420         regs = pci_read_config8(MEMCTRL, 0x63);
 421         regs &= ~0x2;
 422         regs |= val;
 423         pci_write_config8(MEMCTRL, 0x63, regs);
 424
 425         /* SPD 38 Trtp NB3DRAM_REG63[3] */
 426         GET_SPD(dimm, spds, regs, SPD_TRTP);
 427         spds >>= 2;
 428         printk_debug("\nTrtp 0x%x", spds);
 429         if (spds <= (t * 2 / 10))
 430                 val = 0;
 431         else
 432                 val = 1;
 433         val <<= 3;
 434         printk_debug("\nTrtp val = 0x%x", val);
 435
 436         regs = pci_read_config8(MEMCTRL, 0x63);
 437         regs &= ~0x8;
 438         regs |= val;
 439         pci_write_config8(MEMCTRL, 0x63, regs);
 440
 441         /**********************************************/
 442         /*           Set DRAM DRDY Setting            */
 443         /**********************************************/
 444         /* Write slowest value to register */
 445         tmp = sizeof(Host_Reg_Val) / sizeof(Host_Reg_Val[0]);
 446         for (val = 0; val < tmp; val += 2)
 447                 pci_write_config8(HOSTCTRL, Host_Reg_Val[val], Host_Reg_Val[val + 1]);
 448
 449         /* F2_RX51[7]=0, disable DRDY timing */
 450         regs = pci_read_config8(HOSTCTRL, 0x51);
 451         regs &= ~0x80;
 452         pci_write_config8(HOSTCTRL, 0x51, regs);
 453
 454         /**********************************************/
 455         /*           Set DRAM BurstLength             */
 456         /**********************************************/
 457         regs = pci_read_config8(MEMCTRL, 0x6c);
 458         for (dimm = 0; dimm < DIMM_SOCKETS; dimm++) {
 459                 if (pci_read_config8(PCI_DEV(0, 0, 4), (SCRATCH_REG_BASE + (dimm << 1)))) {
 460                         spds = get_spd_data(ctrl, dimm, 16);
 461                         if (!(spds & 0x8))
 462                                 break;
 463                 }
 464         }
 465         if (dimm == 2)
 466                 regs |= 0x8;
 467         pci_write_config8(MEMCTRL, 0x6c, regs);
 468         val = pci_read_config8(HOSTCTRL, 0x54);
 469         val &= ~0x10;
 470         if (dimm == 2)
 471                 val |= 0x10;
 472         pci_write_config8(HOSTCTRL, 0x54, val);
 473
 474         /**********************************************/
 475         /*          Set DRAM Driving Setting          */
 476         /**********************************************/
 477         /* DRAM Timing ODT */
 478         tmp = sizeof(Dram_Driving_ODT_CTRL) / sizeof(Dram_Driving_ODT_CTRL[0]);
 479         for (val = 0; val < tmp; val += 2)
 480                 pci_write_config8(MEMCTRL, Dram_Driving_ODT_CTRL[val],
 481                                   Dram_Driving_ODT_CTRL[val + 1]);
 482
 483         regs = pci_read_config8(PCI_DEV(0, 0, 4), SCRATCH_RANK_NUM);
 484         val = pci_read_config8(MEMCTRL, 0xd5);
 485         val &= ~0xaa;
 486         switch (regs) {
 487         case 3:
 488         case 2:
 489                 val |= 0xa0;
 490                 break;
 491         default:
 492                 val |= 0x80;
 493         }
 494         regs = pci_read_config8(PCI_DEV(0, 0, 4), SCRATCH_DIMM_NUM);
 495         if (regs == 1)
 496                 val |= 0xa;
 497         pci_write_config8(MEMCTRL, 0xd5, val);
 498
 499         regs = pci_read_config8(PCI_DEV(0, 0, 4), SCRATCH_DIMM_NUM);
 500         val = pci_read_config8(MEMCTRL, 0xd6);
 501         val &= ~0x2;
 502         if (regs == 1)
 503                 val |= 0x2;
 504         pci_write_config8(MEMCTRL, 0xd6, val);
 505
 506         regs = pci_read_config8(PCI_DEV(0, 0, 4), SCRATCH_RANK_MAP);
 507         tmp = sizeof(ODT_TBL) / sizeof(ODT_TBL[0]);
 508         for (val = 0; val < tmp; val += 3) {
 509                 if (regs == ODT_TBL[val]) {
 510                         pci_write_config8(MEMCTRL, 0xd8, ODT_TBL[val + 1]);
 511                         /* Store DRAM & NB ODT setting in d0f4_Rxd8 */
 512                         pci_write_config8(PCI_DEV(0, 0, 4), SCRATCH_DRAM_NB_ODT, ODT_TBL[val + 2]);
 513                         break;
 514                 }
 515         }
 516
 517         pci_write_config8(MEMCTRL, 0xd9, 0x0a);
 518         regs = pci_read_config8(PCI_DEV(0, 0, 4), SCRATCH_RANK_NUM);
 519         regs--;
 520         regs = regs << 1;
 521         pci_write_config8(MEMCTRL, 0xe0, DQS_DQ_TBL[regs++]);
 522         pci_write_config8(MEMCTRL, 0xe2, DQS_DQ_TBL[regs]);
 523
 524         /* DRAM Timing CS */
 525         pci_write_config8(MEMCTRL, 0xe4, 0x66);
 526
 527         /* DRAM Timing MAA */
 528         val = 0;
 529         for (dimm = 0; dimm < DIMM_SOCKETS; dimm++) {
 530                 if (pci_read_config8(PCI_DEV(0, 0, 4), (SCRATCH_REG_BASE + (dimm << 1)))) {
 531                         spds = get_spd_data(ctrl, dimm, SPD_PRI_WIDTH);
 532                         spds = 64 / spds;
 533                         if (pci_read_config8
 534                             (PCI_DEV(0, 0, 4), (SCRATCH_REG_BASE + (dimm << 1) + 1)))
 535                                 spds = spds << 1;
 536                         val += spds;
 537                 }
 538         }
 539         printk_debug("\nchip #%d", val);
 540         if (val > 18)
 541                 regs = 0xdb;
 542         else
 543                 regs = 0x86;
 544         pci_write_config8(MEMCTRL, 0xe8, regs);
 545
 546         /* DRAM Timing MAB */
 547         pci_write_config8(MEMCTRL, 0xe9, 0x0);
 548
 549         /* DRAM Timing DCLK VT8454C always 0x66 */
 550         pci_write_config8(MEMCTRL, 0xe6, 0xaa);
 551
 552         /**********************************************/
 553         /*            Set DRAM Duty Control           */
 554         /**********************************************/
 555         regs = pci_read_config8(PCI_DEV(0, 0, 4), SCRATCH_RANK_NUM);
 556         switch (regs) {
 557         case 1:
 558         case 2:         /* 1~2 rank */
 559                 val = 0;
 560                 break;
 561         case 3:
 562         case 4:         /* 3~4 rank */
 563                 regs = pci_read_config8(PCI_DEV(0, 0, 4), SCRATCH_DRAM_FREQ);
 564                 if (regs == DDRII_533)
 565                         val = 4;
 566                 else            /* DDRII-400 */
 567                         val = 0;
 568                 break;
 569         }
 570         regs = 0xec;
 571         for (t = 0; t < 4; t++) {
 572                 pci_write_config8(MEMCTRL, regs, Duty_Control_DDR2[val]);
 573                 regs++;
 574                 val++;
 575         }
 576
 577         /**********************************************/
 578         /*            Set DRAM Clock Control          */
 579         /**********************************************/
 580         /* Write Data Phase */
 581         val = pci_read_config8(PCI_DEV(0, 0, 4), SCRATCH_DRAM_FREQ);
 582         regs = pci_read_config8(MEMCTRL, 0x75);
 583         regs &= 0xf0;
 584         switch (val) {
 585         case DDRII_533:
 586                 pci_write_config8(MEMCTRL, 0x74, 0x07);
 587                 regs |= 0x7;
 588                 break;
 589         case DDRII_400:
 590         default:
 591                 pci_write_config8(MEMCTRL, 0x74, 0x05);
 592                 regs |= 0x5;
 593                 break;
 594         }
 595         pci_write_config8(MEMCTRL, 0x75, regs);
 596         pci_write_config8(MEMCTRL, 0x76, 0x80);
 597
 598         /* Clock Phase Control for FeedBack Mode */
 599         regs = pci_read_config8(MEMCTRL, 0x90);
 600 //      regs |= 0x80;
 601         pci_write_config8(MEMCTRL, 0x90, regs);
 602
 603         regs = pci_read_config8(PCI_DEV(0, 0, 4), SCRATCH_DRAM_FREQ);
 604         switch (regs) {
 605         case DDRII_533:
 606                 regs = pci_read_config8(PCI_DEV(0, 0, 4), SCRATCH_RANK_NUM);
 607                 if (regs == 1)
 608                         val = 0;
 609                 else
 610                         val = 3;
 611                 break;
 612         case DDRII_400:
 613         default:
 614                 val = 6;
 615                 break;
 616         }
 617         regs = pci_read_config8(MEMCTRL, 0x91);
 618         regs &= ~0xc0;
 619         regs |= 0x80;
 620         pci_write_config8(MEMCTRL, 0x91, regs);
 621         regs = 0x91;
 622         for (t = 0; t < 3; t++) {
 623                 dimm = pci_read_config8(MEMCTRL, regs);
 624                 dimm &= ~0x7;
 625                 dimm |= ChA_Clk_Phase_DDR2_Table[val];
 626                 pci_write_config8(MEMCTRL, regs, dimm);
 627                 regs++;
 628                 val++;
 629         }
 630
 631         pci_write_config8(MEMCTRL, 0x97, 0x12);
 632         pci_write_config8(MEMCTRL, 0x98, 0x33);
 633
 634         regs = pci_read_config8(PCI_DEV(0, 0, 4), SCRATCH_RANK_0);
 635         val = pci_read_config8(PCI_DEV(0, 0, 4), SCRATCH_RANK_2);
 636         if (regs && val)
 637                 pci_write_config8(MEMCTRL, 0x9d, 0x00);
 638         else
 639                 pci_write_config8(MEMCTRL, 0x9d, 0x0f);
 640
 641         tmp = sizeof(DQ_DQS_Table) / sizeof(DQ_DQS_Table[0]);
 642         for (val = 0; val < tmp; val += 2)
 643                 pci_write_config8(MEMCTRL, DQ_DQS_Table[val], DQ_DQS_Table[val + 1]);
 644         regs = pci_read_config8(PCI_DEV(0, 0, 4), SCRATCH_DRAM_FREQ);
 645         if (regs == DDRII_533)
 646                 pci_write_config8(MEMCTRL, 0x7b, 0xa0);
 647         else
 648                 pci_write_config8(MEMCTRL, 0x7b, 0x10);
 649
 650         /***************************************************/
 651         /*  Set necessary register before DRAM initialize  */
 652         /***************************************************/
 653         tmp = sizeof(Mem_Reg_Init) / sizeof(Mem_Reg_Init[0]);
 654         for (val = 0; val < tmp; val += 3) {
 655                 regs = pci_read_config8(MEMCTRL, Mem_Reg_Init[val]);
 656                 regs &= Mem_Reg_Init[val + 1];
 657                 regs |= Mem_Reg_Init[val + 2];
 658                 pci_write_config8(MEMCTRL, Mem_Reg_Init[val], regs);
 659         }
 660         regs = pci_read_config8(HOSTCTRL, 0x51);
 661         regs &= 0xbf;           // Clear bit 6 Disable Read Around Write
 662         pci_write_config8(HOSTCTRL, 0x51, regs);
 663
 664         regs = pci_read_config8(HOSTCTRL, 0x54);
 665         t = regs >> 5;
 666         val = pci_read_config8(HOSTCTRL, 0x57);
 667         dimm = val >> 5;
 668         if (t == dimm)
 669                 t = 0x0;
 670         else
 671                 t = 0x1;
 672         regs &= ~0x1;
 673         regs |= t;
 674         val &= ~0x1;
 675         val |= t;
 676         pci_write_config8(HOSTCTRL, 0x57, val);
 677
 678         regs = pci_read_config8(HOSTCTRL, 0x51);
 679         regs |= t;
 680         pci_write_config8(HOSTCTRL, 0x51, regs);
 681
 682         regs = pci_read_config8(MEMCTRL, 0x90);
 683         regs &= 0x7;
 684         val = 0;
 685         if (regs < 0x2)
 686                 val = 0x80;
 687         regs = pci_read_config8(MEMCTRL, 0x76);
 688         regs &= 0x80;
 689         regs |= val;
 690         pci_write_config8(MEMCTRL, 0x76, regs);
 691
 692         regs = pci_read_config8(MEMCTRL, 0x6f);
 693         regs |= 0x10;
 694         pci_write_config8(MEMCTRL, 0x6f, regs);
 695
 696         /***************************************************/
 697         /*    Find suitable DQS value for ChA and ChB      */
 698         /***************************************************/
 699         // Set DQS output delay for Channel A
 700         regs = pci_read_config8(PCI_DEV(0, 0, 4), SCRATCH_DRAM_FREQ);
 701         val = pci_read_config8(PCI_DEV(0, 0, 4), SCRATCH_RANK_NUM);
 702         switch (regs) {
 703         case DDRII_533:
 704                 if (val < 2)
 705                         val = 0;
 706                 else
 707                         val = 2;
 708                 break;
 709         case DDRII_400:
 710         default:
 711                 if (val < 2)
 712                         val = 4;
 713                 else
 714                         val = 6;
 715                 break;
 716         }
 717         for (t = 0; t < 2; t++)
 718                 pci_write_config8(MEMCTRL, (0x70 + t), DQSOChA_DDR2_Driving_Table[val + t]);
 719         // Set DQS output delay for Channel B
 720         pci_write_config8(MEMCTRL, 0x72, 0x0);
 721
 722         regs = pci_read_config8(PCI_DEV(0, 0, 4), SCRATCH_RANK_0);
 723         val = pci_read_config8(PCI_DEV(0, 0, 4), SCRATCH_RANK_2);
 724         if (regs && val)
 725                 pci_write_config8(MEMCTRL, 0x73, 0xfd);
 726         else
 727                 pci_write_config8(MEMCTRL, 0x73, 0x01);
 728 }
 729
 730 static void sdram_set_registers(const struct mem_controller *ctrl)
 731 {
 732         c7_cpu_setup(ctrl);
 733         ddr_detect(ctrl);
 734         sdram_set_safe_values(ctrl);
 735 }
 736
 737 static void step_20_21(const struct mem_controller *ctrl)
 738 {
 739         u8 val;
 740
 741         // Step 20
 742         udelay(200);
 743
 744         val = pci_read_config8(PCI_DEV(0, 0, 4), SCRATCH_DRAM_NB_ODT);
 745         if (val & DDR2_ODT_150ohm)
 746                 read32(0x102200);
 747         else
 748                 read32(0x102020);
 749
 750         /* Step 21. Normal operation */
 751         print_spew("RAM Enable 5: Normal operation\n");
 752         do_ram_command(ctrl, RAM_COMMAND_NORMAL);
 753         udelay(3);
 754 }
 755
 756 static void step_2_19(const struct mem_controller *ctrl)
 757 {
 758         u32 i;
 759         u8 val;
 760
 761         //  Step 2
 762         val = pci_read_config8(MEMCTRL, 0x69);
 763         val &= ~0x03;
 764         pci_write_config8(MEMCTRL, 0x69, val);
 765
 766         /* Step 3 Apply NOP. */
 767         print_spew("RAM Enable 1: Apply NOP\n");
 768         do_ram_command(ctrl, RAM_COMMAND_NOP);
 769
 770         udelay(15);
 771
 772         // Step 4
 773         print_spew("SEND: ");
 774         read32(0);
 775         print_spew("OK\n");
 776
 777         // Step 5
 778         udelay(400);
 779
 780         /* 6. Precharge all. Wait tRP. */
 781         print_spew("RAM Enable 2: Precharge all\n");
 782         do_ram_command(ctrl, RAM_COMMAND_PRECHARGE);
 783
 784         // Step 7
 785         print_spew("SEND: ");
 786         read32(0);
 787         print_spew("OK\n");
 788
 789         /* Step 8. Mode register set. */
 790         print_spew("RAM Enable 4: Mode register set\n");
 791         do_ram_command(ctrl, RAM_COMMAND_MRS);  //enable dll
 792
 793         // Step 9
 794         print_spew("SEND: ");
 795
 796         val = pci_read_config8(PCI_DEV(0, 0, 4), SCRATCH_DRAM_NB_ODT);
 797         if (val & DDR2_ODT_150ohm)
 798                 read32(0x102200);       //DDR2_ODT_150ohm
 799         else
 800                 read32(0x102020);
 801         print_spew("OK\n");
 802
 803         // Step 10
 804         print_spew("SEND: ");
 805         read32(0x800);
 806         print_spew("OK\n");
 807
 808         /* Step 11. Precharge all. Wait tRP. */
 809         print_spew("RAM Enable 2: Precharge all\n");
 810         do_ram_command(ctrl, RAM_COMMAND_PRECHARGE);
 811
 812         // Step 12
 813         print_spew("SEND: ");
 814         read32(0x0);
 815         print_spew("OK\n");
 816
 817         /* Step 13. Perform 8 refresh cycles. Wait tRC each time. */
 818         print_spew("RAM Enable 3: CBR\n");
 819         do_ram_command(ctrl, RAM_COMMAND_CBR);
 820
 821         /* JEDEC says only twice, do 8 times for posterity */
 822         // Step 16: Repeat Step 14 and 15 another 7 times
 823         for (i = 0; i < 8; i++) {
 824                 // Step 14
 825                 read32(0);
 826                 print_spew(".");
 827
 828                 // Step 15
 829                 udelay(100);
 830         }
 831
 832         /* Step 17. Mode register set. Wait 200us. */
 833         print_spew("\nRAM Enable 4: Mode register set\n");
 834
 835         //safe value for now, BL=8, WR=4, CAS=4
 836         do_ram_command(ctrl, RAM_COMMAND_MRS);
 837         udelay(200);
 838
 839         /* Use Single Chanel temporarily */
 840         val = pci_read_config8(MEMCTRL, 0x6c);
 841         if (val & 0x8) {        /* Burst Length = 8 */
 842                 val = pci_read_config8(MEMCTRL, 0x62);
 843                 val &= 0x7;
 844                 i = DDR2_MRS_table[4 + val];
 845         } else {
 846                 val = pci_read_config8(MEMCTRL, 0x62);
 847                 val &= 0x7;
 848                 i = DDR2_MRS_table[val];
 849         }
 850
 851         // Step 18
 852         val = pci_read_config8(MEMCTRL, 0x61);
 853         val = val >> 6;
 854         i |= DDR2_Twr_table[val];
 855         read32(i);
 856
 857         printk_debug("MRS = %08x\n", i);
 858
 859         udelay(15);
 860
 861         // Step 19
 862         val = pci_read_config8(PCI_DEV(0, 0, 4), SCRATCH_DRAM_NB_ODT);
 863         if (val & DDR2_ODT_150ohm)
 864                 read32(0x103e00);       //EMRS OCD Default
 865         else
 866                 read32(0x103c20);
 867 }
 868
 869 static void sdram_set_vr(const struct mem_controller *ctrl, u8 num)
 870 {
 871         u8 reg, val;
 872         val = 0x54 + (num >> 1);
 873         reg = pci_read_config8(MEMCTRL, val);
 874         reg &= (0xf << (4 * (num & 0x1)));
 875         reg |= (((0x8 | num) << 4) >> (4 * (num & 0x1)));
 876         pci_write_config8(MEMCTRL, val, reg);
 877 }
 878 static void sdram_ending_addr(const struct mem_controller *ctrl, u8 num)
 879 {
 880         u8 reg, val;
 881         /* Set Ending Address */
 882         val = 0x40 + num;
 883         reg = pci_read_config8(MEMCTRL, val);
 884         reg += 0x10;
 885         pci_write_config8(MEMCTRL, val, reg);
 886         /* Set Beginning Address */
 887         val = 0x48 + num;
 888         pci_write_config8(MEMCTRL, val, 0x0);
 889 }
 890
 891 static void sdram_clear_vr_addr(const struct mem_controller *ctrl, u8 num)
 892 {
 893         u8 reg, val;
 894         val = 0x54 + (num >> 1);
 895         reg = pci_read_config8(MEMCTRL, val);
 896         reg = ~(0x80 >> (4 * (num & 0x1)));
 897         pci_write_config8(MEMCTRL, val, reg);
 898         val = 0x40 + num;
 899         reg = pci_read_config8(MEMCTRL, val);
 900         reg -= 0x10;
 901         pci_write_config8(MEMCTRL, val, reg);
 902         val = 0x48 + num;
 903         pci_write_config8(MEMCTRL, val, 0x0);
 904 }
 905
 906 /* Perform sizing DRAM by dynamic method */
 907 static void sdram_calc_size(const struct mem_controller *ctrl, u8 num)
 908 {
 909         u8 ca, ra, ba, reg;
 910         ba = pci_read_config8(PCI_DEV(0, 0, 4), SCRATCH_FLAGS);
 911         if (ba == 8) {
 912                 write8(0, 0x0d);
 913                 ra = read8(0);
 914                 write8((1 << SDRAM1X_RA_12_8bk), 0x0c);
 915                 ra = read8(0);
 916
 917                 write8(0, 0x0a);
 918                 ca = read8(0);
 919                 write8((1 << SDRAM1X_CA_09_8bk), 0x0c);
 920                 ca = read8(0);
 921
 922                 write8(0, 0x03);
 923                 ba = read8(0);
 924                 write8((1 << SDRAM1X_BA2_8bk), 0x02);
 925                 ba = read8(0);
 926                 write8((1 << SDRAM1X_BA1_8bk), 0x01);
 927                 ba = read8(0);
 928         } else {
 929                 write8(0, 0x0f);
 930                 ra = read8(0);
 931                 write8((1 << SDRAM1X_RA_14), 0x0e);
 932                 ra = read8(0);
 933                 write8((1 << SDRAM1X_RA_13), 0x0d);
 934                 ra = read8(0);
 935                 write8((1 << SDRAM1X_RA_12), 0x0c);
 936                 ra = read8(0);
 937
 938                 write8(0, 0x0c);
 939                 ca = read8(0);
 940                 write8((1 << SDRAM1X_CA_12), 0x0b);
 941                 ca = read8(0);
 942                 write8((1 << SDRAM1X_CA_11), 0x0a);
 943                 ca = read8(0);
 944                 write8((1 << SDRAM1X_CA_09), 0x09);
 945                 ca = read8(0);
 946
 947                 write8(0, 0x02);
 948                 ba = read8(0);
 949                 write8((1 << SDRAM1X_BA1), 0x01);
 950                 ba = read8(0);
 951         }
 952
 953         if (ra < 10 || ra > 15)
 954                 die("bad RA");
 955         if (ca < 8 || ca > 12)
 956                 die("bad CA");
 957         if (ba < 1 || ba > 3)
 958                 die("bad BA");
 959
 960         /* Calculate MA type save to scratch register */
 961         reg = 0;
 962
 963         switch (ra) {
 964         case 12:
 965                 reg |= MA_12_Row;
 966                 break;
 967         case 13:
 968                 reg |= MA_13_Row;
 969                 break;
 970         case 14:
 971                 reg |= MA_14_Row;
 972                 break;
 973         default:
 974                 reg |= MA_15_Row;
 975         }
 976
 977         switch (ca) {
 978         case 9:
 979                 reg |= MA_9_Column;
 980                 break;
 981         case 10:
 982                 reg |= MA_10_Column;
 983                 break;
 984         case 11:
 985                 reg |= MA_11_Column;
 986                 break;
 987         default:
 988                 reg |= MA_12_Column;
 989         }
 990
 991         switch (ba) {
 992         case 3:
 993                 reg |= MA_8_Bank;
 994                 break;
 995         default:
 996                 reg |= MA_4_Bank;
 997         }
 998
 999         pci_write_config8(PCI_DEV(0, 0, 4), (SCRATCH_RANK0_MA_REG + num), reg);
1000
1001         if (ra >= 13)
1002                 pci_write_config8(PCI_DEV(0, 0, 4), SCRATCH_DRAM_256M_BIT, 1);
1003
1004         /* Calculate rank size save to scratch register */
1005         ra = ra + ca + ba + 3 - 26;     /* 1 unit = 64M */
1006         ra = 1 << ra;
1007         pci_write_config8(PCI_DEV(0, 0, 4), (SCRATCH_RANK0_SIZE_REG + num), ra);
1008 }
1009
1010 static void sdram_enable(const struct mem_controller *ctrl)
1011 {
1012         u8 reg8;
1013         u8 val, i;
1014         device_t dev;
1015         u8 dl, dh;
1016         u32 quot;
1017
1018         /* Init Present Bank */
1019         val = sizeof(Init_Rank_Reg_Table) / sizeof(Init_Rank_Reg_Table[0]);
1020         for (i = 0; i < val; i++)
1021                 pci_write_config8(MEMCTRL, Init_Rank_Reg_Table[i], 0x0);
1022
1023         /* Init other banks */
1024         for (i = 0; i < 4; i++) {
1025                 reg8 = pci_read_config8(PCI_DEV(0, 0, 4), (SCRATCH_RANK_0 + i));
1026                 if (reg8) {
1027                         sdram_set_vr(ctrl, i);
1028                         sdram_ending_addr(ctrl, i);
1029                         step_2_19(ctrl);
1030                         step_20_21(ctrl);
1031                         sdram_clear_vr_addr(ctrl, i);
1032                 }
1033         }
1034
1035 #ifdef MEM_WIDTH_32BIT_MODE
1036         /****************************************************************/
1037         /*                      Set Dram 32bit Mode                     */
1038         /****************************************************************/
1039         reg8 = pci_read_config8(MEMCTRL, 0x6c);
1040         reg8 |= 0x20;
1041         pci_write_config(MEMCTRL, 0x6c, reg8);
1042 #endif
1043
1044         /****************************************************************/
1045         /* Find the DQSI Low/High bound and save it to Scratch register */
1046         /****************************************************************/
1047         for (dl = 0; dl < 0x3f; dl += 2) {
1048                 reg8 = dl & 0x3f;
1049                 reg8 |= 0x80;   /* Set Manual Mode */
1050                 pci_write_config8(MEMCTRL, 0x77, reg8);
1051                 for (i = 0; i < 4; i++) {
1052                         reg8 = pci_read_config8(PCI_DEV(0, 0, 4), (SCRATCH_RANK_0 + i));
1053                         if (reg8) {
1054                                 sdram_set_vr(ctrl, i);
1055                                 sdram_ending_addr(ctrl, i);
1056                                 write32(0, 0x55555555);
1057                                 write32(4, 0x55555555);
1058                                 udelay(15);
1059                                 if (read32(0) != 0x55555555)
1060                                         break;
1061                                 if (read32(4) != 0x55555555)
1062                                         break;
1063                                 write32(0, 0xaaaaaaaa);
1064                                 write32(4, 0xaaaaaaaa);
1065                                 udelay(15);
1066                                 if (read32(0) != 0xaaaaaaaa)
1067                                         break;
1068                                 if (read32(4) != 0xaaaaaaaa)
1069                                         break;
1070                                 sdram_clear_vr_addr(ctrl, i);
1071                         }
1072                 }
1073                 if (i == 4)
1074                         break;
1075                 else
1076                         sdram_clear_vr_addr(ctrl, i);
1077         }
1078         printk_debug("\nDQSI Low %08x", dl);
1079         for (dh = dl; dh < 0x3f; dh += 2) {
1080                 reg8 = dh & 0x3f;
1081                 reg8 |= 0x80;   /* Set Manual Mode */
1082                 pci_write_config8(MEMCTRL, 0x77, reg8);
1083                 for (i = 0; i < 4; i++) {
1084                         reg8 = pci_read_config8(PCI_DEV(0, 0, 4), (SCRATCH_RANK_0 + i));
1085                         if (reg8) {
1086                                 sdram_set_vr(ctrl, i);
1087                                 sdram_ending_addr(ctrl, i);
1088
1089                                 write32(0, 0x55555555);
1090                                 write32(4, 0x55555555);
1091                                 udelay(15);
1092                                 if (read32(0) != 0x55555555)
1093                                         break;
1094                                 if (read32(4) != 0x55555555)
1095                                         break;
1096                                 write32(0, 0xaaaaaaaa);
1097                                 write32(4, 0xaaaaaaaa);
1098                                 udelay(15);
1099                                 if (read32(0) != 0xaaaaaaaa)
1100                                         break;
1101                                 if (read32(4) != 0xaaaaaaaa)
1102                                         break;
1103                                 sdram_clear_vr_addr(ctrl, i);
1104                         }
1105                 }
1106                 if (i != 4) {
1107                         sdram_clear_vr_addr(ctrl, i);
1108                         break;
1109                 }
1110         }
1111         printk_debug("\nDQSI High %02x", dh);
1112         pci_write_config8(PCI_DEV(0, 0, 4), SCRATCH_CHA_DQSI_LOW_REG, dl);
1113         pci_write_config8(PCI_DEV(0, 0, 4), SCRATCH_CHA_DQSI_HIGH_REG, dh);
1114         reg8 = pci_read_config8(MEMCTRL, 0X90) & 0X7;
1115         val = DQSI_Rate_Table[reg8];
1116         quot = dh - dl;
1117         quot = quot * val;
1118         quot >>= 4;
1119         val = quot + dl;
1120         pci_write_config8(PCI_DEV(0, 0, 4), SCRATCH_ChA_DQSI_REG, val);
1121         reg8 = val & 0x3f;
1122         reg8 |= 0x80;
1123         pci_write_config8(MEMCTRL, 0x77, reg8);
1124
1125         /****************************************************************/
1126         /*     Find out the lowest Bank Interleave and Set Register     */
1127         /****************************************************************/
1128 #if 0
1129         //TODO
1130         reg8 = pci_read_config8(MEMCTRL, 0x69);
1131         reg8 &= ~0xc0;
1132         reg8 |= 0x80;           //8 banks
1133         pci_write_config8(MEMCTRL, 0x69, reg8);
1134 #endif
1135         dl = 2;
1136         for (i = 0; i < 4; i++) {
1137                 reg8 = pci_read_config8(PCI_DEV(0, 0, 4), (SCRATCH_RANK_0 + i));
1138                 if (reg8) {
1139                         reg8 = get_spd_data(ctrl, (i >> 1), 17);
1140                         sdram_set_vr(ctrl, i);
1141                         sdram_ending_addr(ctrl, i);
1142                         if (reg8 == 4) {
1143                                 write8(0, 0x02);
1144                                 val = read8(0);
1145                                 write8((1 << SDRAM1X_BA1), 0x01);
1146                                 val = read8(0);
1147                         } else {
1148                                 write8(0, 0x03);
1149                                 val = read8(0);
1150                                 write8((1 << SDRAM1X_BA2_8bk), 0x02);
1151                                 val = read8(0);
1152                                 write8((1 << SDRAM1X_BA1_8bk), 0x01);
1153                                 val = read8(0);
1154                         }
1155                         if (val < dl)
1156                                 dl = val;
1157                         sdram_clear_vr_addr(ctrl, i);
1158                 }
1159         }
1160         dl <<= 6;
1161         reg8 = pci_read_config8(MEMCTRL, 0x69);
1162         reg8 &= ~0xc0;
1163         reg8 |= dl;
1164         pci_write_config8(MEMCTRL, 0x69, reg8);
1165
1166         /****************************************************************/
1167         /*               DRAM Sizing and Fill MA type                   */
1168         /****************************************************************/
1169         for (i = 0; i < 4; i++) {
1170                 val = pci_read_config8(PCI_DEV(0, 0, 4), (SCRATCH_RANK_0 + i));
1171                 if (val) {
1172                         reg8 = get_spd_data(ctrl, (i >> 1), 17);
1173                         pci_write_config8(PCI_DEV(0, 0, 4), SCRATCH_FLAGS, reg8);
1174                         if (reg8 == 4) {
1175                                 /* Use MA Type 3 for DRAM sizing */
1176                                 reg8 = pci_read_config8(MEMCTRL, 0x50);
1177                                 reg8 &= 0x11;
1178                                 reg8 |= 0x66;
1179                                 pci_write_config8(MEMCTRL, 0x50, reg8);
1180                                 pci_write_config8(MEMCTRL, 0x51, reg8);
1181                         } else {
1182                                 /* Use MA Type 5 for DRAM sizing */
1183                                 reg8 = pci_read_config8(MEMCTRL, 0x50);
1184                                 reg8 &= 0x11;
1185                                 reg8 |= 0xaa;
1186                                 pci_write_config8(MEMCTRL, 0x50, reg8);
1187                                 pci_write_config8(MEMCTRL, 0x51, reg8);
1188                                 reg8 = pci_read_config8(MEMCTRL, 0x53);
1189                                 reg8 &= 0x0f;
1190                                 reg8 |= 0x90;
1191                                 pci_write_config8(MEMCTRL, 0x53, reg8);
1192                         }
1193                         sdram_set_vr(ctrl, i);
1194                         val = 0x40 + i;
1195                         reg8 = pci_read_config8(MEMCTRL, val);
1196                         /* max size 3G for new MA table */
1197                         reg8 += 0x30;
1198                         pci_write_config8(MEMCTRL, val, reg8);
1199                         /* Set Beginning Address */
1200                         val = 0x48 + i;
1201                         pci_write_config8(MEMCTRL, val, 0x0);
1202
1203                         sdram_calc_size(ctrl, i);
1204
1205                         /* Clear */
1206                         val = 0x54 + (i >> 1);
1207                         reg8 = pci_read_config8(MEMCTRL, val);
1208                         reg8 = ~(0x80 >> (4 * (i & 0x1)));
1209                         pci_write_config8(MEMCTRL, val, reg8);
1210                         val = 0x40 + i;
1211                         reg8 = pci_read_config8(MEMCTRL, val);
1212                         reg8 -= 0x30;
1213                         pci_write_config8(MEMCTRL, val, reg8);
1214                         val = 0x48 + i;
1215                         pci_write_config8(MEMCTRL, val, 0x0);
1216
1217                 }
1218         }
1219         /* Clear MA Type */
1220         reg8 = pci_read_config8(MEMCTRL, 0x50);
1221         reg8 &= 0x11;
1222         pci_write_config8(MEMCTRL, 0x50, reg8);
1223         pci_write_config8(MEMCTRL, 0x51, reg8);
1224         reg8 = pci_read_config8(MEMCTRL, 0x6b);
1225         reg8 &= ~0x08;
1226         pci_write_config8(MEMCTRL, 0x6b, reg8);
1227
1228         /****************************************************************/
1229         /*             DRAM re-initialize for burst length              */
1230         /****************************************************************/
1231         for (i = 0; i < 4; i++) {
1232                 reg8 = pci_read_config8(PCI_DEV(0, 0, 4), (SCRATCH_RANK_0 + i));
1233                 if (reg8) {
1234                         sdram_set_vr(ctrl, i);
1235                         sdram_ending_addr(ctrl, i);
1236                         step_2_19(ctrl);
1237                         step_20_21(ctrl);
1238                         sdram_clear_vr_addr(ctrl, i);
1239                 }
1240         }
1241
1242         /****************************************************************/
1243         /*                    Set the MA Type                           */
1244         /****************************************************************/
1245         reg8 = pci_read_config8(MEMCTRL, 0x50);
1246         reg8 &= 0x11;
1247         pci_write_config8(MEMCTRL, 0x50, reg8);
1248
1249         reg8 = pci_read_config8(MEMCTRL, 0x51);
1250         reg8 &= 0x11;
1251         pci_write_config8(MEMCTRL, 0x51, reg8);
1252
1253         reg8 = pci_read_config8(MEMCTRL, 0x6b);
1254         reg8 &= ~0x08;
1255         pci_write_config8(MEMCTRL, 0x6b, reg8);
1256
1257         for (i = 0; i < 4; i += 2) {
1258                 reg8 = pci_read_config8(PCI_DEV(0, 0, 4), (SCRATCH_RANK_0 + i));
1259                 if (reg8) {
1260                         reg8 = pci_read_config8(PCI_DEV(0, 0, 4), (SCRATCH_RANK0_MA_REG + i));
1261                         reg8 &= (MA_Bank + MA_Column);
1262                         val = pci_read_config8(MEMCTRL, 0x50);
1263                         if (i == 0) {
1264                                 reg8 <<= 4;
1265                                 val &= 0x1f;
1266                         } else
1267                                 val &= 0xf1;
1268                         val |= reg8;
1269                         pci_write_config8(MEMCTRL, 0x50, val);
1270                 }
1271         }
1272
1273         /****************************************************************/
1274         /*                 Set Start and Ending Address                 */
1275         /****************************************************************/
1276         dl = 0;                 /* Begin Address */
1277         dh = 0;                 /* Ending Address */
1278         for (i = 0; i < 4; i++) {
1279                 reg8 = pci_read_config8(PCI_DEV(0, 0, 4), (SCRATCH_RANK_0 + i));
1280                 if (reg8) {
1281                         reg8 = pci_read_config8(PCI_DEV(0, 0, 4), (SCRATCH_RANK0_SIZE_REG + i));
1282                         if (reg8 == 0)
1283                                 continue;
1284                         dh += reg8;
1285                         pci_write_config8(MEMCTRL, (0x40 + i), dh);
1286                         pci_write_config8(MEMCTRL, (0x48 + i), dl);
1287                         dl = dh;
1288                 }
1289         }
1290         dh <<= 2;
1291         // F7_Rx57 Ending address mirror register
1292         pci_write_config8(PCI_DEV(0, 0, 7), 0x57, dh);
1293         dev = pci_locate_device(PCI_ID(0x1106, 0x324e), 0);
1294         pci_write_config8(dev, 0x57, dh);
1295         // LOW TOP Address
1296         pci_write_config8(MEMCTRL, 0x88, dh);
1297         pci_write_config8(MEMCTRL, 0x85, dh);
1298         // also program vlink mirror
1299         pci_write_config8(PCI_DEV(0, 0, 7), 0xe5, dh);
1300
1301         /****************************************************************/
1302         /*            Set Physical to Virtual Rank mapping              */
1303         /****************************************************************/
1304         pci_write_config32(MEMCTRL, 0x54, 0x0);
1305         for (i = 0; i < 4; i++) {
1306                 reg8 = pci_read_config8(PCI_DEV(0, 0, 4), (SCRATCH_RANK_0 + i));
1307                 if (reg8) {
1308                         reg8 = pci_read_config8(MEMCTRL, (0x54 + (i >> 1)));
1309                         if (i & 0x1) {  /* Odd Rank */
1310                                 reg8 &= 0xf0;
1311                                 reg8 |= (0x8 | i);
1312                         } else {        /* Even Rank */
1313
1314                                 reg8 &= 0x0f;
1315                                 reg8 |= ((0x8 | i) << 4);
1316                         }
1317                         pci_write_config8(MEMCTRL, (0x54 + (i >> 1)), reg8);
1318                 }
1319         }
1320
1321         /****************************************************************/
1322         /*                   Set DRAM Refresh Counter                   */
1323         /****************************************************************/
1324         val = pci_read_config8(MEMCTRL, 0X90) & 0X7;
1325         val <<= 1;
1326         reg8 = pci_read_config8(PCI_DEV(0, 0, 4), SCRATCH_DRAM_256M_BIT);
1327         if (reg8)
1328                 val++;
1329         pci_write_config8(MEMCTRL, 0x6a, REFC_Table[val]);
1330
1331         /****************************************************************/
1332         /*  Chipset Performance UP and other setting after DRAM Sizing  */
1333         /****************************************************************/
1334         /* Dram Registers */
1335         val = sizeof(Dram_Table) / sizeof(Dram_Table[0]);
1336         for (i = 0; i < val; i += 3) {
1337                 reg8 = pci_read_config8(MEMCTRL, Dram_Table[i]);
1338                 reg8 &= Dram_Table[i + 1];
1339                 reg8 |= Dram_Table[i + 2];
1340                 pci_write_config8(MEMCTRL, Dram_Table[i], reg8);
1341         }
1342
1343         /* Host Registers */
1344         val = sizeof(Host_Table) / sizeof(Host_Table[0]);
1345         for (i = 0; i < val; i += 3) {
1346                 reg8 = pci_read_config8(HOSTCTRL, Host_Table[i]);
1347                 reg8 &= Host_Table[i + 1];
1348                 reg8 |= Host_Table[i + 2];
1349                 pci_write_config8(HOSTCTRL, Host_Table[i], reg8);
1350         }
1351
1352         /* PM Registers */
1353 #ifdef SETUP_PM_REGISTERS
1354         val = sizeof(PM_Table) / sizeof(PM_Table[0]);
1355         for (i = 0; i < val; i += 3) {
1356                 reg8 = pci_read_config8(PCI_DEV(0, 0, 4), PM_Table[i]);
1357                 reg8 &= PM_Table[i + 1];
1358                 reg8 |= PM_Table[i + 2];
1359                 pci_write_config8(PCI_DEV(0, 0, 4), PM_Table[i], reg8);
1360         }
1361 #endif
1362         pci_write_config8(HOSTCTRL, 0x5d, 0xb2);
1363
1364         /****************************************************************/
1365         /*              UMA registers for N-series projects             */
1366         /****************************************************************/
1367
1368         /* Manual setting frame buffer bank */
1369         for (i = 0; i < 4; i++) {
1370                 reg8 = pci_read_config8(PCI_DEV(0, 0, 4), (SCRATCH_RANK_0 + i));
1371                 if (reg8)
1372                         val = i;
1373         }
1374         pci_write_config8(MEMCTRL, 0xb0, val);
1375         reg8 = 0x40;            // Frame buffer size 64M
1376         reg8 |= 0x80;           // VGA Enable
1377         reg8 |= 0x0a;           // A[31:28] = 1010b
1378         pci_write_config8(MEMCTRL, 0xa1, reg8);
1379
1380 #ifdef ECC
1381         // Clear Ecc
1382         outl(0x80000180, 0xcf8);
1383         outb(0xff, 0xcfc);
1384         // Enable Ecc
1385         outl(0x80000188, 0xcf8);
1386         outb(0xcf, 0xcfc);
1387
1388         reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xa5);
1389         reg8 |= 0x10;
1390         pci_write_config8(PCI_DEV(0, 0, 0), 0xa5, reg8);
1391
1392         reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0x91);
1393         reg8 |= 0x20;
1394         pci_write_config8(PCI_DEV(0, 0, 0), 0x91, reg8);
1395 #endif
1396
1397         static const struct regmask {
1398                 u8 reg;
1399                 u8 mask;
1400                 u8 val;
1401         } b0d1f0[] = {
1402                 { 0x40, 0x00, 0x8b},
1403                 { 0x41, 0x80, 0x43},
1404                 { 0x42, 0x00, 0x62},
1405                 { 0x43, 0x00, 0x44},
1406                 { 0x44, 0x00, 0x34},
1407                 { 0x45, 0x00, 0x72}
1408         }, b0d0f3[] = {
1409                 { 0x53, 0xf0, 0x0f},
1410                 { 0x60, 0x00, 0x03},
1411                 { 0x65, 0x00, 0xd9},
1412                 { 0x66, 0x00, 0x80},
1413                 { 0x67, 0x00, 0x00},
1414                 { 0x68, 0x00, 0x01},
1415                 { 0x69, 0xe0, 0x03},
1416                 { 0x6b, 0x00, 0x10},
1417                 { 0x6c, 0xc1, 0x08},
1418                 { 0x6e, 0x00, 0x89},
1419                 { 0x6f, 0x00, 0x51},
1420                 { 0x75, ~0x40, 0x40},
1421                 { 0x76, 0x8f, 0x00},
1422                 { 0x7b, 0x00, 0xa0},
1423                 { 0x86, 0x01, 0x24},
1424                 { 0x86, 0x04, 0x29},
1425                 { 0x8c, 0x00, 0x00},
1426                 { 0x8d, 0x00, 0x00},
1427                 { 0x95, ~0x40, 0x00},
1428                 { 0xa2, 0x00, 0x44},
1429                 { 0xb1, 0x00, 0xaa}
1430         }, b0d0f0[] = {
1431                 { 0x4d, 0x00, 0x24},
1432                 { 0x4f, 0x00, 0x01},
1433                 { 0xbc, 0x00, 0x21},
1434                 { 0xbe, 0x00, 0x00},
1435                 { 0xbf, 0x7f, 0x80}
1436         }, b0d17f0[] = {
1437                 { 0x40, ~0x01, 0x01},           // enable timer/counter shadow registers
1438                 { 0x67, ~0x03, 0x01},
1439                 { 0x5b, ~0x01, 0x00},
1440                 { 0x8d, ~0x02, 0x02},
1441                 { 0x97, ~0x80, 0x00},
1442                 { 0xd2, ~0x18, 0x00},
1443                 { 0xe2, ~0x36, 0x06},
1444                 { 0xe4, ~0x80, 0x00},
1445                 { 0xe5, 0x00, 0x40},
1446                 { 0xe6, 0x00, 0x20},
1447                 { 0xe7, ~0xd0, 0xc0},
1448                 { 0xec, ~0x08, 0x00}
1449         }, b0d17f7[] = {
1450                 { 0x4e, ~0x80, 0x80},
1451                 { 0x4f, ~(1 << 6), 1 << 6 },    /* PG_CX700: 14.1.1 enable P2P Bridge Header for External PCI Bus */
1452                 { 0x74, ~0x00, 0x04},           /* PG_CX700: 14.1.2 APIC FSB directly up to snmic, not on pci */
1453                 { 0x7c, ~0x00, 0x02},           /* PG_CX700: 14.1.1 APIC FSB directly up to snmic, not on pci */
1454                 { 0xe6, 0x0, 0x04}              // MSI post
1455         }, b0d19f0[] = {        /* P2PE */
1456                 { 0x42, ~0x08, 0x08},           // Disable HD Audio,
1457                 { 0x40, ~0xc0, 0x80}            // 14.1.3.1.1 of the PG: extended cfg mode for pcie. enable capability, but don't activate
1458         }, b0d0f2[] = {
1459                 { 0x50, ~0x40, 0x88},
1460                 { 0x51, 0x80, 0x7b},
1461                 { 0x52, 0x90, 0x6f},
1462                 { 0x53, 0x00, 0x88},
1463                 { 0x54, 0xe4, 0x16},
1464                 { 0x55, 0xf2, 0x04},
1465                 { 0x56, 0x0f, 0x00},
1466                 { 0x57, ~0x04, 0x00},
1467                 { 0x5d, 0x00, 0xb2},
1468                 { 0x5e, 0x00, 0x88},
1469                 { 0x5f, 0x00, 0xc7},
1470                 { 0x5c, 0x00, 0x01}
1471         };
1472
1473         REGISTERPRESET(0, 0, 0, b0d0f0);
1474         REGISTERPRESET(0, 0, 2, b0d0f2);
1475         REGISTERPRESET(0, 0, 3, b0d0f3);
1476         REGISTERPRESET(0, 1, 0, b0d1f0);
1477         REGISTERPRESET(0, 17, 0, b0d17f0);
1478         REGISTERPRESET(0, 17, 7, b0d17f7);
1479         REGISTERPRESET(0, 19, 0, b0d19f0);
1480 }