src/northbridge/via/cx700/raminit.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007-2009 coresystems GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18  */
  19
  20 #include <types.h>
  21 #include <spd.h>
  22 #include <spd_ddr2.h>
  23 #include <sdram_mode.h>
  24 #include <delay.h>
  25 #include "cx700_registers.h"
  26
  27 /* Debugging macros. */
  28 #if CONFIG_DEBUG_RAM_SETUP
  29 #define PRINTK_DEBUG(x...)      printk(BIOS_DEBUG, x)
  30 #else
  31 #define PRINTK_DEBUG(x...)
  32 #endif
  33
  34 #define RAM_COMMAND_NORMAL      0x0
  35 #define RAM_COMMAND_NOP         0x1
  36 #define RAM_COMMAND_PRECHARGE   0x2
  37 #define RAM_COMMAND_MRS         0x3
  38 #define RAM_COMMAND_CBR         0x4
  39
  40 #define HOSTCTRL                PCI_DEV(0, 0, 2)
  41 #define MEMCTRL                 PCI_DEV(0, 0, 3)
  42
  43 #define DDRII_666       0x5
  44 #define DDRII_533       0x4
  45 #define DDRII_400       0x3
  46 #define DDRII_333       0x2
  47 #define DDRII_266       0x1
  48 #define DDRII_200       0x0
  49
  50 #define OHM_150 1
  51
  52 #ifdef  MEM_WIDTH_32BIT_MODE
  53 #define SDRAM1X_RA_14           30
  54 #define SDRAM1X_RA_13           29
  55 #define SDRAM1X_RA_12           28
  56 #define SDRAM1X_RA_12_8bk       26
  57 #define SDRAM1X_CA_12           15
  58 #define SDRAM1X_CA_11           14
  59 #define SDRAM1X_CA_09           11
  60 #define SDRAM1X_CA_09_8bk       11
  61 #define SDRAM1X_BA1             13
  62 #define SDRAM1X_BA2_8bk         14
  63 #define SDRAM1X_BA1_8bk         13
  64 #else
  65 #define SDRAM1X_RA_14           31
  66 #define SDRAM1X_RA_13           30
  67 #define SDRAM1X_RA_12           29
  68 #define SDRAM1X_RA_12_8bk       27
  69 #define SDRAM1X_CA_12           16
  70 #define SDRAM1X_CA_11           15
  71 #define SDRAM1X_CA_09           12
  72 #define SDRAM1X_CA_09_8bk       12
  73 #define SDRAM1X_BA1             14
  74 #define SDRAM1X_BA2_8bk         15
  75 #define SDRAM1X_BA1_8bk         14
  76 #endif
  77
  78 #define MA_Column       0x06
  79 #define MA_Bank         0x08
  80 #define MA_Row          0x30
  81 #define MA_4_Bank       0x00
  82 #define MA_8_Bank       0x08
  83 #define MA_12_Row       0x00
  84 #define MA_13_Row       0x10
  85 #define MA_14_Row       0x20
  86 #define MA_15_Row       0x30
  87 #define MA_9_Column     0x00
  88 #define MA_10_Column    0x02
  89 #define MA_11_Column    0x04
  90 #define MA_12_Column    0x06
  91
  92 #define GET_SPD(i, val, tmp, reg)                                                               \
  93         do{                                                                                     \
  94                 val = 0;                                                                        \
  95                 tmp = 0;                                                                        \
  96                 for(i = 0; i < 2; i++)  {                                                       \
  97                         if(pci_read_config8(PCI_DEV(0, 0, 4), (SCRATCH_REG_BASE + (i << 1)))) { \
  98                                 tmp = get_spd_data(ctrl, i, reg);                               \
  99                                 if(tmp > val)                                                   \
 100                                         val = tmp;                                              \
 101                         }                                                                       \
 102                 }                                                                               \
 103         } while ( 0 )
 104
 105 #define REGISTERPRESET(bus,dev,fun,bdfspec) \
 106         { u8 i, reg; \
 107                 for (i=0; i<(sizeof((bdfspec))/sizeof(struct regmask)); i++) { \
 108                         printk(BIOS_DEBUG, "Writing bus " #bus " dev " #dev " fun " #fun " register "); \
 109                         printk(BIOS_DEBUG, "%02x", (bdfspec)[i].reg); \
 110                         printk(BIOS_DEBUG, "\n"); \
 111                         reg = pci_read_config8(PCI_DEV((bus), (dev), (fun)), (bdfspec)[i].reg); \
 112                         reg &= (bdfspec)[i].mask; \
 113                         reg |= (bdfspec)[i].val; \
 114                         pci_write_config8(PCI_DEV((bus), (dev), (fun)), (bdfspec)[i].reg, reg); \
 115                 } \
 116         }
 117
 118
 119 static void do_ram_command(const struct mem_controller *ctrl, u8 command)
 120 {
 121         u8 reg;
 122
 123         reg = pci_read_config8(MEMCTRL, 0x6b);
 124         reg &= 0xf8;            /* Clear bits 2-0. */
 125         reg |= command;
 126         pci_write_config8(MEMCTRL, 0x6b, reg);
 127
 128         PRINTK_DEBUG("    Sending RAM command 0x%02x\n", reg);
 129 }
 130
 131 // TODO factor out to another file
 132 static void c7_cpu_setup(const struct mem_controller *ctrl)
 133 {
 134         u8 size, i;
 135         size = sizeof(Reg_Val) / sizeof(Reg_Val[0]);
 136         for (i = 0; i < size; i += 2)
 137                 pci_write_config8(HOSTCTRL, Reg_Val[i], Reg_Val[i + 1]);
 138 }
 139
 140 static void ddr_detect(const struct mem_controller *ctrl)
 141 {
 142         /* FIXME: Only supports 2 ranks per DIMM */
 143         u8 val, rsize, dimm;
 144         u8 nrank = 0;
 145         u8 ndimm = 0;
 146         u8 rmap = 0;
 147         for (dimm = 0; dimm < DIMM_SOCKETS; dimm++) {
 148                 val = get_spd_data(ctrl, dimm, 0);
 149                 if ((val == 0x80) || (val == 0xff)) {
 150                         ndimm++;
 151                         rsize = get_spd_data(ctrl, dimm, SPD_RANK_SIZE);
 152                         /* unit is 128M */
 153                         rsize = (rsize << 3) | (rsize >> 5);
 154                         val =
 155                             get_spd_data(ctrl, dimm,
 156                                          SPD_MOD_ATTRIB_RANK) & SPD_MOD_ATTRIB_RANK_NUM_MASK;
 157                         switch (val) {
 158                         case 1:
 159                                 pci_write_config8(PCI_DEV(0, 0, 4), (SCRATCH_RANK_1 + (dimm << 1)),
 160                                                   rsize);
 161                                 rmap |= (1 << ((dimm << 1) + 1));
 162                                 nrank++;
 163                         case 0:
 164                                 pci_write_config8(PCI_DEV(0, 0, 4), (SCRATCH_RANK_0 + (dimm << 1)),
 165                                                   rsize);
 166                                 rmap |= (1 << (dimm << 1));
 167                                 nrank++;
 168                         }
 169                 }
 170         }
 171         pci_write_config8(PCI_DEV(0, 0, 4), SCRATCH_DIMM_NUM, ndimm);
 172         pci_write_config8(PCI_DEV(0, 0, 4), SCRATCH_RANK_NUM, nrank);
 173         pci_write_config8(PCI_DEV(0, 0, 4), SCRATCH_RANK_MAP, rmap);
 174 }
 175
 176 static void sdram_set_safe_values(const struct mem_controller *ctrl)
 177 {
 178         /* The purpose of this function is to set initial values for the dram
 179          * size and timings. It will be replaced with the SPD based function
 180          * once the RAM commands are working with these values.
 181          */
 182         u8 regs, val, t, dimm;
 183         u32 spds, tmp;
 184
 185         regs = pci_read_config8(MEMCTRL, 0x6c);
 186         if (regs & (1 << 6))
 187                 printk(BIOS_DEBUG, "DDR2 Detected.\n");
 188         else
 189                 die("ERROR: DDR1 memory detected but not supported by coreboot.\n");
 190
 191         /* Enable DDR2 */
 192         regs |= (1 << 7);
 193         pci_write_config8(MEMCTRL, 0x6c, regs);
 194
 195         /* SPD 5 # of ranks */
 196         pci_write_config8(MEMCTRL, 0x6d, 0xc0);
 197
 198         /**********************************************/
 199         /*          Set DRAM Freq (DDR2 533)          */
 200         /**********************************************/
 201         /* SPD 9 SDRAM Cycle Time */
 202         GET_SPD(dimm, spds, regs, 9);
 203
 204         printk(BIOS_DEBUG, "\nDDRII ");
 205         if (spds <= 0x3d) {
 206                 printk(BIOS_DEBUG, "533");
 207                 val = DDRII_533;
 208                 t = 38;
 209         } else if (spds <= 0x50) {
 210                 printk(BIOS_DEBUG, "400");
 211                 val = DDRII_400;
 212                 t = 50;
 213         } else if (spds <= 0x60) {
 214                 printk(BIOS_DEBUG, "333");
 215                 val = DDRII_333;
 216                 t = 60;
 217         } else if (spds <= 0x75) {
 218                 printk(BIOS_DEBUG, "266");
 219                 val = DDRII_266;
 220                 t = 75;
 221         } else {
 222                 printk(BIOS_DEBUG, "200");
 223                 val = DDRII_200;
 224                 t = 100;
 225         }
 226         /* To store DDRII frequence */
 227         pci_write_config8(PCI_DEV(0, 0, 4), SCRATCH_DRAM_FREQ, val);
 228
 229         /* Manual reset and adjust DLL when DRAM change frequency
 230          * This is a necessary sequence.
 231          */
 232         udelay(2000);
 233         regs = pci_read_config8(MEMCTRL, 0x90);
 234         regs |= 0x7;
 235         pci_write_config8(MEMCTRL, 0x90, regs);
 236         udelay(2000);
 237         regs = pci_read_config8(MEMCTRL, 0x90);
 238         regs &= ~0x7;
 239         regs |= val;
 240         pci_write_config8(MEMCTRL, 0x90, regs);
 241         udelay(2000);
 242         regs = pci_read_config8(MEMCTRL, 0x6b);
 243         regs |= 0xc0;
 244         regs &= ~0x10;
 245         pci_write_config8(MEMCTRL, 0x6b, regs);
 246         udelay(1);
 247         regs |= 0x10;
 248         pci_write_config8(MEMCTRL, 0x6b, regs);
 249         udelay(1);
 250         regs &= ~0xc0;
 251         pci_write_config8(MEMCTRL, 0x6b, regs);
 252         regs = pci_read_config8(MEMCTRL, 0x6f);
 253         regs |= 0x1;
 254         pci_write_config8(MEMCTRL, 0x6f, regs);
 255
 256         /**********************************************/
 257         /*      Set DRAM Timing Setting (DDR2 533)    */
 258         /**********************************************/
 259         /* SPD 9 18 23 25 CAS Latency NB3DRAM_REG62[2:0] */
 260         /* Read SPD byte 18 CAS Latency */
 261         GET_SPD(dimm, spds, regs, SPD_CAS_LAT);
 262         printk(BIOS_DEBUG, "\nCAS Supported ");
 263         if (spds & SPD_CAS_LAT_2)
 264                 printk(BIOS_DEBUG, "2 ");
 265         if (spds & SPD_CAS_LAT_3)
 266                 printk(BIOS_DEBUG, "3 ");
 267         if (spds & SPD_CAS_LAT_4)
 268                 printk(BIOS_DEBUG, "4 ");
 269         if (spds & SPD_CAS_LAT_5)
 270                 printk(BIOS_DEBUG, "5 ");
 271         if (spds & SPD_CAS_LAT_6)
 272                 printk(BIOS_DEBUG, "6");
 273
 274         /* We don't consider CAS = 6, because CX700 doesn't support it */
 275         printk(BIOS_DEBUG, "\n CAS:");
 276         if (spds & SPD_CAS_LAT_5) {
 277                 printk(BIOS_DEBUG, "Starting at CL5");
 278                 val = 0x3;
 279                 /* See whether we can improve it */
 280                 GET_SPD(dimm, tmp, regs, SPD_CAS_LAT_MIN_X_1);
 281                 if ((spds & SPD_CAS_LAT_4) && (tmp < 0x50)) {
 282                         printk(BIOS_DEBUG, "\n... going to CL4");
 283                         val = 0x2;
 284                 }
 285                 GET_SPD(dimm, tmp, regs, SPD_CAS_LAT_MIN_X_2);
 286                 if ((spds & SPD_CAS_LAT_3) && (tmp < 0x50)) {
 287                         printk(BIOS_DEBUG, "\n... going to CL3");
 288                         val = 0x1;
 289                 }
 290         } else {
 291                 printk(BIOS_DEBUG, "Starting at CL4");
 292                 val = 0x2;
 293                 GET_SPD(dimm, tmp, regs, SPD_CAS_LAT_MIN_X_1);
 294                 if ((spds & SPD_CAS_LAT_3) && (tmp < 0x50)) {
 295                         printk(BIOS_DEBUG, "\n... going to CL3");
 296                         val = 0x1;
 297                 }
 298                 GET_SPD(dimm, tmp, regs, SPD_CAS_LAT_MIN_X_2);
 299                 if ((spds & SPD_CAS_LAT_2) && (tmp < 0x50)) {
 300                         printk(BIOS_DEBUG, "\n... going to CL2");
 301                         val = 0x0;
 302                 }
 303         }
 304         regs = pci_read_config8(MEMCTRL, 0x62);
 305         regs &= ~0x7;
 306         regs |= val;
 307         pci_write_config8(MEMCTRL, 0x62, regs);
 308
 309         /* SPD 27 Trp NB3DRAM_REG64[3:2] */
 310         GET_SPD(dimm, spds, regs, SPD_TRP);
 311         printk(BIOS_DEBUG, "\nTrp %d", spds);
 312         spds >>= 2;
 313         for (val = 2; val <= 5; val++) {
 314                 if (spds <= (val * t / 10)) {
 315                         val = val - 2;
 316                         break;
 317                 }
 318         }
 319         val <<= 2;
 320         regs = pci_read_config8(MEMCTRL, 0x64);
 321         regs &= ~0xc;
 322         regs |= val;
 323         pci_write_config8(MEMCTRL, 0x64, regs);
 324
 325         /* SPD 29 Trcd NB3DRAM_REG64[7:6] */
 326         GET_SPD(dimm, spds, regs, SPD_TRCD);
 327         printk(BIOS_DEBUG, "\nTrcd %d", spds);
 328         spds >>= 2;
 329         for (val = 2; val <= 5; val++) {
 330                 if (spds <= (val * t / 10)) {
 331                         val = val - 2;
 332                         break;
 333                 }
 334         }
 335         val <<= 6;
 336         regs = pci_read_config8(MEMCTRL, 0x64);
 337         regs &= ~0xc0;
 338         regs |= val;
 339         pci_write_config8(MEMCTRL, 0x64, regs);
 340
 341         /* SPD 30 Tras NB3DRAM_REG62[7:4] */
 342         GET_SPD(dimm, spds, regs, SPD_TRAS);
 343         printk(BIOS_DEBUG, "\nTras %d", spds);
 344         for (val = 5; val <= 20; val++) {
 345                 if (spds <= (val * t / 10)) {
 346                         val = val - 5;
 347                         break;
 348                 }
 349         }
 350         val <<= 4;
 351         regs = pci_read_config8(MEMCTRL, 0x62);
 352         regs &= ~0xf0;
 353         regs |= val;
 354         pci_write_config8(MEMCTRL, 0x62, regs);
 355
 356         /* SPD 42 SPD 40 Trfc NB3DRAM_REG61[5:0] */
 357         GET_SPD(dimm, spds, regs, SPD_TRFC);
 358         printk(BIOS_DEBUG, "\nTrfc %d", spds);
 359         tmp = spds;
 360         GET_SPD(dimm, spds, regs, SPD_EX_TRC_TRFC);
 361         if (spds & 0x1)
 362                 tmp += 256;
 363         if (spds & 0xe)
 364                 tmp++;
 365         for (val = 8; val <= 71; val++) {
 366                 if (tmp <= (val * t / 10)) {
 367                         val = val - 8;
 368                         break;
 369                 }
 370         }
 371         regs = pci_read_config8(MEMCTRL, 0x61);
 372         regs &= ~0x3f;
 373         regs |= val;
 374         pci_write_config8(MEMCTRL, 0x61, regs);
 375
 376         /* SPD 28 Trrd NB3DRAM_REG63[7:6] */
 377         GET_SPD(dimm, spds, regs, SPD_TRRD);
 378         for (val = 2; val <= 5; val++) {
 379                 if (spds <= (val * t / 10)) {
 380                         val = val - 2;
 381                         break;
 382                 }
 383         }
 384         val <<= 6;
 385         printk(BIOS_DEBUG, "\nTrrd val = 0x%x", val);
 386         regs = pci_read_config8(MEMCTRL, 0x63);
 387         regs &= ~0xc0;
 388         regs |= val;
 389         pci_write_config8(MEMCTRL, 0x63, regs);
 390
 391         /* SPD 36 Twr NB3DRAM_REG61[7:6] */
 392         GET_SPD(dimm, spds, regs, SPD_TWR);
 393         for (val = 2; val <= 5; val++) {
 394                 if (spds <= (val * t / 10)) {
 395                         val = val - 2;
 396                         break;
 397                 }
 398         }
 399         val <<= 6;
 400         printk(BIOS_DEBUG, "\nTwr val = 0x%x", val);
 401
 402         regs = pci_read_config8(MEMCTRL, 0x61);
 403         regs &= ~0xc0;
 404         regs |= val;
 405         pci_write_config8(MEMCTRL, 0x61, regs);
 406
 407         /* SPD 37 Twtr NB3DRAM_REG63[1] */
 408         GET_SPD(dimm, spds, regs, SPD_TWTR);
 409         spds >>= 2;
 410         printk(BIOS_DEBUG, "\nTwtr 0x%x", spds);
 411         if (spds <= (t * 2 / 10))
 412                 val = 0;
 413         else
 414                 val = 1;
 415         val <<= 1;
 416         printk(BIOS_DEBUG, "\nTwtr val = 0x%x", val);
 417
 418         regs = pci_read_config8(MEMCTRL, 0x63);
 419         regs &= ~0x2;
 420         regs |= val;
 421         pci_write_config8(MEMCTRL, 0x63, regs);
 422
 423         /* SPD 38 Trtp NB3DRAM_REG63[3] */
 424         GET_SPD(dimm, spds, regs, SPD_TRTP);
 425         spds >>= 2;
 426         printk(BIOS_DEBUG, "\nTrtp 0x%x", spds);
 427         if (spds <= (t * 2 / 10))
 428                 val = 0;
 429         else
 430                 val = 1;
 431         val <<= 3;
 432         printk(BIOS_DEBUG, "\nTrtp val = 0x%x", val);
 433
 434         regs = pci_read_config8(MEMCTRL, 0x63);
 435         regs &= ~0x8;
 436         regs |= val;
 437         pci_write_config8(MEMCTRL, 0x63, regs);
 438
 439         /**********************************************/
 440         /*           Set DRAM DRDY Setting            */
 441         /**********************************************/
 442         /* Write slowest value to register */
 443         tmp = sizeof(Host_Reg_Val) / sizeof(Host_Reg_Val[0]);
 444         for (val = 0; val < tmp; val += 2)
 445                 pci_write_config8(HOSTCTRL, Host_Reg_Val[val], Host_Reg_Val[val + 1]);
 446
 447         /* F2_RX51[7]=0, disable DRDY timing */
 448         regs = pci_read_config8(HOSTCTRL, 0x51);
 449         regs &= ~0x80;
 450         pci_write_config8(HOSTCTRL, 0x51, regs);
 451
 452         /**********************************************/
 453         /*           Set DRAM BurstLength             */
 454         /**********************************************/
 455         regs = pci_read_config8(MEMCTRL, 0x6c);
 456         for (dimm = 0; dimm < DIMM_SOCKETS; dimm++) {
 457                 if (pci_read_config8(PCI_DEV(0, 0, 4), (SCRATCH_REG_BASE + (dimm << 1)))) {
 458                         spds = get_spd_data(ctrl, dimm, 16);
 459                         if (!(spds & 0x8))
 460                                 break;
 461                 }
 462         }
 463         if (dimm == 2)
 464                 regs |= 0x8;
 465         pci_write_config8(MEMCTRL, 0x6c, regs);
 466         val = pci_read_config8(HOSTCTRL, 0x54);
 467         val &= ~0x10;
 468         if (dimm == 2)
 469                 val |= 0x10;
 470         pci_write_config8(HOSTCTRL, 0x54, val);
 471
 472         /**********************************************/
 473         /*          Set DRAM Driving Setting          */
 474         /**********************************************/
 475         /* DRAM Timing ODT */
 476         tmp = sizeof(Dram_Driving_ODT_CTRL) / sizeof(Dram_Driving_ODT_CTRL[0]);
 477         for (val = 0; val < tmp; val += 2)
 478                 pci_write_config8(MEMCTRL, Dram_Driving_ODT_CTRL[val],
 479                                   Dram_Driving_ODT_CTRL[val + 1]);
 480
 481         regs = pci_read_config8(PCI_DEV(0, 0, 4), SCRATCH_RANK_NUM);
 482         val = pci_read_config8(MEMCTRL, 0xd5);
 483         val &= ~0xaa;
 484         switch (regs) {
 485         case 3:
 486         case 2:
 487                 val |= 0xa0;
 488                 break;
 489         default:
 490                 val |= 0x80;
 491         }
 492         regs = pci_read_config8(PCI_DEV(0, 0, 4), SCRATCH_DIMM_NUM);
 493         if (regs == 1)
 494                 val |= 0xa;
 495         pci_write_config8(MEMCTRL, 0xd5, val);
 496
 497         regs = pci_read_config8(PCI_DEV(0, 0, 4), SCRATCH_DIMM_NUM);
 498         val = pci_read_config8(MEMCTRL, 0xd6);
 499         val &= ~0x2;
 500         if (regs == 1)
 501                 val |= 0x2;
 502         pci_write_config8(MEMCTRL, 0xd6, val);
 503
 504         regs = pci_read_config8(PCI_DEV(0, 0, 4), SCRATCH_RANK_MAP);
 505         tmp = sizeof(ODT_TBL) / sizeof(ODT_TBL[0]);
 506         for (val = 0; val < tmp; val += 3) {
 507                 if (regs == ODT_TBL[val]) {
 508                         pci_write_config8(MEMCTRL, 0xd8, ODT_TBL[val + 1]);
 509                         /* Store DRAM & NB ODT setting in d0f4_Rxd8 */
 510                         pci_write_config8(PCI_DEV(0, 0, 4), SCRATCH_DRAM_NB_ODT, ODT_TBL[val + 2]);
 511                         break;
 512                 }
 513         }
 514
 515         pci_write_config8(MEMCTRL, 0xd9, 0x0a);
 516         regs = pci_read_config8(PCI_DEV(0, 0, 4), SCRATCH_RANK_NUM);
 517         regs--;
 518         regs = regs << 1;
 519         pci_write_config8(MEMCTRL, 0xe0, DQS_DQ_TBL[regs++]);
 520         pci_write_config8(MEMCTRL, 0xe2, DQS_DQ_TBL[regs]);
 521
 522         /* DRAM Timing CS */
 523         pci_write_config8(MEMCTRL, 0xe4, 0x66);
 524
 525         /* DRAM Timing MAA */
 526         val = 0;
 527         for (dimm = 0; dimm < DIMM_SOCKETS; dimm++) {
 528                 if (pci_read_config8(PCI_DEV(0, 0, 4), (SCRATCH_REG_BASE + (dimm << 1)))) {
 529                         spds = get_spd_data(ctrl, dimm, SPD_PRI_WIDTH);
 530                         spds = 64 / spds;
 531                         if (pci_read_config8
 532                             (PCI_DEV(0, 0, 4), (SCRATCH_REG_BASE + (dimm << 1) + 1)))
 533                                 spds = spds << 1;
 534                         val += spds;
 535                 }
 536         }
 537         printk(BIOS_DEBUG, "\nchip #%d", val);
 538         if (val > 18)
 539                 regs = 0xdb;
 540         else
 541                 regs = 0x86;
 542         pci_write_config8(MEMCTRL, 0xe8, regs);
 543
 544         /* DRAM Timing MAB */
 545         pci_write_config8(MEMCTRL, 0xe9, 0x0);
 546
 547         /* DRAM Timing DCLK VT8454C always 0x66 */
 548         pci_write_config8(MEMCTRL, 0xe6, 0xaa);
 549
 550         /**********************************************/
 551         /*            Set DRAM Duty Control           */
 552         /**********************************************/
 553         regs = pci_read_config8(PCI_DEV(0, 0, 4), SCRATCH_RANK_NUM);
 554         switch (regs) {
 555         case 1:
 556         case 2:         /* 1~2 rank */
 557                 val = 0;
 558                 break;
 559         case 3:
 560         case 4:         /* 3~4 rank */
 561                 regs = pci_read_config8(PCI_DEV(0, 0, 4), SCRATCH_DRAM_FREQ);
 562                 if (regs == DDRII_533)
 563                         val = 4;
 564                 else            /* DDRII-400 */
 565                         val = 0;
 566                 break;
 567         }
 568         regs = 0xec;
 569         for (t = 0; t < 4; t++) {
 570                 pci_write_config8(MEMCTRL, regs, Duty_Control_DDR2[val]);
 571                 regs++;
 572                 val++;
 573         }
 574
 575         /**********************************************/
 576         /*            Set DRAM Clock Control          */
 577         /**********************************************/
 578         /* Write Data Phase */
 579         val = pci_read_config8(PCI_DEV(0, 0, 4), SCRATCH_DRAM_FREQ);
 580         regs = pci_read_config8(MEMCTRL, 0x75);
 581         regs &= 0xf0;
 582         switch (val) {
 583         case DDRII_533:
 584                 pci_write_config8(MEMCTRL, 0x74, 0x07);
 585                 regs |= 0x7;
 586                 break;
 587         case DDRII_400:
 588         default:
 589                 pci_write_config8(MEMCTRL, 0x74, 0x05);
 590                 regs |= 0x5;
 591                 break;
 592         }
 593         pci_write_config8(MEMCTRL, 0x75, regs);
 594         pci_write_config8(MEMCTRL, 0x76, 0x80);
 595
 596         /* Clock Phase Control for FeedBack Mode */
 597         regs = pci_read_config8(MEMCTRL, 0x90);
 598 //      regs |= 0x80;
 599         pci_write_config8(MEMCTRL, 0x90, regs);
 600
 601         regs = pci_read_config8(PCI_DEV(0, 0, 4), SCRATCH_DRAM_FREQ);
 602         switch (regs) {
 603         case DDRII_533:
 604                 regs = pci_read_config8(PCI_DEV(0, 0, 4), SCRATCH_RANK_NUM);
 605                 if (regs == 1)
 606                         val = 0;
 607                 else
 608                         val = 3;
 609                 break;
 610         case DDRII_400:
 611         default:
 612                 val = 6;
 613                 break;
 614         }
 615         regs = pci_read_config8(MEMCTRL, 0x91);
 616         regs &= ~0xc0;
 617         regs |= 0x80;
 618         pci_write_config8(MEMCTRL, 0x91, regs);
 619         regs = 0x91;
 620         for (t = 0; t < 3; t++) {
 621                 dimm = pci_read_config8(MEMCTRL, regs);
 622                 dimm &= ~0x7;
 623                 dimm |= ChA_Clk_Phase_DDR2_Table[val];
 624                 pci_write_config8(MEMCTRL, regs, dimm);
 625                 regs++;
 626                 val++;
 627         }
 628
 629         pci_write_config8(MEMCTRL, 0x97, 0x12);
 630         pci_write_config8(MEMCTRL, 0x98, 0x33);
 631
 632         regs = pci_read_config8(PCI_DEV(0, 0, 4), SCRATCH_RANK_0);
 633         val = pci_read_config8(PCI_DEV(0, 0, 4), SCRATCH_RANK_2);
 634         if (regs && val)
 635                 pci_write_config8(MEMCTRL, 0x9d, 0x00);
 636         else
 637                 pci_write_config8(MEMCTRL, 0x9d, 0x0f);
 638
 639         tmp = sizeof(DQ_DQS_Table) / sizeof(DQ_DQS_Table[0]);
 640         for (val = 0; val < tmp; val += 2)
 641                 pci_write_config8(MEMCTRL, DQ_DQS_Table[val], DQ_DQS_Table[val + 1]);
 642         regs = pci_read_config8(PCI_DEV(0, 0, 4), SCRATCH_DRAM_FREQ);
 643         if (regs == DDRII_533)
 644                 pci_write_config8(MEMCTRL, 0x7b, 0xa0);
 645         else
 646                 pci_write_config8(MEMCTRL, 0x7b, 0x10);
 647
 648         /***************************************************/
 649         /*  Set necessary register before DRAM initialize  */
 650         /***************************************************/
 651         tmp = sizeof(Mem_Reg_Init) / sizeof(Mem_Reg_Init[0]);
 652         for (val = 0; val < tmp; val += 3) {
 653                 regs = pci_read_config8(MEMCTRL, Mem_Reg_Init[val]);
 654                 regs &= Mem_Reg_Init[val + 1];
 655                 regs |= Mem_Reg_Init[val + 2];
 656                 pci_write_config8(MEMCTRL, Mem_Reg_Init[val], regs);
 657         }
 658         regs = pci_read_config8(HOSTCTRL, 0x51);
 659         regs &= 0xbf;           // Clear bit 6 Disable Read Around Write
 660         pci_write_config8(HOSTCTRL, 0x51, regs);
 661
 662         regs = pci_read_config8(HOSTCTRL, 0x54);
 663         t = regs >> 5;
 664         val = pci_read_config8(HOSTCTRL, 0x57);
 665         dimm = val >> 5;
 666         if (t == dimm)
 667                 t = 0x0;
 668         else
 669                 t = 0x1;
 670         regs &= ~0x1;
 671         regs |= t;
 672         val &= ~0x1;
 673         val |= t;
 674         pci_write_config8(HOSTCTRL, 0x57, val);
 675
 676         regs = pci_read_config8(HOSTCTRL, 0x51);
 677         regs |= t;
 678         pci_write_config8(HOSTCTRL, 0x51, regs);
 679
 680         regs = pci_read_config8(MEMCTRL, 0x90);
 681         regs &= 0x7;
 682         val = 0;
 683         if (regs < 0x2)
 684                 val = 0x80;
 685         regs = pci_read_config8(MEMCTRL, 0x76);
 686         regs &= 0x80;
 687         regs |= val;
 688         pci_write_config8(MEMCTRL, 0x76, regs);
 689
 690         regs = pci_read_config8(MEMCTRL, 0x6f);
 691         regs |= 0x10;
 692         pci_write_config8(MEMCTRL, 0x6f, regs);
 693
 694         /***************************************************/
 695         /*    Find suitable DQS value for ChA and ChB      */
 696         /***************************************************/
 697         // Set DQS output delay for Channel A
 698         regs = pci_read_config8(PCI_DEV(0, 0, 4), SCRATCH_DRAM_FREQ);
 699         val = pci_read_config8(PCI_DEV(0, 0, 4), SCRATCH_RANK_NUM);
 700         switch (regs) {
 701         case DDRII_533:
 702                 if (val < 2)
 703                         val = 0;
 704                 else
 705                         val = 2;
 706                 break;
 707         case DDRII_400:
 708         default:
 709                 if (val < 2)
 710                         val = 4;
 711                 else
 712                         val = 6;
 713                 break;
 714         }
 715         for (t = 0; t < 2; t++)
 716                 pci_write_config8(MEMCTRL, (0x70 + t), DQSOChA_DDR2_Driving_Table[val + t]);
 717         // Set DQS output delay for Channel B
 718         pci_write_config8(MEMCTRL, 0x72, 0x0);
 719
 720         regs = pci_read_config8(PCI_DEV(0, 0, 4), SCRATCH_RANK_0);
 721         val = pci_read_config8(PCI_DEV(0, 0, 4), SCRATCH_RANK_2);
 722         if (regs && val)
 723                 pci_write_config8(MEMCTRL, 0x73, 0xfd);
 724         else
 725                 pci_write_config8(MEMCTRL, 0x73, 0x01);
 726 }
 727
 728 static void sdram_set_registers(const struct mem_controller *ctrl)
 729 {
 730         c7_cpu_setup(ctrl);
 731         ddr_detect(ctrl);
 732         sdram_set_safe_values(ctrl);
 733 }
 734
 735 static void step_20_21(const struct mem_controller *ctrl)
 736 {
 737         u8 val;
 738
 739         // Step 20
 740         udelay(200);
 741
 742         val = pci_read_config8(PCI_DEV(0, 0, 4), SCRATCH_DRAM_NB_ODT);
 743         if (val & DDR2_ODT_150ohm)
 744                 read32(0x102200);
 745         else
 746                 read32(0x102020);
 747
 748         /* Step 21. Normal operation */
 749         print_spew("RAM Enable 5: Normal operation\n");
 750         do_ram_command(ctrl, RAM_COMMAND_NORMAL);
 751         udelay(3);
 752 }
 753
 754 static void step_2_19(const struct mem_controller *ctrl)
 755 {
 756         u32 i;
 757         u8 val;
 758
 759         //  Step 2
 760         val = pci_read_config8(MEMCTRL, 0x69);
 761         val &= ~0x03;
 762         pci_write_config8(MEMCTRL, 0x69, val);
 763
 764         /* Step 3 Apply NOP. */
 765         print_spew("RAM Enable 1: Apply NOP\n");
 766         do_ram_command(ctrl, RAM_COMMAND_NOP);
 767
 768         udelay(15);
 769
 770         // Step 4
 771         print_spew("SEND: ");
 772         read32(0);
 773         print_spew("OK\n");
 774
 775         // Step 5
 776         udelay(400);
 777
 778         /* 6. Precharge all. Wait tRP. */
 779         print_spew("RAM Enable 2: Precharge all\n");
 780         do_ram_command(ctrl, RAM_COMMAND_PRECHARGE);
 781
 782         // Step 7
 783         print_spew("SEND: ");
 784         read32(0);
 785         print_spew("OK\n");
 786
 787         /* Step 8. Mode register set. */
 788         print_spew("RAM Enable 4: Mode register set\n");
 789         do_ram_command(ctrl, RAM_COMMAND_MRS);  //enable dll
 790
 791         // Step 9
 792         print_spew("SEND: ");
 793
 794         val = pci_read_config8(PCI_DEV(0, 0, 4), SCRATCH_DRAM_NB_ODT);
 795         if (val & DDR2_ODT_150ohm)
 796                 read32(0x102200);       //DDR2_ODT_150ohm
 797         else
 798                 read32(0x102020);
 799         print_spew("OK\n");
 800
 801         // Step 10
 802         print_spew("SEND: ");
 803         read32(0x800);
 804         print_spew("OK\n");
 805
 806         /* Step 11. Precharge all. Wait tRP. */
 807         print_spew("RAM Enable 2: Precharge all\n");
 808         do_ram_command(ctrl, RAM_COMMAND_PRECHARGE);
 809
 810         // Step 12
 811         print_spew("SEND: ");
 812         read32(0x0);
 813         print_spew("OK\n");
 814
 815         /* Step 13. Perform 8 refresh cycles. Wait tRC each time. */
 816         print_spew("RAM Enable 3: CBR\n");
 817         do_ram_command(ctrl, RAM_COMMAND_CBR);
 818
 819         /* JEDEC says only twice, do 8 times for posterity */
 820         // Step 16: Repeat Step 14 and 15 another 7 times
 821         for (i = 0; i < 8; i++) {
 822                 // Step 14
 823                 read32(0);
 824                 print_spew(".");
 825
 826                 // Step 15
 827                 udelay(100);
 828         }
 829
 830         /* Step 17. Mode register set. Wait 200us. */
 831         print_spew("\nRAM Enable 4: Mode register set\n");
 832
 833         //safe value for now, BL=8, WR=4, CAS=4
 834         do_ram_command(ctrl, RAM_COMMAND_MRS);
 835         udelay(200);
 836
 837         /* Use Single Chanel temporarily */
 838         val = pci_read_config8(MEMCTRL, 0x6c);
 839         if (val & 0x8) {        /* Burst Length = 8 */
 840                 val = pci_read_config8(MEMCTRL, 0x62);
 841                 val &= 0x7;
 842                 i = DDR2_MRS_table[4 + val];
 843         } else {
 844                 val = pci_read_config8(MEMCTRL, 0x62);
 845                 val &= 0x7;
 846                 i = DDR2_MRS_table[val];
 847         }
 848
 849         // Step 18
 850         val = pci_read_config8(MEMCTRL, 0x61);
 851         val = val >> 6;
 852         i |= DDR2_Twr_table[val];
 853         read32(i);
 854
 855         printk(BIOS_DEBUG, "MRS = %08x\n", i);
 856
 857         udelay(15);
 858
 859         // Step 19
 860         val = pci_read_config8(PCI_DEV(0, 0, 4), SCRATCH_DRAM_NB_ODT);
 861         if (val & DDR2_ODT_150ohm)
 862                 read32(0x103e00);       //EMRS OCD Default
 863         else
 864                 read32(0x103c20);
 865 }
 866
 867 static void sdram_set_vr(const struct mem_controller *ctrl, u8 num)
 868 {
 869         u8 reg, val;
 870         val = 0x54 + (num >> 1);
 871         reg = pci_read_config8(MEMCTRL, val);
 872         reg &= (0xf << (4 * (num & 0x1)));
 873         reg |= (((0x8 | num) << 4) >> (4 * (num & 0x1)));
 874         pci_write_config8(MEMCTRL, val, reg);
 875 }
 876 static void sdram_ending_addr(const struct mem_controller *ctrl, u8 num)
 877 {
 878         u8 reg, val;
 879         /* Set Ending Address */
 880         val = 0x40 + num;
 881         reg = pci_read_config8(MEMCTRL, val);
 882         reg += 0x10;
 883         pci_write_config8(MEMCTRL, val, reg);
 884         /* Set Beginning Address */
 885         val = 0x48 + num;
 886         pci_write_config8(MEMCTRL, val, 0x0);
 887 }
 888
 889 static void sdram_clear_vr_addr(const struct mem_controller *ctrl, u8 num)
 890 {
 891         u8 reg, val;
 892         val = 0x54 + (num >> 1);
 893         reg = pci_read_config8(MEMCTRL, val);
 894         reg = ~(0x80 >> (4 * (num & 0x1)));
 895         pci_write_config8(MEMCTRL, val, reg);
 896         val = 0x40 + num;
 897         reg = pci_read_config8(MEMCTRL, val);
 898         reg -= 0x10;
 899         pci_write_config8(MEMCTRL, val, reg);
 900         val = 0x48 + num;
 901         pci_write_config8(MEMCTRL, val, 0x0);
 902 }
 903
 904 /* Perform sizing DRAM by dynamic method */
 905 static void sdram_calc_size(const struct mem_controller *ctrl, u8 num)
 906 {
 907         u8 ca, ra, ba, reg;
 908         ba = pci_read_config8(PCI_DEV(0, 0, 4), SCRATCH_FLAGS);
 909         if (ba == 8) {
 910                 write8(0, 0x0d);
 911                 ra = read8(0);
 912                 write8((1 << SDRAM1X_RA_12_8bk), 0x0c);
 913                 ra = read8(0);
 914
 915                 write8(0, 0x0a);
 916                 ca = read8(0);
 917                 write8((1 << SDRAM1X_CA_09_8bk), 0x0c);
 918                 ca = read8(0);
 919
 920                 write8(0, 0x03);
 921                 ba = read8(0);
 922                 write8((1 << SDRAM1X_BA2_8bk), 0x02);
 923                 ba = read8(0);
 924                 write8((1 << SDRAM1X_BA1_8bk), 0x01);
 925                 ba = read8(0);
 926         } else {
 927                 write8(0, 0x0f);
 928                 ra = read8(0);
 929                 write8((1 << SDRAM1X_RA_14), 0x0e);
 930                 ra = read8(0);
 931                 write8((1 << SDRAM1X_RA_13), 0x0d);
 932                 ra = read8(0);
 933                 write8((1 << SDRAM1X_RA_12), 0x0c);
 934                 ra = read8(0);
 935
 936                 write8(0, 0x0c);
 937                 ca = read8(0);
 938                 write8((1 << SDRAM1X_CA_12), 0x0b);
 939                 ca = read8(0);
 940                 write8((1 << SDRAM1X_CA_11), 0x0a);
 941                 ca = read8(0);
 942                 write8((1 << SDRAM1X_CA_09), 0x09);
 943                 ca = read8(0);
 944
 945                 write8(0, 0x02);
 946                 ba = read8(0);
 947                 write8((1 << SDRAM1X_BA1), 0x01);
 948                 ba = read8(0);
 949         }
 950
 951         if (ra < 10 || ra > 15)
 952                 die("bad RA");
 953         if (ca < 8 || ca > 12)
 954                 die("bad CA");
 955         if (ba < 1 || ba > 3)
 956                 die("bad BA");
 957
 958         /* Calculate MA type save to scratch register */
 959         reg = 0;
 960
 961         switch (ra) {
 962         case 12:
 963                 reg |= MA_12_Row;
 964                 break;
 965         case 13:
 966                 reg |= MA_13_Row;
 967                 break;
 968         case 14:
 969                 reg |= MA_14_Row;
 970                 break;
 971         default:
 972                 reg |= MA_15_Row;
 973         }
 974
 975         switch (ca) {
 976         case 9:
 977                 reg |= MA_9_Column;
 978                 break;
 979         case 10:
 980                 reg |= MA_10_Column;
 981                 break;
 982         case 11:
 983                 reg |= MA_11_Column;
 984                 break;
 985         default:
 986                 reg |= MA_12_Column;
 987         }
 988
 989         switch (ba) {
 990         case 3:
 991                 reg |= MA_8_Bank;
 992                 break;
 993         default:
 994                 reg |= MA_4_Bank;
 995         }
 996
 997         pci_write_config8(PCI_DEV(0, 0, 4), (SCRATCH_RANK0_MA_REG + num), reg);
 998
 999         if (ra >= 13)
1000                 pci_write_config8(PCI_DEV(0, 0, 4), SCRATCH_DRAM_256M_BIT, 1);
1001
1002         /* Calculate rank size save to scratch register */
1003         ra = ra + ca + ba + 3 - 26;     /* 1 unit = 64M */
1004         ra = 1 << ra;
1005         pci_write_config8(PCI_DEV(0, 0, 4), (SCRATCH_RANK0_SIZE_REG + num), ra);
1006 }
1007
1008 static void sdram_enable(const struct mem_controller *ctrl)
1009 {
1010         u8 reg8;
1011         u8 val, i;
1012         device_t dev;
1013         u8 dl, dh;
1014         u32 quot;
1015
1016         /* Init Present Bank */
1017         val = sizeof(Init_Rank_Reg_Table) / sizeof(Init_Rank_Reg_Table[0]);
1018         for (i = 0; i < val; i++)
1019                 pci_write_config8(MEMCTRL, Init_Rank_Reg_Table[i], 0x0);
1020
1021         /* Init other banks */
1022         for (i = 0; i < 4; i++) {
1023                 reg8 = pci_read_config8(PCI_DEV(0, 0, 4), (SCRATCH_RANK_0 + i));
1024                 if (reg8) {
1025                         sdram_set_vr(ctrl, i);
1026                         sdram_ending_addr(ctrl, i);
1027                         step_2_19(ctrl);
1028                         step_20_21(ctrl);
1029                         sdram_clear_vr_addr(ctrl, i);
1030                 }
1031         }
1032
1033 #ifdef MEM_WIDTH_32BIT_MODE
1034         /****************************************************************/
1035         /*                      Set Dram 32bit Mode                     */
1036         /****************************************************************/
1037         reg8 = pci_read_config8(MEMCTRL, 0x6c);
1038         reg8 |= 0x20;
1039         pci_write_config(MEMCTRL, 0x6c, reg8);
1040 #endif
1041
1042         /****************************************************************/
1043         /* Find the DQSI Low/High bound and save it to Scratch register */
1044         /****************************************************************/
1045         for (dl = 0; dl < 0x3f; dl += 2) {
1046                 reg8 = dl & 0x3f;
1047                 reg8 |= 0x80;   /* Set Manual Mode */
1048                 pci_write_config8(MEMCTRL, 0x77, reg8);
1049                 for (i = 0; i < 4; i++) {
1050                         reg8 = pci_read_config8(PCI_DEV(0, 0, 4), (SCRATCH_RANK_0 + i));
1051                         if (reg8) {
1052                                 sdram_set_vr(ctrl, i);
1053                                 sdram_ending_addr(ctrl, i);
1054                                 write32(0, 0x55555555);
1055                                 write32(4, 0x55555555);
1056                                 udelay(15);
1057                                 if (read32(0) != 0x55555555)
1058                                         break;
1059                                 if (read32(4) != 0x55555555)
1060                                         break;
1061                                 write32(0, 0xaaaaaaaa);
1062                                 write32(4, 0xaaaaaaaa);
1063                                 udelay(15);
1064                                 if (read32(0) != 0xaaaaaaaa)
1065                                         break;
1066                                 if (read32(4) != 0xaaaaaaaa)
1067                                         break;
1068                                 sdram_clear_vr_addr(ctrl, i);
1069                         }
1070                 }
1071                 if (i == 4)
1072                         break;
1073                 else
1074                         sdram_clear_vr_addr(ctrl, i);
1075         }
1076         printk(BIOS_DEBUG, "\nDQSI Low %08x", dl);
1077         for (dh = dl; dh < 0x3f; dh += 2) {
1078                 reg8 = dh & 0x3f;
1079                 reg8 |= 0x80;   /* Set Manual Mode */
1080                 pci_write_config8(MEMCTRL, 0x77, reg8);
1081                 for (i = 0; i < 4; i++) {
1082                         reg8 = pci_read_config8(PCI_DEV(0, 0, 4), (SCRATCH_RANK_0 + i));
1083                         if (reg8) {
1084                                 sdram_set_vr(ctrl, i);
1085                                 sdram_ending_addr(ctrl, i);
1086
1087                                 write32(0, 0x55555555);
1088                                 write32(4, 0x55555555);
1089                                 udelay(15);
1090                                 if (read32(0) != 0x55555555)
1091                                         break;
1092                                 if (read32(4) != 0x55555555)
1093                                         break;
1094                                 write32(0, 0xaaaaaaaa);
1095                                 write32(4, 0xaaaaaaaa);
1096                                 udelay(15);
1097                                 if (read32(0) != 0xaaaaaaaa)
1098                                         break;
1099                                 if (read32(4) != 0xaaaaaaaa)
1100                                         break;
1101                                 sdram_clear_vr_addr(ctrl, i);
1102                         }
1103                 }
1104                 if (i != 4) {
1105                         sdram_clear_vr_addr(ctrl, i);
1106                         break;
1107                 }
1108         }
1109         printk(BIOS_DEBUG, "\nDQSI High %02x", dh);
1110         pci_write_config8(PCI_DEV(0, 0, 4), SCRATCH_CHA_DQSI_LOW_REG, dl);
1111         pci_write_config8(PCI_DEV(0, 0, 4), SCRATCH_CHA_DQSI_HIGH_REG, dh);
1112         reg8 = pci_read_config8(MEMCTRL, 0X90) & 0X7;
1113         val = DQSI_Rate_Table[reg8];
1114         quot = dh - dl;
1115         quot = quot * val;
1116         quot >>= 4;
1117         val = quot + dl;
1118         pci_write_config8(PCI_DEV(0, 0, 4), SCRATCH_ChA_DQSI_REG, val);
1119         reg8 = val & 0x3f;
1120         reg8 |= 0x80;
1121         pci_write_config8(MEMCTRL, 0x77, reg8);
1122
1123         /****************************************************************/
1124         /*     Find out the lowest Bank Interleave and Set Register     */
1125         /****************************************************************/
1126 #if 0
1127         //TODO
1128         reg8 = pci_read_config8(MEMCTRL, 0x69);
1129         reg8 &= ~0xc0;
1130         reg8 |= 0x80;           //8 banks
1131         pci_write_config8(MEMCTRL, 0x69, reg8);
1132 #endif
1133         dl = 2;
1134         for (i = 0; i < 4; i++) {
1135                 reg8 = pci_read_config8(PCI_DEV(0, 0, 4), (SCRATCH_RANK_0 + i));
1136                 if (reg8) {
1137                         reg8 = get_spd_data(ctrl, (i >> 1), 17);
1138                         sdram_set_vr(ctrl, i);
1139                         sdram_ending_addr(ctrl, i);
1140                         if (reg8 == 4) {
1141                                 write8(0, 0x02);
1142                                 val = read8(0);
1143                                 write8((1 << SDRAM1X_BA1), 0x01);
1144                                 val = read8(0);
1145                         } else {
1146                                 write8(0, 0x03);
1147                                 val = read8(0);
1148                                 write8((1 << SDRAM1X_BA2_8bk), 0x02);
1149                                 val = read8(0);
1150                                 write8((1 << SDRAM1X_BA1_8bk), 0x01);
1151                                 val = read8(0);
1152                         }
1153                         if (val < dl)
1154                                 dl = val;
1155                         sdram_clear_vr_addr(ctrl, i);
1156                 }
1157         }
1158         dl <<= 6;
1159         reg8 = pci_read_config8(MEMCTRL, 0x69);
1160         reg8 &= ~0xc0;
1161         reg8 |= dl;
1162         pci_write_config8(MEMCTRL, 0x69, reg8);
1163
1164         /****************************************************************/
1165         /*               DRAM Sizing and Fill MA type                   */
1166         /****************************************************************/
1167         for (i = 0; i < 4; i++) {
1168                 val = pci_read_config8(PCI_DEV(0, 0, 4), (SCRATCH_RANK_0 + i));
1169                 if (val) {
1170                         reg8 = get_spd_data(ctrl, (i >> 1), 17);
1171                         pci_write_config8(PCI_DEV(0, 0, 4), SCRATCH_FLAGS, reg8);
1172                         if (reg8 == 4) {
1173                                 /* Use MA Type 3 for DRAM sizing */
1174                                 reg8 = pci_read_config8(MEMCTRL, 0x50);
1175                                 reg8 &= 0x11;
1176                                 reg8 |= 0x66;
1177                                 pci_write_config8(MEMCTRL, 0x50, reg8);
1178                                 pci_write_config8(MEMCTRL, 0x51, reg8);
1179                         } else {
1180                                 /* Use MA Type 5 for DRAM sizing */
1181                                 reg8 = pci_read_config8(MEMCTRL, 0x50);
1182                                 reg8 &= 0x11;
1183                                 reg8 |= 0xaa;
1184                                 pci_write_config8(MEMCTRL, 0x50, reg8);
1185                                 pci_write_config8(MEMCTRL, 0x51, reg8);
1186                                 reg8 = pci_read_config8(MEMCTRL, 0x53);
1187                                 reg8 &= 0x0f;
1188                                 reg8 |= 0x90;
1189                                 pci_write_config8(MEMCTRL, 0x53, reg8);
1190                         }
1191                         sdram_set_vr(ctrl, i);
1192                         val = 0x40 + i;
1193                         reg8 = pci_read_config8(MEMCTRL, val);
1194                         /* max size 3G for new MA table */
1195                         reg8 += 0x30;
1196                         pci_write_config8(MEMCTRL, val, reg8);
1197                         /* Set Beginning Address */
1198                         val = 0x48 + i;
1199                         pci_write_config8(MEMCTRL, val, 0x0);
1200
1201                         sdram_calc_size(ctrl, i);
1202
1203                         /* Clear */
1204                         val = 0x54 + (i >> 1);
1205                         reg8 = pci_read_config8(MEMCTRL, val);
1206                         reg8 = ~(0x80 >> (4 * (i & 0x1)));
1207                         pci_write_config8(MEMCTRL, val, reg8);
1208                         val = 0x40 + i;
1209                         reg8 = pci_read_config8(MEMCTRL, val);
1210                         reg8 -= 0x30;
1211                         pci_write_config8(MEMCTRL, val, reg8);
1212                         val = 0x48 + i;
1213                         pci_write_config8(MEMCTRL, val, 0x0);
1214
1215                 }
1216         }
1217         /* Clear MA Type */
1218         reg8 = pci_read_config8(MEMCTRL, 0x50);
1219         reg8 &= 0x11;
1220         pci_write_config8(MEMCTRL, 0x50, reg8);
1221         pci_write_config8(MEMCTRL, 0x51, reg8);
1222         reg8 = pci_read_config8(MEMCTRL, 0x6b);
1223         reg8 &= ~0x08;
1224         pci_write_config8(MEMCTRL, 0x6b, reg8);
1225
1226         /****************************************************************/
1227         /*             DRAM re-initialize for burst length              */
1228         /****************************************************************/
1229         for (i = 0; i < 4; i++) {
1230                 reg8 = pci_read_config8(PCI_DEV(0, 0, 4), (SCRATCH_RANK_0 + i));
1231                 if (reg8) {
1232                         sdram_set_vr(ctrl, i);
1233                         sdram_ending_addr(ctrl, i);
1234                         step_2_19(ctrl);
1235                         step_20_21(ctrl);
1236                         sdram_clear_vr_addr(ctrl, i);
1237                 }
1238         }
1239
1240         /****************************************************************/
1241         /*                    Set the MA Type                           */
1242         /****************************************************************/
1243         reg8 = pci_read_config8(MEMCTRL, 0x50);
1244         reg8 &= 0x11;
1245         pci_write_config8(MEMCTRL, 0x50, reg8);
1246
1247         reg8 = pci_read_config8(MEMCTRL, 0x51);
1248         reg8 &= 0x11;
1249         pci_write_config8(MEMCTRL, 0x51, reg8);
1250
1251         reg8 = pci_read_config8(MEMCTRL, 0x6b);
1252         reg8 &= ~0x08;
1253         pci_write_config8(MEMCTRL, 0x6b, reg8);
1254
1255         for (i = 0; i < 4; i += 2) {
1256                 reg8 = pci_read_config8(PCI_DEV(0, 0, 4), (SCRATCH_RANK_0 + i));
1257                 if (reg8) {
1258                         reg8 = pci_read_config8(PCI_DEV(0, 0, 4), (SCRATCH_RANK0_MA_REG + i));
1259                         reg8 &= (MA_Bank + MA_Column);
1260                         val = pci_read_config8(MEMCTRL, 0x50);
1261                         if (i == 0) {
1262                                 reg8 <<= 4;
1263                                 val &= 0x1f;
1264                         } else
1265                                 val &= 0xf1;
1266                         val |= reg8;
1267                         pci_write_config8(MEMCTRL, 0x50, val);
1268                 }
1269         }
1270
1271         /****************************************************************/
1272         /*                 Set Start and Ending Address                 */
1273         /****************************************************************/
1274         dl = 0;                 /* Begin Address */
1275         dh = 0;                 /* Ending Address */
1276         for (i = 0; i < 4; i++) {
1277                 reg8 = pci_read_config8(PCI_DEV(0, 0, 4), (SCRATCH_RANK_0 + i));
1278                 if (reg8) {
1279                         reg8 = pci_read_config8(PCI_DEV(0, 0, 4), (SCRATCH_RANK0_SIZE_REG + i));
1280                         if (reg8 == 0)
1281                                 continue;
1282                         dh += reg8;
1283                         pci_write_config8(MEMCTRL, (0x40 + i), dh);
1284                         pci_write_config8(MEMCTRL, (0x48 + i), dl);
1285                         dl = dh;
1286                 }
1287         }
1288         dh <<= 2;
1289         // F7_Rx57 Ending address mirror register
1290         pci_write_config8(PCI_DEV(0, 0, 7), 0x57, dh);
1291         dev = pci_locate_device(PCI_ID(0x1106, 0x324e), 0);
1292         pci_write_config8(dev, 0x57, dh);
1293         // LOW TOP Address
1294         pci_write_config8(MEMCTRL, 0x88, dh);
1295         pci_write_config8(MEMCTRL, 0x85, dh);
1296         // also program vlink mirror
1297         pci_write_config8(PCI_DEV(0, 0, 7), 0xe5, dh);
1298
1299         /****************************************************************/
1300         /*            Set Physical to Virtual Rank mapping              */
1301         /****************************************************************/
1302         pci_write_config32(MEMCTRL, 0x54, 0x0);
1303         for (i = 0; i < 4; i++) {
1304                 reg8 = pci_read_config8(PCI_DEV(0, 0, 4), (SCRATCH_RANK_0 + i));
1305                 if (reg8) {
1306                         reg8 = pci_read_config8(MEMCTRL, (0x54 + (i >> 1)));
1307                         if (i & 0x1) {  /* Odd Rank */
1308                                 reg8 &= 0xf0;
1309                                 reg8 |= (0x8 | i);
1310                         } else {        /* Even Rank */
1311
1312                                 reg8 &= 0x0f;
1313                                 reg8 |= ((0x8 | i) << 4);
1314                         }
1315                         pci_write_config8(MEMCTRL, (0x54 + (i >> 1)), reg8);
1316                 }
1317         }
1318
1319         /****************************************************************/
1320         /*                   Set DRAM Refresh Counter                   */
1321         /****************************************************************/
1322         val = pci_read_config8(MEMCTRL, 0X90) & 0X7;
1323         val <<= 1;
1324         reg8 = pci_read_config8(PCI_DEV(0, 0, 4), SCRATCH_DRAM_256M_BIT);
1325         if (reg8)
1326                 val++;
1327         pci_write_config8(MEMCTRL, 0x6a, REFC_Table[val]);
1328
1329         /****************************************************************/
1330         /*  Chipset Performance UP and other setting after DRAM Sizing  */
1331         /****************************************************************/
1332         /* Dram Registers */
1333         val = sizeof(Dram_Table) / sizeof(Dram_Table[0]);
1334         for (i = 0; i < val; i += 3) {
1335                 reg8 = pci_read_config8(MEMCTRL, Dram_Table[i]);
1336                 reg8 &= Dram_Table[i + 1];
1337                 reg8 |= Dram_Table[i + 2];
1338                 pci_write_config8(MEMCTRL, Dram_Table[i], reg8);
1339         }
1340
1341         /* Host Registers */
1342         val = sizeof(Host_Table) / sizeof(Host_Table[0]);
1343         for (i = 0; i < val; i += 3) {
1344                 reg8 = pci_read_config8(HOSTCTRL, Host_Table[i]);
1345                 reg8 &= Host_Table[i + 1];
1346                 reg8 |= Host_Table[i + 2];
1347                 pci_write_config8(HOSTCTRL, Host_Table[i], reg8);
1348         }
1349
1350         /* PM Registers */
1351 #ifdef SETUP_PM_REGISTERS
1352         val = sizeof(PM_Table) / sizeof(PM_Table[0]);
1353         for (i = 0; i < val; i += 3) {
1354                 reg8 = pci_read_config8(PCI_DEV(0, 0, 4), PM_Table[i]);
1355                 reg8 &= PM_Table[i + 1];
1356                 reg8 |= PM_Table[i + 2];
1357                 pci_write_config8(PCI_DEV(0, 0, 4), PM_Table[i], reg8);
1358         }
1359 #endif
1360         pci_write_config8(HOSTCTRL, 0x5d, 0xb2);
1361
1362         /****************************************************************/
1363         /*              UMA registers for N-series projects             */
1364         /****************************************************************/
1365
1366         /* Manual setting frame buffer bank */
1367         for (i = 0; i < 4; i++) {
1368                 reg8 = pci_read_config8(PCI_DEV(0, 0, 4), (SCRATCH_RANK_0 + i));
1369                 if (reg8)
1370                         val = i;
1371         }
1372         pci_write_config8(MEMCTRL, 0xb0, val);
1373         reg8 = 0x40;            // Frame buffer size 64M
1374         reg8 |= 0x80;           // VGA Enable
1375         reg8 |= 0x0a;           // A[31:28] = 1010b
1376         pci_write_config8(MEMCTRL, 0xa1, reg8);
1377
1378 #ifdef ECC
1379         // Clear Ecc
1380         outl(0x80000180, 0xcf8);
1381         outb(0xff, 0xcfc);
1382         // Enable Ecc
1383         outl(0x80000188, 0xcf8);
1384         outb(0xcf, 0xcfc);
1385
1386         reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xa5);
1387         reg8 |= 0x10;
1388         pci_write_config8(PCI_DEV(0, 0, 0), 0xa5, reg8);
1389
1390         reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0x91);
1391         reg8 |= 0x20;
1392         pci_write_config8(PCI_DEV(0, 0, 0), 0x91, reg8);
1393 #endif
1394
1395         static const struct regmask {
1396                 u8 reg;
1397                 u8 mask;
1398                 u8 val;
1399         } b0d1f0[] = {
1400                 { 0x40, 0x00, 0x8b},
1401                 { 0x41, 0x80, 0x43},
1402                 { 0x42, 0x00, 0x62},
1403                 { 0x43, 0x00, 0x44},
1404                 { 0x44, 0x00, 0x34},
1405                 { 0x45, 0x00, 0x72}
1406         }, b0d0f3[] = {
1407                 { 0x53, 0xf0, 0x0f},
1408                 { 0x60, 0x00, 0x03},
1409                 { 0x65, 0x00, 0xd9},
1410                 { 0x66, 0x00, 0x80},
1411                 { 0x67, 0x00, 0x00},
1412                 { 0x68, 0x00, 0x01},
1413                 { 0x69, 0xe0, 0x03},
1414                 { 0x6b, 0x00, 0x10},
1415                 { 0x6c, 0xc1, 0x08},
1416                 { 0x6e, 0x00, 0x89},
1417                 { 0x6f, 0x00, 0x51},
1418                 { 0x75, ~0x40, 0x40},
1419                 { 0x76, 0x8f, 0x00},
1420                 { 0x7b, 0x00, 0xa0},
1421                 { 0x86, 0x01, 0x24},
1422                 { 0x86, 0x04, 0x29},
1423                 { 0x8c, 0x00, 0x00},
1424                 { 0x8d, 0x00, 0x00},
1425                 { 0x95, ~0x40, 0x00},
1426                 { 0xa2, 0x00, 0x44},
1427                 { 0xb1, 0x00, 0xaa}
1428         }, b0d0f0[] = {
1429                 { 0x4d, 0x00, 0x24},
1430                 { 0x4f, 0x00, 0x01},
1431                 { 0xbc, 0x00, 0x21},
1432                 { 0xbe, 0x00, 0x00},
1433                 { 0xbf, 0x7f, 0x80}
1434         }, b0d17f0[] = {
1435                 { 0x40, ~0x01, 0x01},           // enable timer/counter shadow registers
1436                 { 0x67, ~0x03, 0x01},
1437                 { 0x5b, ~0x01, 0x00},
1438                 { 0x8d, ~0x02, 0x02},
1439                 { 0x97, ~0x80, 0x00},
1440                 { 0xd2, ~0x18, 0x00},
1441                 { 0xe2, ~0x36, 0x06},
1442                 { 0xe4, ~0x80, 0x00},
1443                 { 0xe5, 0x00, 0x40},
1444                 { 0xe6, 0x00, 0x20},
1445                 { 0xe7, ~0xd0, 0xc0},
1446                 { 0xec, ~0x08, 0x00}
1447         }, b0d17f7[] = {
1448                 { 0x4e, ~0x80, 0x80},
1449                 { 0x4f, ~(1 << 6), 1 << 6 },    /* PG_CX700: 14.1.1 enable P2P Bridge Header for External PCI Bus */
1450                 { 0x74, ~0x00, 0x04},           /* PG_CX700: 14.1.2 APIC FSB directly up to snmic, not on pci */
1451                 { 0x7c, ~0x00, 0x02},           /* PG_CX700: 14.1.1 APIC FSB directly up to snmic, not on pci */
1452                 { 0xe6, 0x0, 0x04}              // MSI post
1453         }, b0d19f0[] = {        /* P2PE */
1454                 { 0x42, ~0x08, 0x08},           // Disable HD Audio,
1455                 { 0x40, ~0xc0, 0x80}            // 14.1.3.1.1 of the PG: extended cfg mode for pcie. enable capability, but don't activate
1456         }, b0d0f2[] = {
1457                 { 0x50, ~0x40, 0x88},
1458                 { 0x51, 0x80, 0x7b},
1459                 { 0x52, 0x90, 0x6f},
1460                 { 0x53, 0x00, 0x88},
1461                 { 0x54, 0xe4, 0x16},
1462                 { 0x55, 0xf2, 0x04},
1463                 { 0x56, 0x0f, 0x00},
1464                 { 0x57, ~0x04, 0x00},
1465                 { 0x5d, 0x00, 0xb2},
1466                 { 0x5e, 0x00, 0x88},
1467                 { 0x5f, 0x00, 0xc7},
1468                 { 0x5c, 0x00, 0x01}
1469         };
1470
1471         REGISTERPRESET(0, 0, 0, b0d0f0);
1472         REGISTERPRESET(0, 0, 2, b0d0f2);
1473         REGISTERPRESET(0, 0, 3, b0d0f3);
1474         REGISTERPRESET(0, 1, 0, b0d1f0);
1475         REGISTERPRESET(0, 17, 0, b0d17f0);
1476         REGISTERPRESET(0, 17, 7, b0d17f7);
1477         REGISTERPRESET(0, 19, 0, b0d19f0);
1478 }