2 * This file is part of the coreboot project.
4 * Copyright (C) 2007-2009 coresystems GmbH
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <console/console.h>
23 #include <device/device.h>
24 #include <device/pci.h>
25 #include <device/hypertransport.h>
26 #include <device/pci_ids.h>
31 #include <cpu/x86/mtrr.h>
33 #include "northbridge.h"
35 #if CONFIG_WRITE_HIGH_TABLES==1
39 static void pci_domain_set_resources(device_t dev)
44 unsigned long tomk, tolmk;
45 unsigned char rambits;
48 pci_tolm = find_pci_tolm(dev->link_list);
49 mc_dev = dev_find_device(PCI_VENDOR_ID_VIA, 0x3324, 0);
51 rambits = pci_read_config8(mc_dev, 0x88);
54 /* Get memory size and frame buffer from northbridge's registers.
56 * If register contains an invalid value we set frame buffer size to a
57 * default of 32M, but that probably won't happen.
59 reg = pci_read_config8(mc_dev, 0xa1);
63 /* TOP 1M SMM Memory */
64 if (reg == 0x0 || reg == 0x6 || reg == 0x7)
65 tomk = (((rambits << 6) - 32 - 1) * 1024); // Set frame buffer 32M for default
67 tomk = (((rambits << 6) - (4 << reg) - 1) * 1024);
69 /* Compute the top of Low memory */
70 tolmk = pci_tolm >> 10;
72 /* The PCI hole does does not overlap the memory. */
74 tolmk -= 1024; // TOP 1M SM Memory
77 #if CONFIG_WRITE_HIGH_TABLES == 1
78 high_tables_base = (tolmk * 1024) - HIGH_MEMORY_SIZE;
79 high_tables_size = HIGH_MEMORY_SIZE;
80 printk(BIOS_DEBUG, "tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n",
81 tomk*1024, high_tables_base, high_tables_size);
84 /* Report the memory regions */
87 /* TODO: Hole needed? Should this go elsewhere? */
88 ram_resource(dev, idx++, 0, 640); /* first 640k */
89 ram_resource(dev, idx++, 768, (tolmk - 768)); /* leave a hole for vga */
90 assign_resources(dev->link_list);
93 static struct device_operations pci_domain_ops = {
94 .read_resources = pci_domain_read_resources,
95 .set_resources = pci_domain_set_resources,
96 .enable_resources = NULL,
98 .scan_bus = pci_domain_scan_bus,
101 static void cpu_bus_init(device_t dev)
103 initialize_cpus(dev->link_list);
106 static void cpu_bus_noop(device_t dev)
110 static struct device_operations cpu_bus_ops = {
111 .read_resources = cpu_bus_noop,
112 .set_resources = cpu_bus_noop,
113 .enable_resources = cpu_bus_noop,
114 .init = cpu_bus_init,
118 static void enable_dev(struct device *dev)
120 /* Our wonderful device model */
121 if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
122 dev->ops = &pci_domain_ops;
124 } else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
125 dev->ops = &cpu_bus_ops;
129 struct chip_operations northbridge_via_cx700_ops = {
130 CHIP_NAME("VIA CX700 Northbridge")
131 .enable_dev = enable_dev