2 * This file is part of the coreboot project.
4 * Copyright (C) 2007-2009 coresystems GmbH
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 // other bioses use this, too:
21 #define SMBUS_IO_BASE 0x0500
23 #define SMBHSTSTAT SMBUS_IO_BASE + 0x0
24 #define SMBSLVSTAT SMBUS_IO_BASE + 0x1
25 #define SMBHSTCTL SMBUS_IO_BASE + 0x2
26 #define SMBHSTCMD SMBUS_IO_BASE + 0x3
27 #define SMBXMITADD SMBUS_IO_BASE + 0x4
28 #define SMBHSTDAT0 SMBUS_IO_BASE + 0x5
29 #define SMBHSTDAT1 SMBUS_IO_BASE + 0x6
31 #define SMBBLKDAT SMBUS_IO_BASE + 0x7
32 #define SMBSLVCTL SMBUS_IO_BASE + 0x8
33 #define SMBTRNSADD SMBUS_IO_BASE + 0x9
34 #define SMBSLVDATA SMBUS_IO_BASE + 0xa
35 #define SMLINK_PIN_CTL SMBUS_IO_BASE + 0xe
36 #define SMBUS_PIN_CTL SMBUS_IO_BASE + 0xf
38 /* Define register settings */
39 #define HOST_RESET 0xff
40 #define READ_CMD 0x01 // 1 in the 0 bit of SMBHSTADD states to READ
42 #define SMBUS_TIMEOUT (100*1000*10)
44 #define I2C_TRANS_CMD 0x40
45 #define CLOCK_SLAVE_ADDRESS 0x69
47 #define SMBUS_DELAY() outb(0x80, 0x80)
49 /* Debugging macros. */
50 #if CONFIG_DEBUG_SMBUS
51 #define PRINT_DEBUG(x) print_debug(x)
52 #define PRINT_DEBUG_HEX16(x) print_debug_hex16(x)
54 #define PRINT_DEBUG(x)
55 #define PRINT_DEBUG_HEX16(x)
58 /* Internal functions */
59 #if CONFIG_DEBUG_SMBUS
60 static void smbus_print_error(unsigned char host_status_register, int loops)
62 /* Check if there actually was an error */
63 if (host_status_register == 0x00 || host_status_register == 0x40 ||
64 host_status_register == 0x42)
66 print_err("SMBus Error: ");
67 print_err_hex8(host_status_register);
70 if (loops >= SMBUS_TIMEOUT) {
71 print_err("SMBus Timout\n");
73 if (host_status_register & (1 << 4)) {
74 print_err("Interrup/SMI# was Failed Bus Transaction\n");
76 if (host_status_register & (1 << 3)) {
77 print_err("Bus Error\n");
79 if (host_status_register & (1 << 2)) {
80 print_err("Device Error\n");
82 if (host_status_register & (1 << 1)) {
83 /* This isn't a real error... */
84 print_debug("Interrupt/SMI# was Successful Completion\n");
86 if (host_status_register & (1 << 0)) {
87 print_err("Host Busy\n");
92 static void smbus_wait_until_ready(void)
98 /* Yes, this is a mess, but it's the easiest way to do it */
99 while (((inb(SMBHSTSTAT) & 1) == 1) && (loops <= SMBUS_TIMEOUT)) {
103 #if CONFIG_DEBUG_SMBUS
104 /* Some systems seem to have a flakey SMBus. No need to spew a lot of
105 * errors on those, once we know that SMBus access is principally
108 smbus_print_error(inb(SMBHSTSTAT), loops);
112 static void smbus_reset(void)
114 outb(HOST_RESET, SMBHSTSTAT);
117 /* Public functions */
118 static void set_ics_data(unsigned char dev, int data, char len)
122 /* clear host data port */
123 outb(0x00, SMBHSTDAT0);
125 smbus_wait_until_ready();
127 /* read to reset block transfer counter */
130 /* fill blocktransfer array */
132 //char d2_data[] = {0x0d,0x00,0x3f,0xcd,0x7f,0xbf,0x1a,0x2a,0x01,0x0f,0x0b,0x00,0x8d,0x9b};
133 outb(0x0d, SMBBLKDAT);
134 outb(0x00, SMBBLKDAT);
135 outb(0x3f, SMBBLKDAT);
136 outb(0xcd, SMBBLKDAT);
137 outb(0x7f, SMBBLKDAT);
138 outb(0xbf, SMBBLKDAT);
139 outb(0x1a, SMBBLKDAT);
140 outb(0x2a, SMBBLKDAT);
141 outb(0x01, SMBBLKDAT);
142 outb(0x0f, SMBBLKDAT);
143 outb(0x0b, SMBBLKDAT);
144 outb(0x80, SMBBLKDAT);
145 outb(0x8d, SMBBLKDAT);
146 outb(0x9b, SMBBLKDAT);
148 //char d4_data[] = {0x08,0xff,0x3f,0x00,0x00,0xff,0xff,0xff,0xff};
149 outb(0x08, SMBBLKDAT);
150 outb(0xff, SMBBLKDAT);
151 outb(0x3f, SMBBLKDAT);
152 outb(0x00, SMBBLKDAT);
153 outb(0x00, SMBBLKDAT);
154 outb(0xff, SMBBLKDAT);
155 outb(0xff, SMBBLKDAT);
156 outb(0xff, SMBBLKDAT);
157 outb(0xff, SMBBLKDAT);
160 //for (i=0; i < len; i++)
161 // outb(data[i],SMBBLKDAT);
163 outb(dev, SMBXMITADD);
165 outb(len, SMBHSTDAT0);
166 outb(0x74, SMBHSTCTL);
170 smbus_wait_until_ready();
176 static unsigned int get_spd_data(const struct mem_controller *ctrl, unsigned int dimm,
179 unsigned int val, addr;
183 /* clear host data port */
184 outb(0x00, SMBHSTDAT0);
186 smbus_wait_until_ready();
188 /* Fetch the SMBus address of the SPD ROM from
189 * the ctrl struct in romstage.c in case they are at
190 * non-standard positions.
191 * SMBus Address shifted by 1
193 addr = (ctrl->channel0[dimm]) << 1;
195 outb(addr | 0x1, SMBXMITADD);
196 outb(offset, SMBHSTCMD);
197 outb(0x48, SMBHSTCTL);
201 smbus_wait_until_ready();
203 val = inb(SMBHSTDAT0);
208 static void enable_smbus(void)
212 /* The CX700 ISA Bridge (0x1106, 0x8324) is hardcoded to this location,
215 dev = PCI_DEV(0, 17, 0);
217 /* SMBus Clock Select: Divider fof 14.318MHz */
218 pci_write_config8(dev, 0x94, 0x20);
220 /* SMBus I/O Base, enable SMBus */
221 pci_write_config16(dev, 0xd0, SMBUS_IO_BASE | 1);
223 /* SMBus Clock from 128K Source, Enable SMBus Host Controller */
224 pci_write_config8(dev, 0xd2, 0x05);
226 /* Enable I/O decoding */
227 pci_write_config16(dev, 0x04, 0x0003);
229 /* Setup clock chips */
230 set_ics_data(0xd2, 0, 14);
231 set_ics_data(0xd4, 0, 9);
234 /* Debugging Function */
235 #if CONFIG_DEBUG_SMBUS
236 static void dump_spd_data(const struct mem_controller *ctrl)
238 int dimm, offset, regs;
241 for (dimm = 0; dimm < DIMM_SOCKETS; dimm++) {
242 print_debug("SPD Data for DIMM ");
243 print_debug_hex8(dimm);
246 val = get_spd_data(ctrl, dimm, 0);
249 } else if (val == 0x80) {
252 print_debug("No DIMM present\n");
255 for (offset = 0; offset < regs; offset++) {
256 print_debug(" Offset ");
257 print_debug_hex8(offset);
258 print_debug(" = 0x");
259 print_debug_hex8(get_spd_data(ctrl, dimm, offset));
265 #define dump_spd_data(ctrl)