src/northbridge/via/cx700/cx700_vga.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007-2009 coresystems GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18  */
  19
  20 #include <console/console.h>
  21 #include <arch/io.h>
  22 #include <stdint.h>
  23 #include <device/device.h>
  24 #include <device/pci.h>
  25 #include <device/pci_ids.h>
  26 #include <stdlib.h>
  27 #include <string.h>
  28 #include <bitops.h>
  29 #include <cpu/cpu.h>
  30 #include <cpu/x86/mtrr.h>
  31 #include <cpu/x86/msr.h>
  32 #include <arch/interrupt.h>
  33 #include "chip.h"
  34 #include "northbridge.h"
  35
  36 /* PCI Domain 1 Device 0 Function 0 */
  37
  38 #define SR_INDEX        0x3c4
  39 #define SR_DATA         0x3c5
  40 #define CRTM_INDEX      0x3b4
  41 #define CRTM_DATA       0x3b5
  42 #define CRTC_INDEX      0x3d4
  43 #define CRTC_DATA       0x3d5
  44
  45 static int via_cx700_int15_handler(struct eregs *regs)
  46 {
  47         int res=-1;
  48         printk(BIOS_DEBUG, "via_cx700_int15_handler\n");
  49         switch(regs->eax & 0xffff) {
  50         case 0x5f19:
  51                 break;
  52         case 0x5f18:
  53                 regs->eax=0x5f;
  54                 regs->ebx=0x545; // MCLK = 133, 32M frame buffer, 256 M main memory
  55                 regs->ecx=0x060;
  56                 res=0;
  57                 break;
  58         case 0x5f00:
  59                 regs->eax = 0x8600;
  60                 break;
  61         case 0x5f01:
  62                 regs->eax = 0x5f;
  63                 regs->ecx = (regs->ecx & 0xffffff00 ) | 2; // panel type =  2 = 1024 * 768
  64                 res = 0;
  65                 break;
  66         case 0x5f02:
  67                 regs->eax=0x5f;
  68                 regs->ebx= (regs->ebx & 0xffff0000) | 2;
  69                 regs->ecx= (regs->ecx & 0xffff0000) | 0x401;  // PAL + crt only
  70                 regs->edx= (regs->edx & 0xffff0000) | 0;  // TV Layout - default
  71                 res=0;
  72                 break;
  73         case 0x5f0f:
  74                 regs->eax=0x860f;
  75                 break;
  76         default:
  77                 printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n",
  78                                 regs->eax & 0xffff);
  79                 break;
  80         }
  81         return res;
  82 }
  83
  84 void write_protect_vgabios(void)
  85 {
  86         device_t dev;
  87
  88         printk(BIOS_DEBUG, "write_protect_vgabios\n");
  89
  90         dev = dev_find_device(PCI_VENDOR_ID_VIA, 0x3324, 0);
  91         if (dev)
  92                 pci_write_config8(dev, 0x80, 0xff);
  93
  94         dev = dev_find_device(PCI_VENDOR_ID_VIA, 0x7324, 0);
  95         if (dev)
  96                 pci_write_config8(dev, 0x61, 0xff);
  97 }
  98
  99 static void vga_init(device_t dev)
 100 {
 101         u8 reg8;
 102
 103         mainboard_interrupt_handlers(0x15, &via_cx700_int15_handler);
 104
 105         //*
 106         pci_write_config8(dev, 0x04, 0x07);
 107         pci_write_config8(dev, 0x3e, 0x02);
 108         pci_write_config8(dev, 0x0d, 0x40);
 109         pci_write_config32(dev, 0x10, 0xa0000008);
 110         pci_write_config32(dev, 0x14, 0xdd000000);
 111         pci_write_config8(dev, 0x3c, 0x0b);
 112         //*/
 113
 114         printk(BIOS_DEBUG, "Initializing VGA...\n");
 115
 116         pci_dev_init(dev);
 117
 118         printk(BIOS_DEBUG, "Enable VGA console\n");
 119         // this is how it should look:
 120         //   call_bios_interrupt(0x10,0x4f1f,0x8003,1,0);
 121         // this is how it looks:
 122         vga_enable_console();
 123
 124         /* It's not clear if these need to be programmed before or after
 125          * the VGA bios runs. Try both, clean up later */
 126         /* Set memory rate to 200MHz */
 127         outb(0x3d, CRTM_INDEX);
 128         reg8 = inb(CRTM_DATA);
 129         reg8 &= 0x0f;
 130         reg8 |= (0x3 << 4);
 131         outb(0x3d, CRTM_INDEX);
 132         outb(reg8, CRTM_DATA);
 133
 134         /* Set framebuffer size to 32mb */
 135         reg8 = (32 / 4);
 136         outb(0x39, SR_INDEX);
 137         outb(reg8, SR_DATA);
 138 }
 139
 140 static struct device_operations vga_operations = {
 141         .read_resources = pci_dev_read_resources,
 142         .set_resources = pci_dev_set_resources,
 143         .enable_resources = pci_dev_enable_resources,
 144         .init = vga_init,
 145         .ops_pci = 0,
 146 };
 147
 148 static const struct pci_driver vga_driver __pci_driver = {
 149         .ops = &vga_operations,
 150         .vendor = PCI_VENDOR_ID_VIA,
 151         .device = 0x3157,
 152 };