2 * This file is part of the coreboot project.
4 * Copyright (C) 2008 VIA Technologies, Inc.
5 * (Written by Aaron Lwe <aaron.lwe@gmail.com> for VIA)
6 * Copyright (C) 2007 Corey Osgood <corey.osgood@gmail.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
23 #include <console/console.h>
26 #include <device/device.h>
27 #include <device/pci.h>
28 #include <device/pci_ids.h>
34 #include "northbridge.h"
37 static void memctrl_init(device_t dev)
42 u8 pagec, paged, pagee, pagef;
45 /* Set up the vga framebuffer size */
46 reg16 = (log2(CONFIG_VIDEO_MB) << 12) | (1 << 15);
47 pci_write_config16(dev, 0xa0, reg16);
49 /* Set up VGA timers */
50 pci_write_config8(dev, 0xa2, 0x44);
52 for (ranks = 0x4b; ranks >= 0x48; ranks--) {
53 if (pci_read_config8(dev, ranks)) {
62 /* GMINT Misc. FrameBuffer rank */
63 pci_write_config16(dev, 0xb0, reg16);
65 pci_write_config8(dev, 0xb8, 0x08);
68 pagec = 0xff, paged = 0xff, pagee = 0xff, pagef = 0x30;
69 /* PAGE C, D, E are all read write enable */
70 pci_write_config8(dev, 0x80, pagec);
71 pci_write_config8(dev, 0x81, paged);
72 pci_write_config8(dev, 0x82, pagee);
73 /* PAGE F are read/writable */
74 shadowreg = pci_read_config8(dev, 0x83);
76 pci_write_config8(dev, 0x83, shadowreg);
78 vlink_dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_CN700_VLINK, 0);
80 pci_write_config8(vlink_dev, 0x61, pagec);
81 pci_write_config8(vlink_dev, 0x62, paged);
82 pci_write_config8(vlink_dev, 0x64, pagee);
83 shadowreg = pci_read_config8(vlink_dev, 0x63);
85 pci_write_config8(vlink_dev, 0x63, shadowreg);
89 static const struct device_operations memctrl_operations = {
90 .read_resources = cn700_noop,
94 static const struct pci_driver memctrl_driver __pci_driver = {
95 .ops = &memctrl_operations,
96 .vendor = PCI_VENDOR_ID_VIA,
97 .device = PCI_DEVICE_ID_VIA_CN700_MEMCTRL,
100 static void pci_domain_read_resources(device_t dev)
102 struct resource *resource;
104 printk_spew("Entering cn700 pci_domain_read_resources.\n");
106 /* Initialize the system wide io space constraints */
107 resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0));
108 resource->limit = 0xffffUL;
109 resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
112 /* Initialize the system wide memory resources constraints */
113 resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0));
114 resource->limit = 0xffffffffULL;
115 resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
118 printk_spew("Leaving cn700 pci_domain_read_resources.\n");
121 static void ram_resource(device_t dev, unsigned long index,
122 unsigned long basek, unsigned long sizek)
124 struct resource *resource;
129 resource = new_resource(dev, index);
130 resource->base = ((resource_t)basek) << 10;
131 resource->size = ((resource_t)sizek) << 10;
132 resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
133 IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
136 static void tolm_test(void *gp, struct device *dev, struct resource *new)
138 struct resource **best_p = gp;
139 struct resource *best;
141 if (!best || (best->base > new->base)) {
147 static u32 find_pci_tolm(struct bus *bus)
149 print_debug("Entering find_pci_tolm\n");
150 struct resource *min;
153 search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min);
155 if (min && tolm > min->base) {
158 print_debug("Leaving find_pci_tolm\n");
162 static void pci_domain_set_resources(device_t dev)
165 * the order is important to find the correct ram size.
167 static const u8 ramregs[] = {0x43, 0x42, 0x41, 0x40};
171 printk_spew("Entering cn700 pci_domain_set_resources.\n");
173 pci_tolm = find_pci_tolm(&dev->link[0]);
174 mc_dev = dev_find_device(PCI_VENDOR_ID_VIA,
175 PCI_DEVICE_ID_VIA_CN700_MEMCTRL, 0);
178 unsigned long tomk, tolmk;
179 unsigned char rambits;
183 * once the register value is not zero, the ramsize is
184 * this register's value multiply 64 * 1024 * 1024
186 for(rambits = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) {
188 rambits = pci_read_config8(mc_dev, ramregs[i]);
193 tomk = rambits * 64 * 1024;
194 printk_spew("tomk is 0x%x\n", tomk);
195 /* Compute the Top Of Low Memory, in Kb */
196 tolmk = pci_tolm >> 10;
198 /* The PCI hole does does not overlap the memory. */
201 /* Report the memory regions */
203 /* TODO: Hole needed? */
204 ram_resource(dev, idx++, 0, 640); /* first 640k */
205 /* Leave a hole for vga, 0xa0000 - 0xc0000 */
206 ram_resource(dev, idx++, 768, (tolmk - 768 - CONFIG_VIDEO_MB * 1024));
208 assign_resources(&dev->link[0]);
211 static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
213 printk_debug("Entering cn700 pci_domain_scan_bus.\n");
215 max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
219 static const struct device_operations pci_domain_ops = {
220 .read_resources = pci_domain_read_resources,
221 .set_resources = pci_domain_set_resources,
222 .enable_resources = enable_childrens_resources,
224 .scan_bus = pci_domain_scan_bus,
227 static void cpu_bus_init(device_t dev)
229 initialize_cpus(&dev->link[0]);
232 static void cpu_bus_noop(device_t dev)
236 static const struct device_operations cpu_bus_ops = {
237 .read_resources = cpu_bus_noop,
238 .set_resources = cpu_bus_noop,
239 .enable_resources = cpu_bus_noop,
240 .init = cpu_bus_init,
244 static void enable_dev(struct device *dev)
246 printk_spew("In cn700 enable_dev for device %s.\n", dev_path(dev));
248 /* Set the operations if it is a special bus type */
249 if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
250 dev->ops = &pci_domain_ops;
253 else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
254 dev->ops = &cpu_bus_ops;
258 struct chip_operations northbridge_via_cn700_ops = {
259 CHIP_NAME("VIA CN700 Northbridge")
260 .enable_dev = enable_dev,