2 * (C) Copyright 2005 Nick Barker <nick.barker9@btinternet.com>
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
22 Automatically detect and set up ddr dram on the CLE266 chipset.
23 Assumes DDR memory, though chipset also supports SDRAM
24 Assumes at least 266Mhz memory as no attempt is made to clock
25 the chipset down if slower memory is installed.
27 256 Mb 266Mhz 1 Bank (i.e. single sided)
28 256 Mb 266Mhz 2 Bank (i.e. double sided)
29 512 Mb 266Mhz 2 Bank (i.e. double sided)
31 /* ported and enhanced from assembler level code in coreboot v1 */
34 #include <sdram_mode.h>
36 #include <cpu/x86/mtrr.h>
39 static void dimm_read(unsigned long bank,unsigned long x)
42 volatile unsigned long y;
44 y = * (volatile unsigned long *) (x+ bank) ;
49 static void print_val(char *str, int val)
52 print_debug_hex8(val);
56 * Configure the bus between the CPU and the northbridge. This might be able to
57 * be moved to post-ram code in the future. For the most part, these registers
58 * should not be messed around with. These are too complex to explain short of
59 * copying the datasheets into the comments, but most of these values are from
60 * the BIOS Porting Guide, so they should work on any board. If they don't,
61 * try the values from your factory BIOS.
63 * TODO: Changing the DRAM frequency doesn't work (hard lockup).
65 * @param dev The northbridge's CPU Host Interface (D0F2).
67 static void c3_cpu_setup(device_t dev)
69 /* Host bus interface registers (D0F2 0x50-0x67) */
70 /* Taken from CN700 and updated from running CN400 */
72 /* Host Bus I/O Circuit (see datasheet) */
73 /* Host Address Pullup/down Driving */
74 pci_write_config8(dev, 0x70, 0x33);
75 pci_write_config8(dev, 0x71, 0x44);
76 pci_write_config8(dev, 0x72, 0x33);
77 pci_write_config8(dev, 0x73, 0x44);
79 /* Output Delay Stagger Control */
80 pci_write_config8(dev, 0x74, 0x70);
82 /* AGTL+ I/O Circuit */
83 pci_write_config8(dev, 0x75, 0x08);
85 /* AGTL+ Compensation Status */
86 pci_write_config8(dev, 0x76, 0x74);
88 /* AGTL+ Auto Compensation Offest */
89 pci_write_config8(dev, 0x77, 0x00);
91 /* Request phase control */
92 pci_write_config8(dev, 0x50, 0xA8);
94 /* Line DRDY# Timing Control */
95 pci_write_config8(dev, 0x60, 0x00);
96 pci_write_config8(dev, 0x61, 0x00);
97 pci_write_config8(dev, 0x62, 0x00);
99 /* QW DRDY# Timing Control */
100 pci_write_config8(dev, 0x63, 0x00);
101 pci_write_config8(dev, 0x64, 0x00);
102 pci_write_config8(dev, 0x65, 0x00);
104 /* Read Line Burst DRDY# Timing Control */
105 pci_write_config8(dev, 0x66, 0x00);
106 pci_write_config8(dev, 0x67, 0x00);
108 /* CPU Interface Control */
109 pci_write_config8(dev, 0x51, 0xFE);
110 pci_write_config8(dev, 0x52, 0xEF);
113 pci_write_config8(dev, 0x53, 0x88);
115 /* Write Policy & Reorder Latecy */
116 pci_write_config8(dev, 0x56, 0x00);
118 /* Delivery-Trigger Control */
119 pci_write_config8(dev, 0x58, 0x00);
122 pci_write_config8(dev, 0x59, 0x30);
124 /* CPU Misc Control */
125 pci_write_config8(dev, 0x5C, 0x00);
128 pci_write_config8(dev, 0x5d, 0xb2);
130 /* Bandwidth Timer */
131 pci_write_config8(dev, 0x5e, 0x88);
133 /* CPU Miscellaneous Control */
134 pci_write_config8(dev, 0x5f, 0xc7);
136 /* CPU Miscellaneous Control */
137 pci_write_config8(dev, 0x55, 0x28);
141 static void ddr_ram_setup(void)
143 uint8_t b, c, bank, ma;
145 unsigned long bank_address;
148 print_debug("CN400 RAM init starting\r\n");
150 pci_write_config8(ctrl.d0f7, 0x75, 0x08);
153 /* No Interleaving or Multi Page */
154 pci_write_config8(ctrl.d0f3, 0x69, 0x00);
155 pci_write_config8(ctrl.d0f3, 0x6b, 0x10);
158 DRAM MA Map Type Device 0 Fn3 Offset 50-51
160 Determine memory addressing based on the module's memory technology and
161 arrangement. See Table 4-9 of Intel's 82443GX datasheet for details.
163 Bank 1/0 MA map type 50[7-5]
164 Bank 1/0 command rate 50[4]
165 Bank 3/2 MA map type 50[3-1]
166 Bank 3/2 command rate 50[0]
169 Read SPD byte 17, Number of banks on SDRAM device.
172 b = smbus_read_byte(0x50, SPD_NUM_BANKS_PER_SDRAM);
173 //print_val("Detecting Memory\r\nNumber of Banks ",b);
175 // Only supporting 4 bank chips just now
178 Read SPD byte 3, Number of row addresses.
182 b = smbus_read_byte(0x50, SPD_NUM_ROWS);
183 //print_val("\r\nNumber of Rows ", b);
185 if( b >= 0x0d ){ // 256/512Mb
193 Read SPD byte 13, Primary DRAM width.
195 b = smbus_read_byte(0x50, SPD_PRIMARY_SDRAM_WIDTH);
196 //print_val("\r\nPrimary DRAM width", b);
197 if( b != 4 ) // not 64/128Mb (x4)
202 Read SPD byte 4, Number of column addresses.
204 b = smbus_read_byte(0x50, SPD_NUM_COLUMNS);
205 //print_val("\r\nNo Columns ",b);
206 if( b == 10 || b == 11 || b == 12) c |= 0x60; // 10/11 bit col addr
207 if( b == 9 ) c |= 0x40; // 9 bit col addr
208 if( b == 8 ) c |= 0x20; // 8 bit col addr
210 //print_val("\r\nMA type ", c);
211 pci_write_config8(ctrl.d0f3, 0x50, c);
216 die("DRAM module size is not supported by CN400\r\n");
221 DRAM bank size. See 4.3.1 pg 35
223 5a->5d set to end address for each bank. 1 bit == 32MB
226 5c = bank 0 + b1 + b2
227 5d = bank 0 + b1 + b2 + b3
230 // Read SPD byte 31 Module bank density
232 b = smbus_read_byte(0x50, SPD_DENSITY_OF_EACH_ROW_ON_MODULE);
241 if (bank == 0x48) bank |= 0x01;
247 if (bank == 0x44) bank |= 0x02;
252 if (bank == 0x44) bank |= 0x01;
258 if (bank == 0x40) bank |= 0x02;
265 else if( b & 0x08) c = 0x01; // 32MB
266 else c = 0x01; // Error, use default
268 //print_val("\r\nBank 0 (*32 Mb) ",c);
270 // set bank zero size
271 pci_write_config8(ctrl.d0f3, 0x40, c);
273 // SPD byte 5 # of physical banks
274 b = smbus_read_byte(0x50, SPD_NUM_DIMM_BANKS);
276 //print_val("\r\nNo Physical Banks ",b);
281 //print_val("\r\nTotal Memory (*32 Mb) ",c);
285 die("Only a single DIMM is supported by EPIA-N(L)\r\n");
288 // set banks 1,2,3...
289 pci_write_config8(ctrl.d0f3, 0x41,c);
290 pci_write_config8(ctrl.d0f3, 0x42,c);
291 pci_write_config8(ctrl.d0f3, 0x43,c);
292 pci_write_config8(ctrl.d0f3, 0x44,c);
293 pci_write_config8(ctrl.d0f3, 0x45,c);
294 pci_write_config8(ctrl.d0f3, 0x46,c);
295 pci_write_config8(ctrl.d0f3, 0x47,c);
299 /* Read SPD byte 18 CAS Latency */
300 b = smbus_read_byte(0x50, SPD_ACCEPTABLE_CAS_LATENCIES);
301 /* print_debug("\r\nCAS Supported ");
309 c = smbus_read_byte(0x50, SPD_MIN_CYCLE_TIME_AT_CAS_MAX);
310 print_val("\r\nCycle time at CL X (nS)", c);
311 c = smbus_read_byte(0x50, SPD_SDRAM_CYCLE_TIME_2ND);
312 print_val("\r\nCycle time at CL X-0.5 (nS)", c);
313 c = smbus_read_byte(0x50, SPD_SDRAM_CYCLE_TIME_3RD);
314 print_val("\r\nCycle time at CL X-1 (nS)", c);
316 bank = smbus_read_byte(0x50, SPD_MIN_CYCLE_TIME_AT_CAS_MAX);
318 /* Setup DRAM Cycle Time */
319 if ( bank <= 0x50 ) bank = 0x14;
320 else if (bank <= 0x60) bank = 0x18;
323 if( b & 0x10 ){ // DDR offering optional CAS 3
324 //print_debug("\r\nStarting at CAS 3");
326 /* see if we can better it */
327 if( b & 0x08 ){ // DDR mandatory CAS 2.5
328 if( smbus_read_byte(0x50, SPD_SDRAM_CYCLE_TIME_2ND) <= bank ){ // we can manage max MHz at CAS 2.5
329 //print_debug("\r\nWe can do CAS 2.5");
333 if( b & 0x04 ){ // DDR mandatory CAS 2
334 if( smbus_read_byte(0x50, SPD_SDRAM_CYCLE_TIME_3RD) <= bank ){ // we can manage max Mhz at CAS 2
335 //print_debug("\r\nWe can do CAS 2");
339 }else{ // no optional CAS values just 2 & 2.5
340 //print_debug("\r\nStarting at CAS 2.5");
341 c = 0x20; // assume CAS 2.5
342 if( b & 0x04){ // Should always happen
343 if( smbus_read_byte(0x50, SPD_SDRAM_CYCLE_TIME_2ND) <= bank){ // we can manage max Mhz at CAS 2
344 //print_debug("\r\nWe can do CAS 2");
351 DRAM Timing Device 0 Fn 3 Offset 56
353 RAS Pulse width 56[7,6]
355 Row pre-charge 56[1,0]
363 RAS/CAS delay 56[3,2]
365 Determine row pre-charge time (tRP)
368 Read SPD byte 27, min row pre-charge time.
371 b = smbus_read_byte(0x50, SPD_MIN_ROW_PRECHARGE_TIME);
373 //print_val("\r\ntRP ",b);
374 if ( b >= (5 * bank)) {
375 c |= 0x03; // set tRP = 5T
377 else if ( b >= (4 * bank)) {
378 c |= 0x02; // set tRP = 4T
380 else if ( b >= (3 * bank)) {
381 c |= 0x01; // set tRP = 3T
385 Determine RAS to CAS delay (tRCD)
387 Read SPD byte 29, min row pre-charge time.
390 b = smbus_read_byte(0x50, SPD_MIN_RAS_TO_CAS_DELAY);
391 //print_val("\r\ntRCD ",b);
393 if ( b >= (5 * bank)) c |= 0x0C; // set tRCD = 5T
394 else if ( b >= (4 * bank)) c |= 0x08; // set tRCD = 4T
395 else if ( b >= (3 * bank)) c |= 0x04; // set tRCD = 3T
398 Determine RAS pulse width (tRAS)
401 Read SPD byte 30, device min active to pre-charge time.
404 b = smbus_read_byte(0x50, SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY);
405 //print_val("\r\ntRAS ",b);
406 if ( b >= (9 * bank)) c |= 0xC0; // set tRAS = 9T
407 else if ( b >= (8 * bank)) c |= 0x80; // set tRAS = 8T
408 else if ( b >= (7 * bank)) c |= 0x40; // set tRAS = 7T
410 /* Write DRAM Timing All Banks I */
411 pci_write_config8(ctrl.d0f3, 0x56, c);
413 /* TWrite DRAM Timing All Banks II */
414 pci_write_config8(ctrl.d0f3, 0x57, 0x1a);
416 /* DRAM arbitration timer */
417 pci_write_config8(ctrl.d0f3, 0x65, 0x99);
420 DRAM Clock Device 0 Fn 3 Offset 68
422 bank = smbus_read_byte(0x50, SPD_MIN_CYCLE_TIME_AT_CAS_MAX);
424 /* Setup DRAM Cycle Time */
427 /* DRAM DDR Control Alert! Alert! See also c3_cpu_setup */
428 /* This sets to 133MHz FSB / DDR400. */
429 pci_write_config8(ctrl.d0f3, 0x68, 0x85);
431 else if (bank <= 0x60)
433 /* DRAM DDR Control Alert! Alert! This hardwires to */
434 /* 133MHz FSB / DDR333. See also c3_cpu_setup */
435 pci_write_config8(ctrl.d0f3, 0x68, 0x81);
439 /* DRAM DDR Control Alert! Alert! This hardwires to */
440 /* 133MHz FSB / DDR266. See also c3_cpu_setup */
441 pci_write_config8(ctrl.d0f3, 0x68, 0x80);
444 /* Delay >= 100ns after DRAM Frequency adjust, See 4.1.1.3 pg 15 */
448 Determine bank interleave
450 Read SPD byte 17, Number of banks on SDRAM device.
453 b = smbus_read_byte(0x50, SPD_NUM_BANKS_PER_SDRAM);
454 if( b == 4) c |= 0x80;
455 else if (b == 2) c |= 0x40;
457 /* 4-Way Interleave With Multi-Paging (From Running System)*/
458 pci_write_config8(ctrl.d0f3, 0x69, c);
460 /* DRAM Arbitration Control */
461 pci_write_config8(ctrl.d0f3, 0x66, 0x82);
464 pci_write_config8(ctrl.d0f3, 0x6e, 0x00);
466 /* Disable refresh for now */
467 pci_write_config8(ctrl.d0f3, 0x6a, 0x00);
471 /* DRAM Clock Control */
472 pci_write_config8(ctrl.d0f3, 0x6c, 0x00);
474 /* DRAM Bus Turn-Around Setting */
475 pci_write_config8(ctrl.d0f3, 0x60, 0x01);
477 /* Disable DRAM refresh */
478 pci_write_config8(ctrl.d0f3,0x6a,0x0);
481 /* Memory Pads Driving and Range Select */
482 pci_write_config8(ctrl.d0f3, 0xe2, 0xAA);
483 pci_write_config8(ctrl.d0f3, 0xe3, 0x00);
484 pci_write_config8(ctrl.d0f3, 0xe4, 0x99);
486 /* DRAM signal timing control */
487 pci_write_config8(ctrl.d0f3, 0x74, 0x99);
488 pci_write_config8(ctrl.d0f3, 0x76, 0x09);
490 pci_write_config8(ctrl.d0f3, 0xe0, 0xAA);
491 pci_write_config8(ctrl.d0f3, 0xe1, 0x00);
492 pci_write_config8(ctrl.d0f3, 0xe6, 0x00);
493 pci_write_config8(ctrl.d0f3, 0xe8, 0xEE);
494 pci_write_config8(ctrl.d0f3, 0xea, 0xEE);
497 /* SPD byte 5 # of physical banks */
498 b = smbus_read_byte(0x50, SPD_NUM_DIMM_BANKS) -1;
501 pci_write_config8(ctrl.d0f3, 0xb0, c);
503 /* Enable DIMM Ranks */
504 pci_write_config8(ctrl.d0f3, 0x48, ma);
507 c = smbus_read_byte(0x50, SPD_SUPPORTED_BURST_LENGTHS);
511 print_debug("Setting Burst Length 8\r\n");
513 CPU Frequency Device 0 Function 2 Offset 54
515 CPU FSB Operating Frequency (bits 7:5)
516 000 : 100MHz 001 : 133MHz
522 Don't change Frequency from power up defaults
523 This seems to lockup the RAM interface
525 c = pci_read_config8(ctrl.d0f2, 0x54);
527 pci_write_config8(ctrl.d0f2, 0x54, c);
528 i = 0x008; // Used later to set SDRAM MSR
532 for( bank = 0 , bank_address=0; bank <= b ; bank++) {
534 DDR init described in Via VT8623 BIOS Porting Guide. Pg 28 (4.2.3.1)
537 /* NOP command enable */
538 c = pci_read_config8(ctrl.d0f3, DRAM_MISC_CTL);
539 c &= 0xf8; /* Clear bits 2-0. */
540 c |= RAM_COMMAND_NOP;
541 pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c);
543 /* read a double word from any address of the dimm */
544 dimm_read(bank_address,0x1f000);
547 /* All bank precharge Command Enable */
548 c = pci_read_config8(ctrl.d0f3, DRAM_MISC_CTL);
549 c &= 0xf8; /* Clear bits 2-0. */
550 c |= RAM_COMMAND_PRECHARGE;
551 pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c);
552 dimm_read(bank_address,0x1f000);
555 /* MSR Enable Low DIMM*/
556 c = pci_read_config8(ctrl.d0f3, DRAM_MISC_CTL);
557 c &= 0xf8; /* Clear bits 2-0. */
558 c |= RAM_COMMAND_MSR_LOW;
559 pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c);
560 /* TODO: Bank Addressing for Different Numbers of Row Addresses */
561 dimm_read(bank_address,0x2000);
563 dimm_read(bank_address,0x800);
566 /* All banks precharge Command Enable */
567 c = pci_read_config8(ctrl.d0f3, DRAM_MISC_CTL);
568 c &= 0xf8; /* Clear bits 2-0. */
569 c |= RAM_COMMAND_PRECHARGE;
570 pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c);
571 dimm_read(bank_address,0x1f200);
573 /* CBR Cycle Enable */
574 c = pci_read_config8(ctrl.d0f3, DRAM_MISC_CTL);
575 c &= 0xf8; /* Clear bits 2-0. */
576 c |= RAM_COMMAND_CBR;
577 pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c);
581 dimm_read(bank_address,0x1f300);
586 c = pci_read_config8(ctrl.d0f3, DRAM_MISC_CTL);
587 c &= 0xf8; /* Clear bits 2-0. */
588 c |= RAM_COMMAND_MSR_LOW;
589 pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c);
593 Mode Register Definition
594 with adjustement so that address calculation is correct - 64 bit technology, therefore
595 a0-a2 refer to byte within a 64 bit long word, and a3 is the first address line presented
596 to DIMM as a row or column address.
599 MR[6] Burst Type 0 = sequential, 1 = interleaved
600 MR[5-3] burst length 001 = 2, 010 = 4, 011 = 8, others reserved
613 CAS 2 0101011000 = 0x158
614 CAS 2.5 1101011000 = 0x358
615 CAS 3 0111011000 = 0x1d8
618 c = pci_read_config8(ctrl.d0f3, 0x56);
619 if( (c & 0x30) == 0x10 )
620 dimm_read(bank_address,(0x150 + i));
621 else if((c & 0x30) == 0x20 )
622 dimm_read(bank_address,(0x350 + i));
624 dimm_read(bank_address,(0x1d0 + i));
627 /* Normal SDRAM Mode */
628 c = pci_read_config8(ctrl.d0f3, DRAM_MISC_CTL);
629 c &= 0xf8; /* Clear bits 2-0. */
630 c |= RAM_COMMAND_NORMAL;
631 pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c);
633 bank_address = pci_read_config8(ctrl.d0f3,0x40+bank) * 0x2000000;
634 } // end of for each bank
637 /* Set DRAM DQS Output Control */
638 pci_write_config8(ctrl.d0f3, 0x79, 0x11);
640 /* Set DQS A/B Input delay to defaults */
641 pci_write_config8(ctrl.d0f3, 0x7A, 0xA1);
642 pci_write_config8(ctrl.d0f3, 0x7B, 0x62);
644 /* SPD byte 5 # of physical banks */
645 b = smbus_read_byte(0x50, SPD_NUM_DIMM_BANKS) -1;
647 /* determine low bond */
649 bank_address = pci_read_config8(ctrl.d0f3,0x40) * 0x2000000;
653 for(i = 0x40 ; i < 0x0ff; i++){
654 pci_write_config8(ctrl.d0f3,0x70,i);
656 *(volatile unsigned long*)(0x4000) = 0;
657 *(volatile unsigned long*)(0x4100+bank_address) = 0;
658 *(volatile unsigned long*)(0x4200) = 0;
659 *(volatile unsigned long*)(0x4300+bank_address) = 0;
660 *(volatile unsigned long*)(0x4400) = 0;
661 *(volatile unsigned long*)(0x4500+bank_address) = 0;
664 *(volatile unsigned long*)(0x4000) = 0x12345678;
665 *(volatile unsigned long*)(0x4100+bank_address) = 0x81234567;
666 *(volatile unsigned long*)(0x4200) = 0x78123456;
667 *(volatile unsigned long*)(0x4300+bank_address) = 0x67812345;
668 *(volatile unsigned long*)(0x4400) = 0x56781234;
669 *(volatile unsigned long*)(0x4500+bank_address) = 0x45678123;
672 if( *(volatile unsigned long*)(0x4000) != 0x12345678)
675 if( *(volatile unsigned long*)(0x4100+bank_address) != 0x81234567)
678 if( *(volatile unsigned long*)(0x4200) != 0x78123456)
681 if( *(volatile unsigned long*)(0x4300+bank_address) != 0x67812345)
684 if( *(volatile unsigned long*)(0x4400) != 0x56781234)
687 if( *(volatile unsigned long*)(0x4500+bank_address) != 0x45678123)
690 // if everything verified then found low bond
694 print_val("\r\nLow Bond ",i);
697 for( ; i <0xff ; i++){
698 pci_write_config8(ctrl.d0f3,0x70, i);
700 *(volatile unsigned long*)(0x8000) = 0;
701 *(volatile unsigned long*)(0x8100+bank_address) = 0;
702 *(volatile unsigned long*)(0x8200) = 0x0;
703 *(volatile unsigned long*)(0x8300+bank_address) = 0;
704 *(volatile unsigned long*)(0x8400) = 0x0;
705 *(volatile unsigned long*)(0x8500+bank_address) = 0;
708 *(volatile unsigned long*)(0x8000) = 0x12345678;
709 *(volatile unsigned long*)(0x8100+bank_address) = 0x81234567;
710 *(volatile unsigned long*)(0x8200) = 0x78123456;
711 *(volatile unsigned long*)(0x8300+bank_address) = 0x67812345;
712 *(volatile unsigned long*)(0x8400) = 0x56781234;
713 *(volatile unsigned long*)(0x8500+bank_address) = 0x45678123;
716 if( *(volatile unsigned long*)(0x8000) != 0x12345678)
719 if( *(volatile unsigned long*)(0x8100+bank_address) != 0x81234567)
722 if( *(volatile unsigned long*)(0x8200) != 0x78123456)
725 if( *(volatile unsigned long*)(0x8300+bank_address) != 0x67812345)
728 if( *(volatile unsigned long*)(0x8400) != 0x56781234)
731 if( *(volatile unsigned long*)(0x8500+bank_address) != 0x45678123)
735 print_val(" High Bond ",i);
736 c = ((i - c)<<1)/3 + c;
737 print_val(" Setting DQS delay",c);
739 pci_write_config8(ctrl.d0f3,0x70,c);
741 pci_write_config8(ctrl.d0f3,0x70,0x67);
744 /* Set DQS ChB Output to the default */
745 pci_write_config8(ctrl.d0f3, 0x71, 0x6c);
747 /* Set DQS Input Delays */
748 pci_write_config8(ctrl.d0f3, 0x72, 0x29);
749 pci_write_config8(ctrl.d0f3, 0x73, 0x99);
752 pci_write_config8(ctrl.d0f3, 0x67, 0x50);
754 /* Enable Toggle Limiting */
755 pci_write_config8(ctrl.d0f4, 0xA3, 0x80);
758 DRAM refresh rate Device 0 F3 Offset 6a
759 TODO :: Fix for different DRAM technologies
760 other than 512Mb and DRAM Freq
761 Units of 16 DRAM clock cycles - 1.
763 //c = pci_read_config8(ctrl.d0f3, 0x68);
765 //b = smbus_read_byte(0x50, SPD_REFRESH);
766 //print_val("SPD_REFRESH = ", b);
768 pci_write_config8(ctrl.d0f3,0x6a,0x6C);
771 /* Enable TLB Auto refresh */
772 b = pci_read_config8(ctrl.d0f3, 0x69);
774 pci_write_config8(ctrl.d0f3, 0x69, b);
776 /* Open Up the Rest of the Shadow RAM */
777 pci_write_config8(ctrl.d0f3,0x80,0xff);
778 pci_write_config8(ctrl.d0f3,0x81,0xff);
781 pci_write_config8(ctrl.d0f7,0x70,0x82);
782 pci_write_config8(ctrl.d0f7,0x73,0x01);
783 pci_write_config8(ctrl.d0f7,0x76,0x50);
785 pci_write_config8(ctrl.d0f7,0x71,0xc8);
787 print_debug("CN400 Init done\r\n");
790 pci_write_config16(ctrl.d0f3, 0xa0, (1 << 15));
791 pci_write_config16(ctrl.d0f3, 0xa4, 0x0010);
793 /* Graphics Control Basic Init. */
794 //pci_write_config8(ctrl.d0f3, 0xb0, 0xFf);
795 //pci_write_config8(ctrl.d0f3, 0xb1, 0xAA);
796 //pci_write_config8(ctrl.d0f3, 0xb2, 0xAA);
797 //pci_write_config8(ctrl.d0f3, 0xb3, 0x5A);
798 //pci_write_config8(ctrl.d0f3, 0xb4, 0x0f);
800 /* AGP Controller Interface Basic Init */
801 //pci_write_config8(ctrl.d0f3, 0xc0, 0x3b);
803 /* VGA device, Basic frame Buffer Init. */
804 //pci_write_config8(ctrl.d0f3, 0xa0, 0x01);
805 /* Bit 7 = Enable VGA When Set to 1 */
806 //pci_write_config8(ctrl.d0f3, 0xa1, 0xef);
807 //pci_write_config8(ctrl.d0f3, 0xa4, 0x00);