2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 Corey Osgood <corey.osgood@gmail.com>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
23 static inline void cn400_noop(device_t dev)
31 #define SR_INDEX 0x3c4
33 #define CRTM_INDEX 0x3b4
34 #define CRTM_DATA 0x3b5
35 #define CRTC_INDEX 0x3d4
36 #define CRTC_DATA 0x3d5
38 /* Memory controller registers */
39 #define RANK0_END 0x40
40 #define RANK1_END 0x41
41 #define RANK2_END 0x42
42 #define RANK3_END 0x43
44 #define DDR_PAGE_CTL 0x69
45 #define DRAM_REFRESH_COUNTER 0x6a
46 #define DRAM_MISC_CTL 0x6b
47 #define CH_A_DQS_OUTPUT_DELAY 0x70
48 #define CH_A_MD_OUTPUT_DELAY 0x71
50 /* RAM init commands */
51 #define RAM_COMMAND_NORMAL (const char) 0x00
52 #define RAM_COMMAND_NOP (const char) 0x01
53 #define RAM_COMMAND_PRECHARGE (const char) 0x02
54 #define RAM_COMMAND_MSR_LOW (const char) 0x03
55 #define RAM_COMMAND_CBR (const char) 0x04
56 #define RAM_COMMAND_MSR_HIGH (const char) 0x05