src/northbridge/motorola/mpc107/mpc107_northbridge.c

   1 #include <console/console.h>
   2 #include <arch/io.h>
   3 #include <stdint.h>
   4 #include <device/device.h>
   5 #include <device/pci.h>
   6 #include <stdlib.h>
   7 #include <string.h>
   8 #include <bitops.h>
   9 #include <cpu/cpu.h>
  10 #include "chip.h"
  11
  12 static void pci_domain_read_resources(device_t dev)
  13 {
  14         struct resource *resource;
  15
  16         /* Initialize the system wide io space constraints */
  17         resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
  18         resource->base  = 0;
  19         resource->limit = 0xffffUL;
  20         resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
  21
  22         /* Initialize the system wide memory resources constraints */
  23         resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
  24         resource->base  = 0x80000000ULL;
  25         resource->limit = 0xfeffffffULL; /* We can put pci resources in the system controll area */
  26         resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
  27 }
  28
  29 static void pci_domain_set_resources(device_t dev)
  30 {
  31         device_t mc_dev;
  32
  33         /* Get the memory controller device */
  34         mc_dev = dev->link[0].children;
  35         if (mc_dev) {
  36                 /* Figure out which areas occupied by ram. */
  37                 int i, idx;
  38                 uint32_t memstart1, memstart2, extmemstart1, extmemstart2;
  39                 uint32_t memend1, memend2, extmemend1, extmemend2;
  40                 uint8_t bank_enable;
  41                 unsigned long start, end, size;
  42
  43                 /* Find the memory setup */
  44                 memstart1    = pci_read_config32(dev, 0x80);
  45                 memstart2    = pci_read_config32(dev, 0x84);
  46                 extmemstart1 = pci_read_config32(dev, 0x88);
  47                 extmemstart1 = pci_read_config32(dev, 0x8c);
  48                 memend1      = pci_read_config32(dev, 0x90);
  49                 memend2      = pci_read_config32(dev, 0x94);
  50                 extmemend1   = pci_read_config32(dev, 0x98);
  51                 extmemend2   = pci_read_config32(dev, 0x9c);
  52                 bank_enable  = pci_read_config32(dev, 0xa0);
  53
  54                 /* Report the memory regions */
  55                 idx = 10;
  56                 for(i = 0; i < 8; i++) {
  57                         struct resource *res;
  58                         /* Ignore banks that are not enabled */
  59                         if (!(bank_enable & (1 << i))) {
  60                                 continue;
  61                         }
  62                         /* Find the start and end of each bank */
  63                         if (i < 4) {
  64                                 int shift = (8*i);
  65                                 start =  ((memstart1    >> shift) & 0xff) << 20;
  66                                 start |= ((extmemstart1 >> shift) & 0xff) << 28;
  67                                 end   =  ((memend1      >> shift) & 0xff) << 20;
  68                                 end   |= ((extmemend1   >> shift) & 0xff) << 28;
  69                         } else {
  70                                 int shift = (8*(i - 4));
  71                                 start =  ((memstart2    >> shift) & 0xff) << 20;
  72                                 start |= ((extmemstart2 >> shift) & 0xff) << 28;
  73                                 end   =  ((memend2      >> shift) & 0xff) << 20;
  74                                 end   |= ((extmemend2   >> shift) & 0xff) << 28;
  75                         }
  76                         /* Comput the size of the bank */
  77                         size = (end + (1 << 20)) - start;
  78
  79                         /* And now report the memory region */
  80                         res = new_resource(dev, idx++);
  81                         res->base = start;
  82                         res->size = size;
  83                         res->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
  84                                 IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
  85                 }
  86         }
  87         /* And assign the resources */
  88         assign_resources(&dev->link[0]);
  89 }
  90
  91
  92 static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
  93 {
  94         max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
  95         return max;
  96 }
  97
  98 static struct device_operations pci_domain_ops = {
  99         .read_resources   = pci_domain_read_resources,
 100         .set_resources    = pci_domain_set_resources,
 101         .enable_resources = enable_childrens_resources,
 102         .init             = 0,
 103         .scan_bus         = pci_domain_scan_bus,
 104         .ops_pci_bus      = &pci_ppc_conf1,
 105 };
 106
 107 static void cpu_bus_init(device_t dev)
 108 {
 109         initialize_cpus(&dev->link[0]);
 110 }
 111
 112 static void cpu_bus_noop(device_t dev)
 113 {
 114 }
 115
 116 static struct device_operations cpu_bus_ops = {
 117         .read_resources   = cpu_bus_noop,
 118         .set_resources    = cpu_bus_noop,
 119         .enable_resources = cpu_bus_noop,
 120         .init             = cpu_bus_init,
 121         .scan_bus         = 0,
 122 };
 123
 124 static void enable_dev(struct device *dev)
 125 {
 126         /* Set the operations if it is a special bus type */
 127         if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
 128                 dev->ops = &pci_domain_ops;
 129         }
 130         else if (dev->path.type == DEVICE_PATH_CPU_BUS) {
 131                 dev->ops = &cpu_bus_ops;
 132         }
 133 }
 134
 135 struct chip_operations northbridge_motorola_mpc107_ops = {
 136         CHIP_NAME("MPC107")
 137         .enable_dev = enable_dev,
 138 };