2 * This file is part of the coreboot project.
4 * Copyright (C) 2007-2008 coresystems GmbH
5 * Copyright (C) 2009-2010 iWave Systems
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; version 2 of
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 #ifndef __SCH_PULSBO_H__
23 #define __SCH_PULSBO_H__ 1
25 int sch_port_access_read(int port, int reg, int bytes);
26 void sch_port_access_write(int port, int reg, int bytes, long data);
27 void sch_port_access_write_ram_cmd(int cmd, int port, int reg, int data);
29 /* Southbridge IO BARs */
30 /* TODO Make sure these don't get changed by stage2 */
31 #define SCH_ENABLE_BIT (1<<31)
32 #define DEFAULT_ACPIPBLKBASE 0x510
34 #define DEFAULT_SMBUSBASE 0x540
35 #define DEFAULT_GPIOBASE 0x588
36 #define DEFAULT_GPE0BASE 0x5C0
37 #define DEFAULT_SMMCNTRLBASE 0x3F703F76
39 #define DEFAULT_RCBABASE 0xfed1c000
41 #define DEFAULT_PCIEXBAR 0xe0000000 /* 4 KB per PCIe device */
46 /* Root Complex Register Block */
47 #define RCBA8(x) *((volatile u8 *)(DEFAULT_RCBABASE + x))
48 #define RCBA16(x) *((volatile u16 *)(DEFAULT_RCBABASE + x))
49 #define RCBA32(x) *((volatile u32 *)(DEFAULT_RCBABASE + x))
51 /* FIXME: should probably be in southbridge, but is setup in romstage, too */
52 #define CMC_SHADOW 0x3faf0000