src/northbridge/intel/i945/raminit.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007-2009 coresystems GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18  */
  19
  20 #include <cpu/x86/mem.h>
  21 #include <cpu/x86/mtrr.h>
  22 #include <cpu/x86/cache.h>
  23 #include <spd.h>
  24 #include "raminit.h"
  25 #include "i945.h"
  26
  27 #define DEBUG_RAM_SETUP
  28
  29 /* Debugging macros. */
  30 #if defined(DEBUG_RAM_SETUP)
  31 #define PRINTK_DEBUG(x...)      printk_debug(x)
  32 #else
  33 #define PRINTK_DEBUG(x...)
  34 #endif
  35
  36 #define RAM_INITIALIZATION_COMPLETE     (1 << 19)
  37
  38 #define RAM_COMMAND_SELF_REFRESH        (0x0 << 16)
  39 #define RAM_COMMAND_NOP                 (0x1 << 16)
  40 #define RAM_COMMAND_PRECHARGE           (0x2 << 16)
  41 #define RAM_COMMAND_MRS                 (0x3 << 16)
  42 #define RAM_COMMAND_EMRS                (0x4 << 16)
  43 #define RAM_COMMAND_CBR                 (0x6 << 16)
  44 #define RAM_COMMAND_NORMAL              (0x7 << 16)
  45
  46 #define RAM_EMRS_1                      (0x0 << 21)
  47 #define RAM_EMRS_2                      (0x1 << 21)
  48 #define RAM_EMRS_3                      (0x2 << 21)
  49
  50 static void do_ram_command(u32 command)
  51 {
  52         u32 reg32;
  53
  54         reg32 = MCHBAR32(DCC);
  55         reg32 &= ~( (3<<21) | (1<<20) | (1<<19) | (7 << 16) );
  56         reg32 |= command;
  57
  58         /* Also set Init Complete */
  59         if (command == RAM_COMMAND_NORMAL)
  60                 reg32 |= RAM_INITIALIZATION_COMPLETE;
  61
  62         PRINTK_DEBUG("   Sending RAM command 0x%08x", reg32);
  63
  64         MCHBAR32(DCC) = reg32;  /* This is the actual magic */
  65
  66         PRINTK_DEBUG("...done\n");
  67 }
  68
  69 static void ram_read32(u32 offset)
  70 {
  71         PRINTK_DEBUG("   ram read: %08x\n", offset);
  72
  73         read32(offset);
  74 }
  75
  76 #ifdef DEBUG_RAM_SETUP
  77 static void sdram_dump_mchbar_registers(void)
  78 {
  79         int i;
  80         printk_debug("Dumping MCHBAR Registers\n");
  81
  82         for (i=0; i<0xfff; i+=4) {
  83                 if (MCHBAR32(i) == 0)
  84                         continue;
  85                 printk_debug("0x%04x: 0x%08x\n", i, MCHBAR32(i));
  86         }
  87 }
  88 #endif
  89
  90 static int sdram_capabilities_max_supported_memory_frequency(void)
  91 {
  92         u32 reg32;
  93
  94 #ifdef MAXIMUM_SUPPORTED_FREQUENCY
  95         return MAXIMUM_SUPPORTED_FREQUENCY;
  96 #endif
  97
  98         reg32 = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xe4);
  99         reg32 &= (7 << 0);
 100
 101         switch (reg32) {
 102         case 4: return 400;
 103         case 3: return 533;
 104         case 2: return 667;
 105         }
 106         /* Newer revisions of this chipset rather support faster memory clocks,
 107          * so if it's a reserved value, return the fastest memory clock that we
 108          * know of and can handle
 109          */
 110         return 667;
 111 }
 112
 113 /**
 114  * @brief determine whether chipset is capable of dual channel interleaved mode
 115  *
 116  * @return 1 if interleaving is supported, 0 otherwise
 117  */
 118 static int sdram_capabilities_interleave(void)
 119 {
 120         u32 reg32;
 121
 122         reg32 = pci_read_config8(PCI_DEV(0, 0x00,0), 0xe4);
 123         reg32 >>= 25;
 124         reg32 &= 1;
 125
 126         return (!reg32);
 127 }
 128
 129 /**
 130  * @brief determine whether chipset is capable of two memory channels
 131  *
 132  * @return 1 if dual channel operation is supported, 0 otherwise
 133  */
 134 static int sdram_capabilities_dual_channel(void)
 135 {
 136         u32 reg32;
 137
 138         reg32 = pci_read_config8(PCI_DEV(0, 0x00,0), 0xe4);
 139         reg32 >>= 24;
 140         reg32 &= 1;
 141
 142         return (!reg32);
 143 }
 144
 145 static int sdram_capabilities_enhanced_addressing_xor(void)
 146 {
 147         u8 reg8;
 148
 149         reg8 = pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe5); /* CAPID0 + 5 */
 150         reg8 &= (1 << 7);
 151
 152         return (!reg8);
 153 }
 154
 155 static int sdram_capabilities_two_dimms_per_channel(void)
 156 {
 157         u8 reg8;
 158
 159         reg8 = pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe8); /* CAPID0 + 8 */
 160         reg8 &= (1 << 0);
 161
 162         return (reg8 != 0);
 163 }
 164
 165 static int sdram_capabilities_MEM4G_disable(void)
 166 {
 167         u8 reg8;
 168
 169         reg8 = pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe5);
 170         reg8 &= (1 << 0);
 171
 172         return (reg8 != 0);
 173 }
 174
 175 #define GFX_FREQUENCY_CAP_166MHZ        0x04
 176 #define GFX_FREQUENCY_CAP_200MHZ        0x03
 177 #define GFX_FREQUENCY_CAP_250MHZ        0x02
 178 #define GFX_FREQUENCY_CAP_ALL           0x00
 179
 180 static int sdram_capabilities_core_frequencies(void)
 181 {
 182         u8 reg8;
 183
 184         reg8 = pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe5); /* CAPID0 + 5 */
 185         reg8 &= (1 << 3) | (1 << 2) | (1 << 1);
 186         reg8 >>= 1;
 187
 188         return (reg8);
 189 }
 190
 191 static void sdram_detect_errors(void)
 192 {
 193         u8 reg8;
 194         u8 do_reset = 0;
 195
 196         reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2);
 197
 198         if (reg8 & ((1<<7)|(1<<2))) {
 199                 if (reg8 & (1<<2)) {
 200                         printk_debug("SLP S4# Assertion Width Violation.\n");
 201
 202                         pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8);
 203
 204                 }
 205
 206                 if (reg8 & (1<<7)) {
 207                         printk_debug("DRAM initialization was interrupted.\n");
 208                         reg8 &= ~(1<<7);
 209                         pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8);
 210                         do_reset = 1;
 211                 }
 212
 213                 /* Set SLP_S3# Assertion Stretch Enable */
 214                 reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); /* GEN_PMCON_3 */
 215                 reg8 |= (1 << 3);
 216                 pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8);
 217
 218                 if (do_reset) {
 219                         printk_debug("Reset required.\n");
 220                         outb(0x00, 0xcf9);
 221                         outb(0x0e, 0xcf9);
 222                         for (;;) ; /* Wait for reset! */
 223                 }
 224         }
 225
 226         /* Set DRAM initialization bit in ICH7 */
 227         reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2);
 228         reg8 |= (1<<7);
 229         pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8);
 230
 231 }
 232
 233 /**
 234  * @brief Get generic DIMM parameters.
 235  * @param sysinfo Central memory controller information structure
 236  *
 237  * This function gathers several pieces of information for each system DIMM:
 238  *  o DIMM width (x8 / x16)
 239  *  o DIMM sides (single sided / dual sided)
 240  *
 241  *  Also, some non-supported scenarios are detected.
 242  */
 243
 244 static void sdram_get_dram_configuration(struct sys_info *sysinfo)
 245 {
 246         u32 dimm_mask = 0;
 247         int i;
 248
 249         /**
 250          * i945 supports two DIMMs, in two configurations:
 251          *
 252          * - single channel with two dimms
 253          * - dual channel with one dimm per channel
 254          *
 255          * In practice dual channel mainboards have their spd at 0x50, 0x52
 256          * whereas single channel configurations have their spd at 0x50/x51
 257          *
 258          * The capability register knows a lot about the channel configuration
 259          * but for now we stick with the information we gather from the SPD
 260          * ROMs
 261          */
 262
 263         if (sdram_capabilities_dual_channel()) {
 264                 sysinfo->dual_channel = 1;
 265                 printk_debug("This mainboard supports Dual Channel Operation.\n");
 266         } else {
 267                 sysinfo->dual_channel = 0;
 268                 printk_debug("This mainboard supports only Single Channel Operation.\n");
 269         }
 270
 271         /**
 272          * Since we only support two DIMMs in total, there is a limited number
 273          * of combinations. This function returns the type of DIMMs.
 274          * return value:
 275          *   [0:7]  lower DIMM population
 276          *   [8-15] higher DIMM population
 277          *   [16]   dual channel?
 278          *
 279          * There are 5 different possible populations for a DIMM socket:
 280          * 1. x16 double sided (X16DS)
 281          * 2. x8 double sided  (X8DS)
 282          * 3. x16 single sided (X16SS)
 283          * 4. x8 double stacked (X8DDS)
 284          * 5. not populated (NC)
 285          *
 286          * For the return value we start counting at zero.
 287          *
 288          */
 289
 290         for (i=0; i<(2 * DIMM_SOCKETS); i++) {
 291                 u8 reg8, device = DIMM_SPD_BASE + i;
 292
 293                 /* Initialize the socket information with a sane value */
 294                 sysinfo->dimm[i] = SYSINFO_DIMM_NOT_POPULATED;
 295
 296                 /* Dual Channel not supported, but Channel 1? Bail out */
 297                 if (!sdram_capabilities_dual_channel() && (i >> 1))
 298                         continue;
 299
 300                 /* Two DIMMs per channel not supported, but odd DIMM number? */
 301                 if (!sdram_capabilities_two_dimms_per_channel() && (i& 1))
 302                         continue;
 303
 304                 printk_debug("DDR II Channel %d Socket %d: ", (i >> 1), (i & 1));
 305
 306                 if (spd_read_byte(device, SPD_MEMORY_TYPE) != SPD_MEMORY_TYPE_SDRAM_DDR2) {
 307                         printk_debug("N/A\n");
 308                         continue;
 309                 }
 310
 311                 reg8 = spd_read_byte(device, SPD_DIMM_CONFIG_TYPE);
 312                 if (reg8 == ERROR_SCHEME_ECC)
 313                         die("Error: ECC memory not supported by this chipset\n");
 314
 315                 reg8 = spd_read_byte(device, SPD_MODULE_ATTRIBUTES);
 316                 if (reg8 & MODULE_BUFFERED)
 317                         die("Error: Buffered memory not supported by this chipset\n");
 318                 if (reg8 & MODULE_REGISTERED)
 319                         die("Error: Registered memory not supported by this chipset\n");
 320
 321                 switch (spd_read_byte(device, SPD_PRIMARY_SDRAM_WIDTH)) {
 322                 case 0x08:
 323                         switch (spd_read_byte(device, SPD_NUM_DIMM_BANKS) & 0x0f) {
 324                         case 1:
 325                                 printk_debug("x8DDS\n");
 326                                 sysinfo->dimm[i] = SYSINFO_DIMM_X8DDS;
 327                                 break;
 328                         case 0:
 329                                 printk_debug("x8DS\n");
 330                                 sysinfo->dimm[i] = SYSINFO_DIMM_X8DS;
 331                                 break;
 332                         default:
 333                                 printk_debug ("Unsupported.\n");
 334                         }
 335                         break;
 336                 case 0x10:
 337                         switch (spd_read_byte(device, SPD_NUM_DIMM_BANKS) & 0x0f) {
 338                         case 1:
 339                                 printk_debug("x16DS\n");
 340                                 sysinfo->dimm[i] = SYSINFO_DIMM_X16DS;
 341                                 break;
 342                         case 0:
 343                                 printk_debug("x16SS\n");
 344                                 sysinfo->dimm[i] = SYSINFO_DIMM_X16SS;
 345                                 break;
 346                         default:
 347                                 printk_debug ("Unsupported.\n");
 348                         }
 349                         break;
 350                 default:
 351                         die("Unsupported DDR-II memory width.\n");
 352                 }
 353
 354                 dimm_mask |= (1 << i);
 355         }
 356
 357         if (!dimm_mask) {
 358                 die("No memory installed.\n");
 359         }
 360
 361         /* The chipset might be able to do this. What the heck, legacy bios
 362          * just beeps when a single DIMM is in the Channel 1 socket. So let's
 363          * not bother until someone needs this enough to cope with it.
 364          */
 365         if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) {
 366                 printk_err("Channel 0 has no memory populated. This setup is not usable. Please move the DIMM.\n");
 367         }
 368 }
 369
 370 /**
 371  * @brief determine if any DIMMs are stacked
 372  *
 373  * @param sysinfo central sysinfo data structure.
 374  */
 375 static void sdram_verify_package_type(struct sys_info * sysinfo)
 376 {
 377         int i;
 378
 379         /* Assume no stacked DIMMs are available until we find one */
 380         sysinfo->package = 0;
 381         for (i=0; i<2*DIMM_SOCKETS; i++) {
 382                 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
 383                         continue;
 384
 385                 /* Is the current DIMM a stacked DIMM? */
 386                 if (spd_read_byte(DIMM_SPD_BASE + i, SPD_NUM_DIMM_BANKS) & (1 << 4))
 387                         sysinfo->package = 1;
 388         }
 389 }
 390
 391 static u8 sdram_possible_cas_latencies(struct sys_info * sysinfo)
 392 {
 393         int i;
 394         u8 cas_mask;
 395
 396         /* Setup CAS mask with all supported CAS Latencies */
 397         cas_mask = SPD_CAS_LATENCY_DDR2_3 |
 398                    SPD_CAS_LATENCY_DDR2_4 |
 399                    SPD_CAS_LATENCY_DDR2_5;
 400
 401         for (i=0; i<2*DIMM_SOCKETS; i++) {
 402                 if (sysinfo->dimm[i] != SYSINFO_DIMM_NOT_POPULATED)
 403                         cas_mask &= spd_read_byte(DIMM_SPD_BASE + i, SPD_ACCEPTABLE_CAS_LATENCIES);
 404         }
 405
 406         if(!cas_mask) {
 407                 die("No DDR-II modules with accepted CAS latencies found.\n");
 408         }
 409
 410         return cas_mask;
 411 }
 412
 413 static void sdram_detect_cas_latency_and_ram_speed(struct sys_info * sysinfo, u8 cas_mask)
 414 {
 415         int i, j, idx;
 416         int lowest_common_cas = 0;
 417         int max_ram_speed;
 418
 419         const u8 ddr2_speeds_table[] = {
 420                 0x50, 0x60,     /* DDR2 400: tCLK = 5.0ns  tAC = 0.6ns  */
 421                 0x3d, 0x50,     /* DDR2 533: tCLK = 3.75ns tAC = 0.5ns  */
 422                 0x30, 0x45,     /* DDR2 667: tCLK = 3.0ns  tAC = 0.45ns */
 423         };
 424
 425         const u8 spd_lookup_table[] = {
 426                 SPD_MIN_CYCLE_TIME_AT_CAS_MAX,  SPD_ACCESS_TIME_FROM_CLOCK,
 427                 SPD_SDRAM_CYCLE_TIME_2ND,       SPD_ACCESS_TIME_FROM_CLOCK_2ND,
 428                 SPD_SDRAM_CYCLE_TIME_3RD,       SPD_ACCESS_TIME_FROM_CLOCK_3RD
 429         };
 430
 431         switch (sdram_capabilities_max_supported_memory_frequency()) {
 432         case 400: max_ram_speed = 0; break;
 433         case 533: max_ram_speed = 1; break;
 434         case 667: max_ram_speed = 2; break;
 435         }
 436
 437         sysinfo->memory_frequency = 0;
 438         sysinfo->cas = 0;
 439
 440         if (cas_mask & SPD_CAS_LATENCY_DDR2_3) {
 441                 lowest_common_cas = 3;
 442         } else if (cas_mask & SPD_CAS_LATENCY_DDR2_4) {
 443                 lowest_common_cas = 4;
 444         } else if (cas_mask & SPD_CAS_LATENCY_DDR2_5) {
 445                 lowest_common_cas = 5;
 446         }
 447         PRINTK_DEBUG("lowest common cas = %d\n", lowest_common_cas);
 448
 449         for (j = max_ram_speed; j>=0; j--) {
 450                 int freq_cas_mask = cas_mask;
 451
 452                 PRINTK_DEBUG("Probing Speed %d\n", j);
 453                 for (i=0; i<2*DIMM_SOCKETS; i++) {
 454                         int current_cas_mask;
 455
 456                         PRINTK_DEBUG("  DIMM: %d\n", i);
 457                         if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) {
 458                                 continue;
 459                         }
 460
 461                         current_cas_mask = spd_read_byte(DIMM_SPD_BASE + i, SPD_ACCEPTABLE_CAS_LATENCIES);
 462
 463                         while (current_cas_mask) {
 464                                 int highest_supported_cas = 0, current_cas = 0;
 465                                 PRINTK_DEBUG("    Current CAS mask: %04x; ", current_cas_mask);
 466                                 if (current_cas_mask & SPD_CAS_LATENCY_DDR2_5) {
 467                                         highest_supported_cas = 5;
 468                                 } else if (current_cas_mask & SPD_CAS_LATENCY_DDR2_4) {
 469                                         highest_supported_cas = 4;
 470                                 } else if (current_cas_mask & SPD_CAS_LATENCY_DDR2_3) {
 471                                         highest_supported_cas = 3;
 472                                 }
 473                                 if (current_cas_mask & SPD_CAS_LATENCY_DDR2_3) {
 474                                         current_cas = 3;
 475                                 } else if (current_cas_mask & SPD_CAS_LATENCY_DDR2_4) {
 476                                         current_cas = 4;
 477                                 } else if (current_cas_mask & SPD_CAS_LATENCY_DDR2_5) {
 478                                         current_cas = 5;
 479                                 }
 480
 481                                 idx = highest_supported_cas - current_cas;
 482                                 PRINTK_DEBUG("idx=%d, ", idx);
 483                                 PRINTK_DEBUG("tCLK=%x, ", spd_read_byte(DIMM_SPD_BASE + i, spd_lookup_table[2*idx]));
 484                                 PRINTK_DEBUG("tAC=%x", spd_read_byte(DIMM_SPD_BASE + i, spd_lookup_table[(2*idx)+1]));
 485
 486                                 if (spd_read_byte(DIMM_SPD_BASE + i, spd_lookup_table[2*idx]) <= ddr2_speeds_table[2*j] &&
 487                                                 spd_read_byte(DIMM_SPD_BASE + i, spd_lookup_table[(2*idx)+1]) <= ddr2_speeds_table[(2*j)+1]) {
 488                                         PRINTK_DEBUG(":    OK\n");
 489                                         break;
 490                                 }
 491
 492                                 PRINTK_DEBUG(":    Not fast enough!\n");
 493
 494                                 current_cas_mask &= ~(1 << (current_cas));
 495                         }
 496
 497                         freq_cas_mask &= current_cas_mask;
 498                         if (!current_cas_mask) {
 499                                 PRINTK_DEBUG("    No valid CAS for this speed on DIMM %d\n", i);
 500                                 break;
 501                         }
 502                 }
 503                 PRINTK_DEBUG("  freq_cas_mask for speed %d: %04x\n", j, freq_cas_mask);
 504                 if (freq_cas_mask) {
 505                         switch (j) {
 506                         case 0: sysinfo->memory_frequency = 400; break;
 507                         case 1: sysinfo->memory_frequency = 533; break;
 508                         case 2: sysinfo->memory_frequency = 667; break;
 509                         }
 510                         if (freq_cas_mask & SPD_CAS_LATENCY_DDR2_3) {
 511                                 sysinfo->cas = 3;
 512                         } else if (freq_cas_mask & SPD_CAS_LATENCY_DDR2_4) {
 513                                 sysinfo->cas = 4;
 514                         } else if (freq_cas_mask & SPD_CAS_LATENCY_DDR2_5) {
 515                                 sysinfo->cas = 5;
 516                         }
 517                         break;
 518                 }
 519         }
 520
 521         if (sysinfo->memory_frequency && sysinfo->cas) {
 522                 printk_debug("Memory will be driven at %dMHz with CAS=%d clocks\n",
 523                                 sysinfo->memory_frequency, sysinfo->cas);
 524         } else {
 525                 die("Could not find common memory frequency and CAS\n");
 526         }
 527 }
 528
 529 static void sdram_detect_smallest_tRAS(struct sys_info * sysinfo)
 530 {
 531         int i;
 532         int tRAS_time;
 533         int tRAS_cycles;
 534         int freq_multiplier = 0;
 535
 536         switch (sysinfo->memory_frequency) {
 537         case 400: freq_multiplier = 0x14; break; /* 5ns */
 538         case 533: freq_multiplier = 0x0f; break; /* 3.75ns */
 539         case 667: freq_multiplier = 0x0c; break; /* 3ns */
 540         }
 541
 542         tRAS_cycles = 4; /* 4 clocks minimum */
 543         tRAS_time = tRAS_cycles * freq_multiplier;
 544
 545         for (i=0; i<2*DIMM_SOCKETS; i++) {
 546                 u8 reg8;
 547
 548                 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
 549                         continue;
 550
 551                 reg8 = spd_read_byte(DIMM_SPD_BASE + i, SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY);
 552                 if (!reg8) {
 553                         die("Invalid tRAS value.\n");
 554                 }
 555
 556                 while ((tRAS_time >> 2) < reg8) {
 557                         tRAS_time += freq_multiplier;
 558                         tRAS_cycles++;
 559                 }
 560         }
 561         if(tRAS_cycles > 0x18) {
 562                 die("DDR-II Module does not support this frequency (tRAS error)\n");
 563         }
 564
 565         printk_debug("tRAS = %d cycles\n", tRAS_cycles);
 566         sysinfo->tras = tRAS_cycles;
 567 }
 568
 569 static void sdram_detect_smallest_tRP(struct sys_info * sysinfo)
 570 {
 571         int i;
 572         int tRP_time;
 573         int tRP_cycles;
 574         int freq_multiplier = 0;
 575
 576         switch (sysinfo->memory_frequency) {
 577         case 400: freq_multiplier = 0x14; break; /* 5ns */
 578         case 533: freq_multiplier = 0x0f; break; /* 3.75ns */
 579         case 667: freq_multiplier = 0x0c; break; /* 3ns */
 580         }
 581
 582         tRP_cycles = 2; /* 2 clocks minimum */
 583         tRP_time = tRP_cycles * freq_multiplier;
 584
 585         for (i=0; i<2*DIMM_SOCKETS; i++) {
 586                 u8 reg8;
 587
 588                 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
 589                         continue;
 590
 591                 reg8 = spd_read_byte(DIMM_SPD_BASE + i, SPD_MIN_ROW_PRECHARGE_TIME);
 592                 if (!reg8) {
 593                         die("Invalid tRP value.\n");
 594                 }
 595
 596                 while (tRP_time < reg8) {
 597                         tRP_time += freq_multiplier;
 598                         tRP_cycles++;
 599                 }
 600         }
 601
 602         if(tRP_cycles > 6) {
 603                 die("DDR-II Module does not support this frequency (tRP error)\n");
 604         }
 605
 606         printk_debug("tRP = %d cycles\n", tRP_cycles);
 607         sysinfo->trp = tRP_cycles;
 608 }
 609
 610 static void sdram_detect_smallest_tRCD(struct sys_info * sysinfo)
 611 {
 612         int i;
 613         int tRCD_time;
 614         int tRCD_cycles;
 615         int freq_multiplier = 0;
 616
 617         switch (sysinfo->memory_frequency) {
 618         case 400: freq_multiplier = 0x14; break; /* 5ns */
 619         case 533: freq_multiplier = 0x0f; break; /* 3.75ns */
 620         case 667: freq_multiplier = 0x0c; break; /* 3ns */
 621         }
 622
 623         tRCD_cycles = 2; /* 2 clocks minimum */
 624         tRCD_time = tRCD_cycles * freq_multiplier;
 625
 626         for (i=0; i<2*DIMM_SOCKETS; i++) {
 627                 u8 reg8;
 628
 629                 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
 630                         continue;
 631
 632                 reg8 = spd_read_byte(DIMM_SPD_BASE + i, SPD_MIN_RAS_TO_CAS_DELAY);
 633                 if (!reg8) {
 634                         die("Invalid tRCD value.\n");
 635                 }
 636
 637                 while (tRCD_time < reg8) {
 638                         tRCD_time += freq_multiplier;
 639                         tRCD_cycles++;
 640                 }
 641         }
 642         if(tRCD_cycles > 6) {
 643                 die("DDR-II Module does not support this frequency (tRCD error)\n");
 644         }
 645
 646         printk_debug("tRCD = %d cycles\n", tRCD_cycles);
 647         sysinfo->trcd = tRCD_cycles;
 648 }
 649
 650 static void sdram_detect_smallest_tWR(struct sys_info * sysinfo)
 651 {
 652         int i;
 653         int tWR_time;
 654         int tWR_cycles;
 655         int freq_multiplier = 0;
 656
 657         switch (sysinfo->memory_frequency) {
 658         case 400: freq_multiplier = 0x14; break; /* 5ns */
 659         case 533: freq_multiplier = 0x0f; break; /* 3.75ns */
 660         case 667: freq_multiplier = 0x0c; break; /* 3ns */
 661         }
 662
 663         tWR_cycles = 2; /* 2 clocks minimum */
 664         tWR_time = tWR_cycles * freq_multiplier;
 665
 666         for (i=0; i<2*DIMM_SOCKETS; i++) {
 667                 u8 reg8;
 668
 669                 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
 670                         continue;
 671
 672                 reg8 = spd_read_byte(DIMM_SPD_BASE + i, SPD_WRITE_RECOVERY_TIME);
 673                 if (!reg8) {
 674                         die("Invalid tWR value.\n");
 675                 }
 676
 677                 while (tWR_time < reg8) {
 678                         tWR_time += freq_multiplier;
 679                         tWR_cycles++;
 680                 }
 681         }
 682         if(tWR_cycles > 5) {
 683                 die("DDR-II Module does not support this frequency (tWR error)\n");
 684         }
 685
 686         printk_debug("tWR = %d cycles\n", tWR_cycles);
 687         sysinfo->twr = tWR_cycles;
 688 }
 689
 690 static void sdram_detect_smallest_tRFC(struct sys_info * sysinfo)
 691 {
 692         int i, index = 0;
 693
 694         const u8 tRFC_cycles[] = {
 695              /* 75 105 127.5 */
 696                 15, 21, 26,     /* DDR2-400 */
 697                 20, 28, 34,     /* DDR2-533 */
 698                 25, 35, 43      /* DDR2-667 */
 699         };
 700
 701         for (i=0; i<2*DIMM_SOCKETS; i++) {
 702                 u8 reg8;
 703
 704                 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
 705                         continue;
 706
 707                 reg8 = sysinfo->banksize[i*2];
 708                 switch (reg8) {
 709                 case 0x04: reg8 = 0; break;
 710                 case 0x08: reg8 = 1; break;
 711                 case 0x10: reg8 = 2; break;
 712                 case 0x20: reg8 = 3; break;
 713                 }
 714
 715                 if (sysinfo->dimm[i] == SYSINFO_DIMM_X16DS || sysinfo->dimm[i] == SYSINFO_DIMM_X16SS)
 716                         reg8++;
 717
 718                 if (reg8 > 3) {
 719                         /* Can this happen? Go back to 127.5ns just to be sure
 720                          * we don't run out of the array. This may be wrong
 721                          */
 722                         printk_debug("DIMM %d is 1Gb x16.. Please report.\n", i);
 723                         reg8 = 3;
 724                 }
 725
 726                 if (reg8 > index)
 727                         index = reg8;
 728
 729         }
 730         index--;
 731         switch (sysinfo->memory_frequency) {
 732         case 667: index += 3; /* Fallthrough */
 733         case 533: index += 3; /* Fallthrough */
 734         case 400: break;
 735         }
 736
 737         sysinfo->trfc = tRFC_cycles[index];
 738         printk_debug("tRFC = %d cycles\n", tRFC_cycles[index]);
 739 }
 740
 741 static void sdram_detect_smallest_refresh(struct sys_info * sysinfo)
 742 {
 743         int i;
 744
 745         sysinfo->refresh = 0;
 746
 747         for (i=0; i<2*DIMM_SOCKETS; i++) {
 748                 int refresh;
 749
 750                 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
 751                         continue;
 752
 753                 refresh = spd_read_byte(DIMM_SPD_BASE + i, SPD_REFRESH) & ~(1 << 7);
 754
 755                 /* 15.6us */
 756                 if (!refresh)
 757                         continue;
 758
 759                 /* Refresh is slower than 15.6us, use 15.6us */
 760                 if (refresh > 2)
 761                         continue;
 762
 763                 if (refresh == 2) {
 764                         sysinfo->refresh = 1;
 765                         break;
 766                 }
 767
 768                 die("DDR-II module has unsupported refresh value\n");
 769         }
 770         printk_debug("Refresh: %s\n", sysinfo->refresh?"7.8us":"15.6us");
 771 }
 772
 773 static void sdram_verify_burst_length(struct sys_info * sysinfo)
 774 {
 775         int i;
 776
 777         for (i=0; i<2*DIMM_SOCKETS; i++) {
 778                 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
 779                         continue;
 780
 781                 if (!(spd_read_byte(DIMM_SPD_BASE + i, SPD_SUPPORTED_BURST_LENGTHS) & SPD_BURST_LENGTH_8))
 782                         die("Only DDR-II RAM with burst length 8 is supported by this chipset.\n");
 783         }
 784 }
 785
 786 static void sdram_program_dram_width(struct sys_info * sysinfo)
 787 {
 788         u16 c0dramw=0, c1dramw=0;
 789         int idx;
 790
 791         if (sysinfo->dual_channel)
 792                 idx = 2;
 793         else
 794                 idx = 1;
 795
 796         switch (sysinfo->dimm[0]) {
 797         case 0: c0dramw = 0x0000; break; /* x16DS */
 798         case 1: c0dramw = 0x0001; break; /* x8DS */
 799         case 2: c0dramw = 0x0000; break; /* x16SS */
 800         case 3: c0dramw = 0x0005; break; /* x8DDS */
 801         case 4: c0dramw = 0x0000; break; /* NC */
 802         }
 803
 804         switch (sysinfo->dimm[idx]) {
 805         case 0: c1dramw = 0x0000; break; /* x16DS */
 806         case 1: c1dramw = 0x0010; break; /* x8DS */
 807         case 2: c1dramw = 0x0000; break; /* x16SS */
 808         case 3: c1dramw = 0x0050; break; /* x8DDS */
 809         case 4: c1dramw = 0x0000; break; /* NC */
 810         }
 811
 812         if ( !sdram_capabilities_dual_channel() ) {
 813                 /* Single Channel */
 814                 c0dramw |= c1dramw;
 815                 c1dramw = 0;
 816         }
 817
 818         MCHBAR16(C0DRAMW) = c0dramw;
 819         MCHBAR16(C1DRAMW) = c1dramw;
 820 }
 821
 822 static void sdram_write_slew_rates(u32 offset, const u32 *slew_rate_table)
 823 {
 824         int i;
 825
 826         for (i=0; i<16; i++)
 827                 MCHBAR32(offset+(i*4)) = slew_rate_table[i];
 828 }
 829
 830 static void sdram_rcomp_buffer_strength_and_slew(struct sys_info *sysinfo)
 831 {
 832         static const u32 dq2030[] = {
 833                 0x08070706, 0x0a090908, 0x0d0c0b0a, 0x12100f0e,
 834                 0x1a181614, 0x22201e1c, 0x2a282624, 0x3934302d,
 835                 0x0a090908, 0x0c0b0b0a, 0x0e0d0d0c, 0x1211100f,
 836                 0x19171513, 0x211f1d1b, 0x2d292623, 0x3f393531
 837         };
 838
 839         static const u32 dq2330[] = {
 840                 0x08070706, 0x0a090908, 0x0d0c0b0a, 0x12100f0e,
 841                 0x1a181614, 0x22201e1c, 0x2a282624, 0x3934302d,
 842                 0x0a090908, 0x0c0b0b0a, 0x0e0d0d0c, 0x1211100f,
 843                 0x19171513, 0x211f1d1b, 0x2d292623, 0x3f393531
 844         };
 845
 846         static const u32 cmd2710[] = {
 847                 0x07060605, 0x0f0d0b09, 0x19171411, 0x1f1f1d1b,
 848                 0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f,
 849                 0x1110100f, 0x0f0d0b09, 0x19171411, 0x1f1f1d1b,
 850                 0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f
 851         };
 852
 853         static const u32 cmd3210[] = {
 854                 0x0f0d0b0a, 0x17151311, 0x1f1d1b19, 0x1f1f1f1f,
 855                 0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f,
 856                 0x18171615, 0x1f1f1c1a, 0x1f1f1f1f, 0x1f1f1f1f,
 857                 0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f
 858         };
 859
 860         static const u32 clk2030[] = {
 861                 0x0e0d0d0c, 0x100f0f0e, 0x100f0e0d, 0x15131211,
 862                 0x1d1b1917, 0x2523211f, 0x2a282927, 0x32302e2c,
 863                 0x17161514, 0x1b1a1918, 0x1f1e1d1c, 0x23222120,
 864                 0x27262524, 0x2d2b2928, 0x3533312f, 0x3d3b3937
 865         };
 866
 867         static const u32 ctl3215[] = {
 868                 0x01010000, 0x03020101, 0x07060504, 0x0b0a0908,
 869                 0x100f0e0d, 0x14131211, 0x18171615, 0x1c1b1a19,
 870                 0x05040403, 0x07060605, 0x0a090807, 0x0f0d0c0b,
 871                 0x14131211, 0x18171615, 0x1c1b1a19, 0x201f1e1d
 872         };
 873
 874         static const u32 ctl3220[] = {
 875                 0x05040403, 0x07060505, 0x0e0c0a08, 0x1a171411,
 876                 0x2825221f, 0x35322f2b, 0x3e3e3b38, 0x3e3e3e3e,
 877                 0x09080807, 0x0b0a0a09, 0x0f0d0c0b, 0x1b171311,
 878                 0x2825221f, 0x35322f2b, 0x3e3e3b38, 0x3e3e3e3e
 879         };
 880
 881         static const u32 nc[] = {
 882                 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 883                 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 884                 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 885                 0x00000000, 0x00000000, 0x00000000, 0x00000000
 886         };
 887
 888         static const u32 const * const dual_channel_slew_group_lookup[] = {
 889                 dq2030, cmd3210, ctl3215, ctl3215, clk2030, clk2030, dq2030, cmd3210,
 890                 dq2030, cmd3210, ctl3215, ctl3215, clk2030, clk2030, dq2030, cmd3210,
 891                 dq2030, cmd3210, nc,      ctl3215, nc,      clk2030, dq2030, cmd3210,
 892                 dq2030, cmd3210, ctl3215, ctl3215, clk2030, clk2030, dq2030, cmd2710,
 893                 dq2030, cmd3210, nc,      ctl3215, nc,      clk2030, nc,     nc,
 894
 895                 dq2030, cmd3210, ctl3215, ctl3215, clk2030, clk2030, dq2030, cmd3210,
 896                 dq2030, cmd3210, ctl3215, nc,      clk2030, nc,      dq2030, cmd3210,
 897                 dq2030, cmd3210, ctl3215, ctl3215, clk2030, clk2030, dq2030, cmd3210,
 898                 dq2030, cmd3210, ctl3215, nc,      clk2030, nc,      dq2030, cmd2710,
 899                 dq2030, cmd3210, ctl3215, nc,      clk2030, nc,      nc,     nc,
 900
 901                 dq2030, cmd3210, nc,      ctl3215, nc,      clk2030, dq2030, cmd3210,
 902                 dq2030, cmd3210, ctl3215, ctl3215, clk2030, clk2030, dq2030, cmd3210,
 903                 dq2030, cmd3210, nc,      ctl3215, nc,      clk2030, dq2030, cmd3210,
 904                 dq2030, cmd3210, ctl3215, ctl3215, clk2030, clk2030, dq2030, cmd2710,
 905                 dq2030, cmd3210, nc,      ctl3215, nc,      clk2030, nc,     nc,
 906
 907                 dq2030, cmd2710, ctl3215, ctl3215, clk2030, clk2030, dq2030, cmd3210,
 908                 dq2030, cmd2710, ctl3215, nc,      clk2030, nc,      dq2030, cmd3210,
 909                 dq2030, cmd2710, ctl3215, ctl3215, clk2030, clk2030, dq2030, cmd3210,
 910                 dq2030, cmd2710, ctl3215, nc,      clk2030, nc,      dq2030, cmd2710,
 911                 dq2030, cmd2710, ctl3215, nc,      clk2030, nc,      nc,     nc,
 912
 913                 nc,     nc,      nc,      ctl3215, nc,      clk2030, dq2030, cmd3210,
 914                 nc,     nc,      ctl3215, nc,      clk2030, nc,      dq2030, cmd3210,
 915                 nc,     nc,      nc,      ctl3215, nc,      clk2030, dq2030, cmd3210,
 916                 nc,     nc,      ctl3215, nc,      clk2030, clk2030, dq2030, cmd2710
 917         };
 918
 919         static const u32 const * const single_channel_slew_group_lookup[] = {
 920                 dq2330, cmd3210, ctl3215, ctl3215, clk2030, clk2030, dq2330, cmd3210,
 921                 dq2330, cmd3210, ctl3215, ctl3215, clk2030, clk2030, dq2330, cmd3210,
 922                 dq2330, cmd3210, nc,      ctl3215, nc,      clk2030, dq2330, cmd3210,
 923                 dq2330, cmd3210, ctl3215, ctl3215, clk2030, clk2030, dq2330, cmd3210,
 924                 dq2330, cmd3210, nc,      ctl3215, nc,      clk2030, nc,     nc,
 925
 926                 dq2330, cmd3210, ctl3215, ctl3215, clk2030, clk2030, dq2330, cmd3210,
 927                 dq2330, cmd3210, ctl3215, nc,      clk2030, nc,      dq2330, cmd3210,
 928                 dq2330, cmd3210, ctl3215, ctl3215, clk2030, clk2030, dq2330, cmd3210,
 929                 dq2330, cmd3210, ctl3215, nc,      clk2030, nc,      dq2330, cmd3210,
 930                 dq2330, cmd3210, ctl3215, nc,      clk2030, nc,      nc,     nc,
 931
 932                 dq2330, cmd3210, nc,      ctl3215, nc,      clk2030, dq2330, cmd3210,
 933                 dq2330, cmd3210, ctl3215, ctl3215, clk2030, clk2030, dq2330, cmd3210,
 934                 dq2330, cmd3210, nc,      ctl3215, nc,      clk2030, dq2330, cmd3210,
 935                 dq2330, cmd3210, ctl3215, ctl3215, clk2030, clk2030, dq2330, cmd3210,
 936                 dq2330, cmd3210, nc,      ctl3215, nc,      clk2030, nc,     nc,
 937
 938                 dq2330, cmd3210, ctl3215, ctl3215, clk2030, clk2030, dq2330, cmd3210,
 939                 dq2330, cmd3210, ctl3215, nc,      clk2030, nc,      dq2330, cmd3210,
 940                 dq2330, cmd3210, ctl3215, ctl3215, clk2030, clk2030, dq2330, cmd3210,
 941                 dq2330, cmd3210, ctl3215, nc,      clk2030, nc,      dq2330, cmd3210,
 942                 dq2330, cmd3210, ctl3215, nc,      clk2030, nc,      nc,     nc,
 943
 944                 dq2330, nc,      nc,      ctl3215, nc,      clk2030, dq2030, cmd3210,
 945                 dq2330, nc,      ctl3215, nc,      clk2030, nc,      dq2030, cmd3210,
 946                 dq2330, nc,      nc,      ctl3215, nc,      clk2030, dq2030, cmd3210,
 947                 dq2330, nc,      ctl3215, nc,      clk2030, clk2030, dq2030, cmd3210
 948         };
 949
 950         /* Strength multiplier tables */
 951         static const u8 dual_channel_strength_multiplier[] = {
 952                 0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11,
 953                 0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11,
 954                 0x44, 0x11, 0x00, 0x11, 0x00, 0x44, 0x44, 0x11,
 955                 0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x22,
 956                 0x44, 0x11, 0x00, 0x11, 0x00, 0x44, 0x00, 0x00,
 957                 0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11,
 958                 0x44, 0x11, 0x11, 0x00, 0x44, 0x00, 0x44, 0x11,
 959                 0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11,
 960                 0x44, 0x11, 0x11, 0x00, 0x44, 0x00, 0x44, 0x22,
 961                 0x44, 0x11, 0x11, 0x00, 0x44, 0x00, 0x00, 0x00,
 962                 0x44, 0x11, 0x00, 0x11, 0x00, 0x44, 0x44, 0x11,
 963                 0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11,
 964                 0x44, 0x11, 0x00, 0x11, 0x00, 0x44, 0x44, 0x11,
 965                 0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x22,
 966                 0x44, 0x11, 0x00, 0x11, 0x00, 0x44, 0x00, 0x00,
 967                 0x44, 0x22, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11,
 968                 0x44, 0x22, 0x11, 0x00, 0x44, 0x00, 0x44, 0x11,
 969                 0x44, 0x22, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11,
 970                 0x44, 0x22, 0x11, 0x00, 0x44, 0x00, 0x44, 0x22,
 971                 0x44, 0x22, 0x11, 0x00, 0x44, 0x00, 0x00, 0x00,
 972                 0x00, 0x00, 0x00, 0x11, 0x00, 0x44, 0x44, 0x11,
 973                 0x00, 0x00, 0x11, 0x00, 0x44, 0x00, 0x44, 0x11,
 974                 0x00, 0x00, 0x00, 0x11, 0x00, 0x44, 0x44, 0x11,
 975                 0x00, 0x00, 0x11, 0x00, 0x44, 0x44, 0x44, 0x22
 976         };
 977
 978         static const u8 single_channel_strength_multiplier[] = {
 979                 0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11,
 980                 0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11,
 981                 0x33, 0x11, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11,
 982                 0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11,
 983                 0x33, 0x11, 0x00, 0x11, 0x00, 0x44, 0x00, 0x00,
 984                 0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11,
 985                 0x33, 0x11, 0x11, 0x00, 0x44, 0x00, 0x33, 0x11,
 986                 0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11,
 987                 0x33, 0x11, 0x11, 0x00, 0x44, 0x00, 0x33, 0x11,
 988                 0x33, 0x11, 0x11, 0x00, 0x44, 0x00, 0x00, 0x00,
 989                 0x33, 0x11, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11,
 990                 0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11,
 991                 0x33, 0x11, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11,
 992                 0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11,
 993                 0x33, 0x11, 0x00, 0x11, 0x00, 0x44, 0x00, 0x00,
 994                 0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11,
 995                 0x33, 0x11, 0x11, 0x00, 0x44, 0x00, 0x33, 0x11,
 996                 0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11,
 997                 0x33, 0x11, 0x11, 0x00, 0x44, 0x00, 0x33, 0x11,
 998                 0x33, 0x11, 0x11, 0x00, 0x44, 0x00, 0x00, 0x00,
 999                 0x33, 0x00, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11,
1000                 0x33, 0x00, 0x11, 0x00, 0x44, 0x00, 0x33, 0x11,
1001                 0x33, 0x00, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11,
1002                 0x33, 0x00, 0x11, 0x00, 0x44, 0x44, 0x33, 0x11
1003         };
1004
1005         const u8 * strength_multiplier;
1006         const u32* const * slew_group_lookup;
1007         int idx;
1008
1009         /* Set Strength Multipliers */
1010
1011         /* Dual Channel needs different tables. */
1012         if (sdram_capabilities_dual_channel()) {
1013                 printk_debug("Programming Dual Channel RCOMP\n");
1014                 strength_multiplier = dual_channel_strength_multiplier;
1015                 slew_group_lookup   = dual_channel_slew_group_lookup;
1016                 idx = 5 * sysinfo->dimm[0] +  sysinfo->dimm[2];
1017         } else {
1018                 printk_debug("Programming Single Channel RCOMP\n");
1019                 strength_multiplier = single_channel_strength_multiplier;
1020                 slew_group_lookup   = single_channel_slew_group_lookup;
1021                 idx = 5 * sysinfo->dimm[0] + sysinfo->dimm[1];
1022         }
1023
1024         printk_debug("Table Index: %d\n", idx);
1025
1026         MCHBAR8(G1SC) = strength_multiplier[idx * 8 + 0];
1027         MCHBAR8(G2SC) = strength_multiplier[idx * 8 + 1];
1028         MCHBAR8(G3SC) = strength_multiplier[idx * 8 + 2];
1029         MCHBAR8(G4SC) = strength_multiplier[idx * 8 + 3];
1030         MCHBAR8(G5SC) = strength_multiplier[idx * 8 + 4];
1031         MCHBAR8(G6SC) = strength_multiplier[idx * 8 + 5];
1032         MCHBAR8(G7SC) = strength_multiplier[idx * 8 + 6];
1033         MCHBAR8(G8SC) = strength_multiplier[idx * 8 + 7];
1034
1035         /* Channel 0 */
1036         sdram_write_slew_rates(G1SRPUT, slew_group_lookup[idx * 8 + 0]);
1037         sdram_write_slew_rates(G2SRPUT, slew_group_lookup[idx * 8 + 1]);
1038         if ((slew_group_lookup[idx * 8 + 2] != nc) && (sysinfo->package == SYSINFO_PACKAGE_STACKED)) {
1039
1040                 sdram_write_slew_rates(G3SRPUT, ctl3220);
1041         } else {
1042                 sdram_write_slew_rates(G3SRPUT, slew_group_lookup[idx * 8 + 2]);
1043         }
1044         sdram_write_slew_rates(G4SRPUT, slew_group_lookup[idx * 8 + 3]);
1045         sdram_write_slew_rates(G5SRPUT, slew_group_lookup[idx * 8 + 4]);
1046         sdram_write_slew_rates(G6SRPUT, slew_group_lookup[idx * 8 + 5]);
1047
1048         /* Channel 1 */
1049         if (sysinfo->dual_channel) {
1050                 sdram_write_slew_rates(G7SRPUT, slew_group_lookup[idx * 8 + 6]);
1051                 sdram_write_slew_rates(G8SRPUT, slew_group_lookup[idx * 8 + 7]);
1052         } else {
1053                 sdram_write_slew_rates(G7SRPUT, nc);
1054                 sdram_write_slew_rates(G8SRPUT, nc);
1055         }
1056 }
1057
1058 static void sdram_enable_rcomp(void)
1059 {
1060         u32 reg32;
1061         /* Enable Global Periodic RCOMP */
1062         udelay(300);
1063         reg32 = MCHBAR32(GBRCOMPCTL);
1064         reg32 &= ~(1 << 23);
1065         MCHBAR32(GBRCOMPCTL) = reg32;
1066 }
1067
1068 static void sdram_program_dll_timings(struct sys_info *sysinfo)
1069 {
1070         u32 chan0dll = 0, chan1dll = 0;
1071         int i;
1072
1073         printk_debug ("Programming DLL Timings... \n");
1074
1075         MCHBAR16(DQSMT) &= ~( (3 << 12) | (1 << 10) | ( 0xf << 0) );
1076         MCHBAR16(DQSMT) |= (1 << 13) | (0xc << 0);
1077
1078         /* We drive both channels with the same speed */
1079         switch (sysinfo->memory_frequency) {
1080         case 400: chan0dll = 0x26262626; chan1dll=0x26262626; break; /* 400MHz */
1081         case 533: chan0dll = 0x22222222; chan1dll=0x22222222; break; /* 533MHz */
1082         case 667: chan0dll = 0x11111111; chan1dll=0x11111111; break; /* 667MHz */
1083         }
1084
1085         for (i=0; i < 4; i++) {
1086                 MCHBAR32(C0R0B00DQST + (i * 0x10) + 0) = chan0dll;
1087                 MCHBAR32(C0R0B00DQST + (i * 0x10) + 4) = chan0dll;
1088                 MCHBAR32(C1R0B00DQST + (i * 0x10) + 0) = chan1dll;
1089                 MCHBAR32(C1R0B00DQST + (i * 0x10) + 4) = chan1dll;
1090         }
1091 }
1092
1093 static void sdram_force_rcomp(void)
1094 {
1095         u32 reg32;
1096         u8 reg8;
1097
1098         reg32 = MCHBAR32(ODTC);
1099         reg32 |= (1 << 28);
1100         MCHBAR32(ODTC) = reg32;
1101
1102         reg32 = MCHBAR32(SMSRCTL);
1103         reg32 |= (1 << 0);
1104         MCHBAR32(SMSRCTL) = reg32;
1105
1106         /* Start initial RCOMP */
1107         reg32 = MCHBAR32(GBRCOMPCTL);
1108         reg32 |= (1 << 8);
1109         MCHBAR32(GBRCOMPCTL) = reg32;
1110
1111         reg8 = i945_silicon_revision();
1112         if ((reg8 == 0 && (MCHBAR32(DCC) & (3 << 0)) == 0) || (reg8 == 1)) {
1113                 reg32 = MCHBAR32(GBRCOMPCTL);
1114                 reg32 |= (3 << 5);
1115                 MCHBAR32(GBRCOMPCTL) = reg32;
1116         }
1117 }
1118
1119 static void sdram_initialize_system_memory_io(struct sys_info *sysinfo)
1120 {
1121         u8 reg8;
1122         u32 reg32;
1123
1124         printk_debug ("Initializing System Memory IO... \n");
1125         /* Enable Data Half Clock Pushout */
1126         reg8 = MCHBAR8(C0HCTC);
1127         reg8 &= ~0x1f;
1128         reg8 |= ( 1 << 0);
1129         MCHBAR8(C0HCTC) = reg8;
1130
1131         reg8 = MCHBAR8(C1HCTC);
1132         reg8 &= ~0x1f;
1133         reg8 |= ( 1 << 0);
1134         MCHBAR8(C1HCTC) = reg8;
1135
1136         MCHBAR16(WDLLBYPMODE) &= ~( (1 << 9) | (1 << 6) | (1 << 4) | (1 << 3) | (1 << 1) );
1137         MCHBAR16(WDLLBYPMODE) |= (1 << 8) | (1 << 7) | (1 << 5) | (1 << 2) | (1 << 0);
1138
1139         MCHBAR8(C0WDLLCMC) = 0;
1140         MCHBAR8(C1WDLLCMC) = 0;
1141
1142         /* Program RCOMP Settings */
1143         sdram_program_dram_width(sysinfo);
1144
1145         sdram_rcomp_buffer_strength_and_slew(sysinfo);
1146
1147         /* Indicate that RCOMP programming is done */
1148         reg32 = MCHBAR32(GBRCOMPCTL);
1149         reg32 &= ~( (1 << 29) | (1 << 26) | (3 << 21) | (3 << 2) );
1150         reg32 |= (3 << 27) | (3 << 0);
1151         MCHBAR32(GBRCOMPCTL) = reg32;
1152
1153         MCHBAR32(GBRCOMPCTL) |= (1 << 10);
1154
1155         /* Program DLL Timings */
1156         sdram_program_dll_timings(sysinfo);
1157
1158         /* Force RCOMP cycle */
1159         sdram_force_rcomp();
1160 }
1161
1162 static void sdram_enable_system_memory_io(struct sys_info *sysinfo)
1163 {
1164         u32 reg32;
1165
1166         printk_debug ("Enabling System Memory IO... \n");
1167
1168         reg32 = MCHBAR32(RCVENMT);
1169         reg32 &= ~(0x3f << 6);
1170         MCHBAR32(RCVENMT) = reg32; /* [11:6] = 0 */
1171
1172         reg32 |= (1 << 11) | (1 << 9);
1173         MCHBAR32(RCVENMT) = reg32;
1174
1175         reg32 = MCHBAR32(DRTST);
1176         reg32 |= (1 << 3) | (1 << 2);
1177         MCHBAR32(DRTST) = reg32;
1178
1179         reg32 = MCHBAR32(DRTST);
1180         reg32 |= (1 << 6) | (1 << 4);
1181         MCHBAR32(DRTST) = reg32;
1182
1183         asm volatile ("nop; nop;");
1184
1185         reg32 = MCHBAR32(DRTST);
1186
1187         /* Is channel 0 populated? */
1188         if (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED ||
1189                         sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED)
1190                 reg32 |= (1 << 7) | (1 << 5);
1191         else
1192                 reg32 |= (1 << 31);
1193
1194         /* Is channel 1 populated? */
1195         if (sysinfo->dimm[2] != SYSINFO_DIMM_NOT_POPULATED ||
1196                         sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED)
1197                 reg32 |= (1 << 9) | (1 << 8);
1198         else
1199                 reg32 |= (1 << 30);
1200
1201         MCHBAR32(DRTST) = reg32;
1202
1203         /* Activate DRAM Channel IO Buffers */
1204         if (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED ||
1205                         sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED) {
1206                 reg32 = MCHBAR32(C0DRC1);
1207                 reg32 |= (1 << 8);
1208                 MCHBAR32(C0DRC1) = reg32;
1209         }
1210         if (sysinfo->dimm[2] != SYSINFO_DIMM_NOT_POPULATED ||
1211                         sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED) {
1212                 reg32 = MCHBAR32(C1DRC1);
1213                 reg32 |= (1 << 8);
1214                 MCHBAR32(C1DRC1) = reg32;
1215         }
1216 }
1217
1218 struct dimm_size {
1219         unsigned long side1;
1220         unsigned long side2;
1221 };
1222
1223 static struct dimm_size sdram_get_dimm_size(u16 device)
1224 {
1225         /* Calculate the log base 2 size of a DIMM in bits */
1226         struct dimm_size sz;
1227         int value, low, rows, columns;
1228
1229         sz.side1 = 0;
1230         sz.side2 = 0;
1231
1232         rows = spd_read_byte(device, SPD_NUM_ROWS);     /* rows */
1233         if (rows < 0) goto hw_err;
1234         if ((rows & 0xf) == 0) goto val_err;
1235         sz.side1 += rows & 0xf;
1236
1237         columns = spd_read_byte(device, SPD_NUM_COLUMNS);       /* columns */
1238         if (columns < 0) goto hw_err;
1239         if ((columns & 0xf) == 0) goto val_err;
1240         sz.side1 += columns & 0xf;
1241
1242         value = spd_read_byte(device, SPD_NUM_BANKS_PER_SDRAM); /* banks */
1243         if (value < 0) goto hw_err;
1244         if ((value & 0xff) == 0) goto val_err;
1245         sz.side1 += log2(value & 0xff);
1246
1247         /* Get the module data width and convert it to a power of two */
1248         value = spd_read_byte(device, SPD_MODULE_DATA_WIDTH_MSB);       /* (high byte) */
1249         if (value < 0) goto hw_err;
1250         value &= 0xff;
1251         value <<= 8;
1252
1253         low = spd_read_byte(device, SPD_MODULE_DATA_WIDTH_LSB); /* (low byte) */
1254         if (low < 0) goto hw_err;
1255         value = value | (low & 0xff);
1256         if ((value != 72) && (value != 64)) goto val_err;
1257         sz.side1 += log2(value);
1258
1259         /* side 2 */
1260         value = spd_read_byte(device, SPD_NUM_DIMM_BANKS);      /* number of physical banks */
1261
1262         if (value < 0) goto hw_err;
1263         value &= 7;
1264         value++;
1265         if (value == 1) goto out;
1266         if (value != 2) goto val_err;
1267
1268         /* Start with the symmetrical case */
1269         sz.side2 = sz.side1;
1270
1271         if ((rows & 0xf0) == 0) goto out;       /* If symmetrical we are done */
1272
1273         /* Don't die here, I have not come across any of these to test what
1274          * actually happens.
1275          */
1276         printk_err("Assymetric DIMMs are not supported by this chipset\n");
1277
1278         sz.side2 -= (rows & 0x0f);              /* Subtract out rows on side 1 */
1279         sz.side2 += ((rows >> 4) & 0x0f);       /* Add in rows on side 2 */
1280
1281         sz.side2 -= (columns & 0x0f);           /* Subtract out columns on side 1 */
1282         sz.side2 += ((columns >> 4) & 0x0f);    /* Add in columns on side 2 */
1283
1284         goto out;
1285
1286  val_err:
1287         die("Bad SPD value\n");
1288  hw_err:
1289         /* If a hardware error occurs the spd rom probably does not exist.
1290          * In this case report that there is no memory
1291          */
1292         sz.side1 = 0;
1293         sz.side2 = 0;
1294  out:
1295         return sz;
1296 }
1297
1298 static void sdram_detect_dimm_size(struct sys_info * sysinfo)
1299 {
1300         int i;
1301
1302         for(i = 0; i < 2 * DIMM_SOCKETS; i++) {
1303                 struct dimm_size sz;
1304
1305                 sysinfo->banksize[i * 2] = 0;
1306                 sysinfo->banksize[(i * 2) + 1] = 0;
1307
1308                 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
1309                         continue;
1310
1311                 sz = sdram_get_dimm_size(DIMM_SPD_BASE + i);
1312
1313                 sysinfo->banks[i] = spd_read_byte(DIMM_SPD_BASE + i, SPD_NUM_BANKS_PER_SDRAM);  /* banks */
1314
1315                 if (sz.side1 < 30)
1316                         die("DDR-II rank size smaller than 128MB is not supported.\n");
1317
1318                 sysinfo->banksize[i * 2] = 1 << (sz.side1 - 28);
1319
1320                 printk_debug("DIMM %d side 0 = %d MB\n", i, sysinfo->banksize[i * 2] * 32 );
1321
1322                 if (!sz.side2)
1323                         continue;
1324
1325                 /* If there is a second side, it has to have at least 128M, too */
1326                 if (sz.side2 < 30)
1327                         die("DDR-II rank size smaller than 128MB is not supported.\n");
1328
1329                 sysinfo->banksize[(i * 2) + 1] = 1 << (sz.side2 - 28);
1330
1331                 printk_debug("DIMM %d side 1 = %d MB\n", i, sysinfo->banksize[(i * 2) + 1] * 32);
1332         }
1333 }
1334
1335 static int sdram_program_row_boundaries(struct sys_info *sysinfo)
1336 {
1337         int i;
1338         int cum0, cum1, tolud, tom;
1339
1340         printk_debug ("Setting RAM size... \n");
1341
1342         cum0 = 0;
1343         for(i = 0; i < 2 * DIMM_SOCKETS; i++) {
1344                 cum0 += sysinfo->banksize[i];
1345                 MCHBAR8(C0DRB0+i) = cum0;
1346         }
1347
1348         /* Assume we continue in Channel 1 where we stopped in Channel 0 */
1349         cum1 = cum0;
1350
1351         /* Exception: Interleaved starts from the beginning */
1352         if (sysinfo->interleaved)
1353                 cum1 = 0;
1354
1355         /* Exception: Channel 1 is not populated. C1DRB stays zero */
1356         if (sysinfo->dimm[2] == SYSINFO_DIMM_NOT_POPULATED &&
1357                         sysinfo->dimm[3] == SYSINFO_DIMM_NOT_POPULATED)
1358                 cum1 = 0;
1359
1360         for(i = 0; i < 2 * DIMM_SOCKETS; i++) {
1361                 cum1 += sysinfo->banksize[i + 4];
1362                 MCHBAR8(C1DRB0+i) = cum1;
1363         }
1364
1365         /* Set TOLUD Top Of Low Usable DRAM */
1366         if (sysinfo->interleaved)
1367                 tolud = (cum0 + cum1) << 1;
1368         else
1369                 tolud = (cum1 ? cum1 : cum0)  << 1;
1370
1371         /* The TOM register has a different format */
1372         tom = tolud >> 3;
1373
1374         /* Limit the value of TOLUD to leave some space for PCI memory. */
1375         if (tolud > 0xd0)
1376                 tolud = 0xd0;   /* 3.25GB : 0.75GB */
1377
1378         pci_write_config8(PCI_DEV(0,0,0), TOLUD, tolud);
1379
1380         printk_debug("C0DRB = 0x%08x\n", MCHBAR32(C0DRB0));
1381         printk_debug("C1DRB = 0x%08x\n", MCHBAR32(C1DRB0));
1382         printk_debug("TOLUD = 0x%04x\n", pci_read_config8(PCI_DEV(0,0,0), TOLUD));
1383
1384         pci_write_config16(PCI_DEV(0,0,0), TOM, tom);
1385
1386         return 0;
1387 }
1388
1389 static int sdram_set_row_attributes(struct sys_info *sysinfo)
1390 {
1391         int i, value;
1392         u16 dra0=0, dra1=0, dra = 0;
1393
1394         printk_debug ("Setting row attributes... \n");
1395         for(i=0; i < 2 * DIMM_SOCKETS; i++) {
1396                 u16 device;
1397                 u8 columnsrows;
1398
1399                 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) {
1400                         continue;
1401                 }
1402
1403                 device = DIMM_SPD_BASE + i;
1404
1405                 value = spd_read_byte(device, SPD_NUM_ROWS);    /* rows */
1406                 columnsrows = (value & 0x0f);
1407
1408                 value = spd_read_byte(device, SPD_NUM_COLUMNS); /* columns */
1409                 columnsrows |= (value & 0xf) << 4;
1410
1411                 switch (columnsrows) {
1412                 case 0x9d: dra = 2; break;
1413                 case 0xad: dra = 3; break;
1414                 case 0xbd: dra = 4; break;
1415                 case 0xae: dra = 3; break;
1416                 case 0xbe: dra = 4; break;
1417                 default: die("Unsupported Rows/Columns. (DRA)");
1418                 }
1419
1420                 /* Double Sided DIMMs? */
1421                 if (sysinfo->banksize[(2 * i) + 1] != 0) {
1422                         dra = (dra << 4) | dra;
1423                 }
1424
1425                 if (i < DIMM_SOCKETS)
1426                         dra0 |= (dra << (i*8));
1427                 else
1428                         dra1 |= (dra << ((i - DIMM_SOCKETS)*8));
1429         }
1430
1431         MCHBAR16(C0DRA0) = dra0;
1432         MCHBAR16(C1DRA0) = dra1;
1433
1434         printk_debug("C0DRA = 0x%04x\n", dra0);
1435         printk_debug("C1DRA = 0x%04x\n", dra1);
1436
1437         return 0;
1438 }
1439
1440 static void sdram_set_bank_architecture(struct sys_info *sysinfo)
1441 {
1442         u32 off32;
1443         int i;
1444
1445         MCHBAR16(C1BNKARC) &= 0xff00;
1446         MCHBAR16(C0BNKARC) &= 0xff00;
1447
1448         off32 = C0BNKARC;
1449         for (i=0; i < 2 * DIMM_SOCKETS; i++) {
1450                 /* Switch to second channel */
1451                 if (i == DIMM_SOCKETS)
1452                         off32 = C1BNKARC;
1453
1454                 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
1455                         continue;
1456
1457                 if (sysinfo->banks[i] != 8)
1458                         continue;
1459
1460                 printk_spew("DIMM%d has 8 banks.\n");
1461
1462                 if (i & 1)
1463                         MCHBAR16(off32) |= 0x50;
1464                 else
1465                         MCHBAR16(off32) |= 0x05;
1466         }
1467 }
1468
1469 #define REFRESH_7_8US   1
1470 #define REFRESH_15_6US  0
1471 static void sdram_program_refresh_rate(struct sys_info *sysinfo)
1472 {
1473         u32 reg32;
1474
1475         if (sysinfo->refresh == REFRESH_7_8US) {
1476                 reg32 = (2 << 8); /* Refresh enabled at 7.8us */
1477         } else {
1478                 reg32 = (1 << 8); /* Refresh enabled at 15.6us */
1479         }
1480
1481         MCHBAR32(C0DRC0) &= ~(7 << 8);
1482         MCHBAR32(C0DRC0) |= reg32;
1483
1484         MCHBAR32(C1DRC0) &= ~(7 << 8);
1485         MCHBAR32(C1DRC0) |= reg32;
1486 }
1487
1488 static void sdram_program_cke_tristate(struct sys_info *sysinfo)
1489 {
1490         u32 reg32;
1491         int i;
1492
1493         reg32 = MCHBAR32(C0DRC1);
1494
1495         for (i=0; i < 4; i++) {
1496                 if (sysinfo->banksize[i] == 0) {
1497                         reg32 |= (1 << (16 + i));
1498                 }
1499         }
1500
1501         reg32 |= (1 << 12);
1502
1503         reg32 |= (1 << 11);
1504         MCHBAR32(C0DRC1) = reg32;
1505
1506         /* Do we have to do this if we're in Single Channel Mode?  */
1507         reg32 = MCHBAR32(C1DRC1);
1508
1509         for (i=4; i < 8; i++) {
1510                 if (sysinfo->banksize[i] == 0) {
1511                         reg32 |= (1 << (12 + i));
1512                 }
1513         }
1514
1515         reg32 |= (1 << 12);
1516
1517         reg32 |= (1 << 11);
1518         MCHBAR32(C1DRC1) = reg32;
1519 }
1520
1521 static void sdram_program_odt_tristate(struct sys_info *sysinfo)
1522 {
1523         u32 reg32;
1524         int i;
1525
1526         reg32 = MCHBAR32(C0DRC2);
1527
1528         for (i=0; i < 4; i++) {
1529                 if (sysinfo->banksize[i] == 0) {
1530                         reg32 |= (1 << (24 + i));
1531                 }
1532         }
1533         MCHBAR32(C0DRC2) = reg32;
1534
1535         reg32 = MCHBAR32(C1DRC2);
1536
1537         for (i=4; i < 8; i++) {
1538                 if (sysinfo->banksize[i] == 0) {
1539                         reg32 |= (1 << (20 + i));
1540                 }
1541         }
1542         MCHBAR32(C1DRC2) = reg32;
1543 }
1544
1545 static void sdram_set_timing_and_control(struct sys_info *sysinfo)
1546 {
1547         u32 reg32, off32;
1548         u32 tWTR;
1549         u32 temp_drt;
1550         int i, page_size;
1551
1552         static const u8 const drt0_table[] = {
1553           /* CL 3, 4, 5 */
1554                 3, 4, 5,        /* FSB533/400, DDR533/400 */
1555                 4, 5, 6,        /* FSB667, DDR533/400 */
1556                 4, 5, 6,        /* FSB667, DDR667 */
1557         };
1558
1559         static const u8 const cas_table[] = {
1560                 2, 1, 0, 3
1561         };
1562
1563         reg32 = MCHBAR32(C0DRC0);
1564         reg32 |= (1 << 2);      /* Burst Length 8 */
1565         reg32 &= ~( (1 << 13) | (1 << 12) );
1566         MCHBAR32(C0DRC0) = reg32;
1567
1568         reg32 = MCHBAR32(C1DRC0);
1569         reg32 |= (1 << 2);      /* Burst Length 8 */
1570         reg32 &= ~( (1 << 13) | (1 << 12) );
1571         MCHBAR32(C1DRC0) = reg32;
1572
1573         if (!sysinfo->dual_channel && sysinfo->dimm[1] !=
1574                         SYSINFO_DIMM_NOT_POPULATED) {
1575                 reg32 = MCHBAR32(C0DRC0);
1576                 reg32 |= (1 << 15);
1577                 MCHBAR32(C0DRC0) = reg32;
1578         }
1579
1580         sdram_program_refresh_rate(sysinfo);
1581
1582         sdram_program_cke_tristate(sysinfo);
1583
1584         sdram_program_odt_tristate(sysinfo);
1585
1586         /* Calculate DRT0 */
1587
1588         temp_drt = 0;
1589
1590         /* B2B Write Precharge (same bank) = CL-1 + BL/2 + tWR */
1591         reg32 = (sysinfo->cas - 1) + (BURSTLENGTH / 2) + sysinfo->twr;
1592         temp_drt |= (reg32 << 28);
1593
1594         /* Write Auto Precharge (same bank) = CL-1 + BL/2 + tWR + tRP */
1595         reg32 += sysinfo->trp;
1596         temp_drt |= (reg32 << 4);
1597
1598         if (sysinfo->memory_frequency == 667) {
1599                 tWTR = 3; /* 667MHz */
1600         } else {
1601                 tWTR = 2; /* 400 and 533 */
1602         }
1603
1604         /* B2B Write to Read Command Spacing */
1605         reg32 = (sysinfo->cas - 1) + (BURSTLENGTH / 2) + tWTR;
1606         temp_drt |= (reg32 << 24);
1607
1608         /* CxDRT0 [23:22], [21:20], [19:18] [16] have fixed values */
1609         temp_drt |= ( (1 << 22) | (3 << 20) | (1 << 18) | (0 << 16) );
1610
1611         /* Program Write Auto Precharge to Activate */
1612         off32 = 0;
1613         if (sysinfo->fsb_frequency == 667) { /* 667MHz FSB */
1614                 off32 += 3;
1615         }
1616         if (sysinfo->memory_frequency == 667) {
1617                 off32 += 3;
1618         }
1619         off32 += sysinfo->cas - 3;
1620         reg32 = drt0_table[off32];
1621         temp_drt |= (reg32 << 11);
1622
1623         /* Read Auto Precharge to Activate */
1624
1625         temp_drt |= (8 << 0);
1626
1627         MCHBAR32(C0DRT0) = temp_drt;
1628         MCHBAR32(C1DRT0) = temp_drt;
1629
1630         /* Calculate DRT1 */
1631
1632         temp_drt = MCHBAR32(C0DRT1) & 0x00020088;
1633
1634         /* DRAM RASB Precharge */
1635         temp_drt |= (sysinfo->trp - 2) << 0;
1636
1637         /* DRAM RASB to CASB Delay */
1638         temp_drt |= (sysinfo->trcd - 2) << 4;
1639
1640         /* CASB Latency */
1641         temp_drt |= (cas_table[sysinfo->cas - 3]) << 8;
1642
1643         /* Refresh Cycle Time */
1644         temp_drt |= (sysinfo->trfc) << 10;
1645
1646         /* Pre-All to Activate Delay */
1647         temp_drt |= (0 << 16);
1648
1649         /* Precharge to Precharge Delay stays at 1 clock */
1650         temp_drt |= (0 << 18);
1651
1652         /* Activate to Precharge Delay */
1653         temp_drt |= (sysinfo->tras << 19);
1654
1655         /* Read to Precharge (tRTP) */
1656         if (sysinfo->memory_frequency == 667) {
1657                 temp_drt |= (1 << 28);
1658         } else {
1659                 temp_drt |= (0 << 28);
1660         }
1661
1662         /* Determine page size */
1663         reg32 = 0;
1664         page_size = 1; /* Default: 1k pagesize */
1665         for (i=0; i< 2*DIMM_SOCKETS; i++) {
1666                 if (sysinfo->dimm[i] == SYSINFO_DIMM_X16DS ||
1667                                 sysinfo->dimm[i] == SYSINFO_DIMM_X16SS)
1668                         page_size = 2; /* 2k pagesize */
1669         }
1670
1671         if (sysinfo->memory_frequency == 533 && page_size == 2) {
1672                 reg32 = 1;
1673         }
1674         if (sysinfo->memory_frequency == 667) {
1675                 reg32 = page_size;
1676         }
1677
1678         temp_drt |= (reg32 << 30);
1679
1680         MCHBAR32(C0DRT1) = temp_drt;
1681         MCHBAR32(C1DRT1) = temp_drt;
1682
1683         /* Program DRT2 */
1684         reg32 = MCHBAR32(C0DRT2);
1685         reg32 &= ~(1 << 8);
1686         MCHBAR32(C0DRT2) = reg32;
1687
1688         reg32 = MCHBAR32(C1DRT2);
1689         reg32 &= ~(1 << 8);
1690         MCHBAR32(C1DRT2) = reg32;
1691
1692         /* Calculate DRT3 */
1693         temp_drt = MCHBAR32(C0DRT3) & ~0x07ffffff;
1694
1695         /* Get old tRFC value */
1696         reg32 = MCHBAR32(C0DRT1) >> 10;
1697         reg32 &= 0x3f;
1698
1699         /* 788nS - tRFC */
1700         switch (sysinfo->memory_frequency) {
1701         case 400: /* 5nS */
1702                 reg32 = ((78800 / 500) - reg32) & 0x1ff;
1703                 reg32 |= (0x8c << 16) | (0x0c << 10); /* 1 us */
1704                 break;
1705         case 533: /* 3.75nS */
1706                 reg32 = ((78800 / 375) - reg32) & 0x1ff;
1707                 reg32 |= (0xba << 16) | (0x10 << 10); /* 1 us */
1708                 break;
1709         case 667: /* 3nS */
1710                 reg32 = ((78800 / 300) - reg32) & 0x1ff;
1711                 reg32 |= (0xe9 << 16) | (0x14 << 10); /* 1 us */
1712                 break;
1713         }
1714
1715         temp_drt |= reg32;
1716
1717         MCHBAR32(C0DRT3) = temp_drt;
1718         MCHBAR32(C1DRT3) = temp_drt;
1719 }
1720
1721 static void sdram_set_channel_mode(struct sys_info *sysinfo)
1722 {
1723         u32 reg32;
1724
1725         printk_debug("Setting mode of operation for memory channels...");
1726
1727         if (sdram_capabilities_interleave() &&
1728                     ( ( sysinfo->banksize[0] + sysinfo->banksize[1] +
1729                         sysinfo->banksize[2] + sysinfo->banksize[3] ) ==
1730                       ( sysinfo->banksize[4] + sysinfo->banksize[5] +
1731                         sysinfo->banksize[6] + sysinfo->banksize[7] ) ) ) {
1732                 /* Both channels equipped with DIMMs of the same size */
1733                 sysinfo->interleaved = 1;
1734         } else {
1735                 sysinfo->interleaved = 0;
1736         }
1737
1738         reg32 = MCHBAR32(DCC);
1739         reg32 &= ~(7 << 0);
1740
1741         if(sysinfo->interleaved) {
1742                 /* Dual Channel Interleaved */
1743                 printk_debug("Dual Channel Interleaved.\n");
1744                 reg32 |= (1 << 1);
1745         } else if (sysinfo->dimm[0] == SYSINFO_DIMM_NOT_POPULATED &&
1746                         sysinfo->dimm[1] == SYSINFO_DIMM_NOT_POPULATED) {
1747                 /* Channel 1 only */
1748                 printk_debug("Single Channel 1 only.\n");
1749                 reg32 |= (1 << 2);
1750         } else if (sdram_capabilities_dual_channel() && sysinfo->dimm[2] !=
1751                         SYSINFO_DIMM_NOT_POPULATED) {
1752                 /* Dual Channel Assymetric */
1753                 printk_debug("Dual Channel Assymetric.\n");
1754                 reg32 |= (1 << 0);
1755         } else {
1756                 /* All bits 0 means Single Channel 0 operation */
1757                 printk_debug("Single Channel 0 only.\n");
1758         }
1759
1760         reg32 |= (1 << 10);
1761
1762         MCHBAR32(DCC) = reg32;
1763
1764         PRINTK_DEBUG("DCC=0x%08x\n", MCHBAR32(DCC));
1765 }
1766
1767 static void sdram_program_pll_settings(struct sys_info *sysinfo)
1768 {
1769         volatile u16 reg16;
1770
1771         MCHBAR32(PLLMON) = 0x80800000;
1772
1773         switch (MCHBAR32(CLKCFG) & 0x7) {
1774         case 0: sysinfo->fsb_frequency = 400; break;    /* FSB400 */
1775         case 1: sysinfo->fsb_frequency = 533; break;    /* FSB533 */
1776         case 3: sysinfo->fsb_frequency = 667; break;    /* FSB667 */
1777         default: die("Unsupported FSB speed");
1778         }
1779
1780         /* Program CPCTL according to FSB speed */
1781         /* Only write the lower byte */
1782         switch (sysinfo->fsb_frequency) {
1783         case 400: MCHBAR8(CPCTL) = 0x90; break; /* FSB400 */
1784         case 533: MCHBAR8(CPCTL) = 0x95; break; /* FSB533 */
1785         case 667: MCHBAR8(CPCTL) = 0x8d; break; /* FSB667 */
1786         }
1787
1788         MCHBAR16(CPCTL) &= ~(1 << 11);
1789
1790         reg16 = MCHBAR16(CPCTL); /* Read back register to activate settings */
1791 }
1792
1793 static void sdram_program_graphics_frequency(struct sys_info *sysinfo)
1794 {
1795         u8  reg8;
1796         u16 reg16;
1797         u8  freq, second_vco, voltage;
1798
1799 #define CRCLK_166MHz    0x00
1800 #define CRCLK_200MHz    0x01
1801 #define CRCLK_250MHz    0x03
1802 #define CRCLK_400MHz    0x05
1803
1804 #define CDCLK_200MHz    0x00
1805 #define CDCLK_320MHz    0x40
1806
1807 #define VOLTAGE_1_05    0x00
1808 #define VOLTAGE_1_50    0x01
1809
1810         printk_debug ("Setting Graphics Frequency... \n");
1811
1812         printk_debug("FSB: %d MHz ", sysinfo->fsb_frequency);
1813
1814         voltage = VOLTAGE_1_05;
1815         if (MCHBAR32(DFT_STRAP1) & (1 << 20))
1816                 voltage = VOLTAGE_1_50;
1817         printk_debug("Voltage: %s ", (voltage==VOLTAGE_1_05)?"1.05V":"1.5V");
1818
1819         /* Gate graphics hardware for frequency change */
1820         reg8 = pci_read_config16(PCI_DEV(0,2,0), GCFC + 1);
1821         reg8 = (1<<3) | (1<<1); /* disable crclk, gate cdclk */
1822         pci_write_config8(PCI_DEV(0,2,0), GCFC + 1, reg8);
1823
1824         /* Get graphics frequency capabilities */
1825         reg8 = sdram_capabilities_core_frequencies();
1826
1827         freq = CRCLK_250MHz;
1828         switch (reg8) {
1829         case GFX_FREQUENCY_CAP_ALL:
1830                 if (voltage == VOLTAGE_1_05)
1831                         freq = CRCLK_250MHz;
1832                 else
1833                         freq = CRCLK_400MHz;
1834                 break;
1835         case GFX_FREQUENCY_CAP_250MHZ: freq = CRCLK_250MHz; break;
1836         case GFX_FREQUENCY_CAP_200MHZ: freq = CRCLK_200MHz; break;
1837         case GFX_FREQUENCY_CAP_166MHZ: freq = CRCLK_166MHz; break;
1838         }
1839
1840         if (freq != CRCLK_400MHz) {
1841                 /* What chipset are we? Force 166MHz for GMS */
1842                 reg8 = (pci_read_config8(PCI_DEV(0, 0x00,0), 0xe7) & 0x70) >> 4;
1843                 if (reg8==2)
1844                         freq = CRCLK_166MHz;
1845         }
1846
1847         printk_debug("Render: ");
1848         switch (freq) {
1849         case CRCLK_166MHz: printk_debug("166Mhz"); break;
1850         case CRCLK_200MHz: printk_debug("200Mhz"); break;
1851         case CRCLK_250MHz: printk_debug("250Mhz"); break;
1852         case CRCLK_400MHz: printk_debug("400Mhz"); break;
1853         }
1854
1855         if (i945_silicon_revision() == 0) {
1856                 sysinfo->mvco4x = 1;
1857         } else {
1858                 sysinfo->mvco4x = 0;
1859         }
1860
1861         second_vco = 0;
1862
1863         if (voltage == VOLTAGE_1_50) {
1864                 second_vco = 1;
1865         } else if ((i945_silicon_revision() > 0) && (freq == CRCLK_250MHz))  {
1866                 u16 mem = sysinfo->memory_frequency;
1867                 u16 fsb = sysinfo->fsb_frequency;
1868
1869                 if ( (fsb == 667 && mem == 533) ||
1870                      (fsb == 533 && mem == 533) ||
1871                      (fsb == 533 && mem == 400)) {
1872                         second_vco = 1;
1873                 }
1874
1875                 if (fsb == 667 && mem == 533)
1876                         sysinfo->mvco4x = 1;
1877         }
1878
1879         if (second_vco) {
1880                 sysinfo->clkcfg_bit7=1;
1881         } else {
1882                 sysinfo->clkcfg_bit7=0;
1883         }
1884
1885         /* Graphics Core Render Clock */
1886         reg16 = pci_read_config16(PCI_DEV(0,2,0), GCFC);
1887         reg16 &= ~( (7 << 0) | (1 << 13) );
1888         reg16 |= freq;
1889         pci_write_config16(PCI_DEV(0,2,0), GCFC, reg16);
1890
1891         /* Graphics Core Display Clock */
1892         reg8 = pci_read_config8(PCI_DEV(0,2,0), GCFC);
1893         reg8 &= ~( (1<<7) | (7<<4) );
1894
1895         if (voltage == VOLTAGE_1_05) {
1896                 reg8 |= CDCLK_200MHz;
1897                 printk_debug(" Display: 200MHz\n");
1898         } else {
1899                 reg8 |= CDCLK_320MHz;
1900                 printk_debug(" Display: 320MHz\n");
1901         }
1902         pci_write_config8(PCI_DEV(0,2,0), GCFC, reg8);
1903
1904         reg8 = pci_read_config8(PCI_DEV(0,2,0), GCFC + 1);
1905
1906         reg8 |= (1<<3) | (1<<1);
1907         pci_write_config8(PCI_DEV(0,2,0), GCFC + 1, reg8);
1908
1909         reg8 |= 0x0f;
1910         pci_write_config8(PCI_DEV(0,2,0), GCFC + 1, reg8);
1911
1912         /* Ungate core render and display clocks */
1913         reg8 &= 0xf0;
1914         pci_write_config8(PCI_DEV(0,2,0), GCFC + 1, reg8);
1915 }
1916
1917 static void sdram_program_memory_frequency(struct sys_info *sysinfo)
1918 {
1919         u32 clkcfg;
1920         u8 reg8;
1921
1922         printk_debug ("Setting Memory Frequency... ");
1923
1924         clkcfg = MCHBAR32(CLKCFG);
1925
1926         printk_debug("CLKCFG=0x%08x, ", clkcfg);
1927
1928         clkcfg &= ~( (1 << 12) | (1 << 7) | ( 7 << 4) );
1929
1930         if (sysinfo->mvco4x) {
1931                 printk_debug("MVCO 4x, ");
1932                 clkcfg &= ~(1 << 12);
1933         }
1934
1935         if (sysinfo->clkcfg_bit7) {
1936                 printk_debug("second VCO, ");
1937
1938                 clkcfg |= (1 << 7);
1939         }
1940
1941         switch (sysinfo->memory_frequency) {
1942         case 400: clkcfg |= (2 << 4); break;
1943         case 533: clkcfg |= (3 << 4); break;
1944         case 667: clkcfg |= (4 << 4); break;
1945         default: die("Target Memory Frequency Error");
1946         }
1947
1948         if (MCHBAR32(CLKCFG) == clkcfg) {
1949                 printk_debug ("ok (unchanged)\n");
1950                 return;
1951         }
1952
1953         MCHBAR32(CLKCFG) = clkcfg;
1954
1955         /* Make sure the following code is in the
1956          * cache before we execute it.
1957          */
1958         goto cache_code;
1959 vco_update:
1960         reg8 = pci_read_config8(PCI_DEV(0,0x1f,0), 0xa2);
1961         reg8 &= ~(1 << 7);
1962         pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8);
1963
1964         clkcfg &= ~(1 << 10);
1965         MCHBAR32(CLKCFG) = clkcfg;
1966         clkcfg |= (1 << 10);
1967         MCHBAR32(CLKCFG) = clkcfg;
1968
1969         __asm__ __volatile__ (
1970                 "       movl $0x100, %%ecx\n"
1971                 "delay_update:\n"
1972                 "       nop\n"
1973                 "       nop\n"
1974                 "       nop\n"
1975                 "       nop\n"
1976                 "       loop delay_update\n"
1977                 : /* No outputs */
1978                 : /* No inputs */
1979                 : "%ecx"
1980                 );
1981
1982         clkcfg &= ~(1 << 10);
1983         MCHBAR32(CLKCFG) = clkcfg;
1984
1985         goto out;
1986 cache_code:
1987         goto vco_update;
1988 out:
1989
1990         printk_debug("CLKCFG=0x%08x, ", MCHBAR32(CLKCFG));
1991         printk_debug ("ok\n");
1992 }
1993
1994 static void sdram_program_clock_crossing(void)
1995 {
1996         u32 reg32;
1997         int idx = 0;
1998
1999         /**
2000          * We add the indices according to our clocks from CLKCFG.
2001          */
2002
2003         static const u32 data_clock_crossing[] = {
2004                 0x00100401, 0x00000000, /* DDR400 FSB400 */
2005
2006                 0x08040120, 0x00000000, /* DDR400 FSB533 */
2007                 0x00100401, 0x00000000, /* DDR533 FSB533 */
2008
2009                 0x04020120, 0x00000010, /* DDR400 FSB667 */
2010                 0x10040280, 0x00000040, /* DDR533 FSB667 */
2011                 0x00100401, 0x00000000  /* DDR667 FSB667 */
2012         };
2013
2014         static const u32 command_clock_crossing[] = {
2015                 0x04020208, 0x00000000, /* DDR400 FSB400 */
2016
2017                 0x00060108, 0x00000000, /* DDR400 FSB533 */
2018                 0x04020108, 0x00000000, /* DDR533 FSB533 */
2019
2020                 0x00040318, 0x00000000, /* DDR400 FSB667 */
2021                 0x04020118, 0x00000000, /* DDR533 FSB667 */
2022                 0x02010804, 0x00000000  /* DDR667 FSB667 */
2023         };
2024
2025         printk_debug("Programming Clock Crossing...");
2026         reg32 = MCHBAR32(CLKCFG);
2027
2028         printk_debug("MEM=");
2029         switch ((reg32 >> 4) & 7) {
2030         case 2: printk_debug("400"); idx += 0; break;
2031         case 3: printk_debug("533"); idx += 2; break;
2032         case 4: printk_debug("667"); idx += 4; break;
2033         default: printk_debug("RSVD\n"); return;
2034         }
2035
2036         printk_debug(" FSB=");
2037         switch (reg32 & 7) {
2038         case 0: printk_debug("400\n"); idx += 0; break;
2039         case 1: printk_debug("533"); idx += 2; break;
2040         case 3: printk_debug("667"); idx += 6; break;
2041         default: printk_debug("RSVD\n"); return;
2042         }
2043
2044         MCHBAR32(CCCFT + 0) = command_clock_crossing[idx];
2045         MCHBAR32(CCCFT + 4) = command_clock_crossing[idx + 1];
2046
2047         MCHBAR32(C0DCCFT + 0) = data_clock_crossing[idx];
2048         MCHBAR32(C0DCCFT + 4) = data_clock_crossing[idx + 1];
2049         MCHBAR32(C1DCCFT + 0) = data_clock_crossing[idx];
2050         MCHBAR32(C1DCCFT + 4) = data_clock_crossing[idx + 1];
2051
2052         printk_debug("... ok\n");
2053 }
2054
2055 static void sdram_disable_fast_dispatch(void)
2056 {
2057         u32 reg32;
2058
2059         reg32 = MCHBAR32(FSBPMC3);
2060         reg32 |= (1 << 1);
2061         MCHBAR32(FSBPMC3) = reg32;
2062
2063         reg32 = MCHBAR32(SBTEST);
2064         reg32 |= (3 << 1);
2065         MCHBAR32(SBTEST) = reg32;
2066 }
2067
2068 static void sdram_pre_jedec_initialization(void)
2069 {
2070         u32 reg32;
2071
2072         reg32 = MCHBAR32(WCC);
2073         reg32 &= 0x113ff3ff;
2074         reg32 |= (4 << 29) | (3 << 25) | (1 << 10);
2075         MCHBAR32(WCC) = reg32;
2076
2077         MCHBAR32(SMVREFC) |= (1 << 6);
2078
2079         MCHBAR32(MMARB0) &= ~(3 << 17);
2080         MCHBAR32(MMARB0) |= (1 << 21) | (1 << 16);
2081
2082         MCHBAR32(MMARB1) &= ~(7 << 8);
2083         MCHBAR32(MMARB1) |= (3 << 8);
2084
2085         /* Adaptive Idle Timer Control */
2086         MCHBAR32(C0AIT) = 0x000006c4;
2087         MCHBAR32(C0AIT+4) = 0x871a066d;
2088
2089         MCHBAR32(C1AIT) = 0x000006c4;
2090         MCHBAR32(C1AIT+4) = 0x871a066d;
2091 }
2092
2093 #define EA_DUALCHANNEL_XOR_BANK_RANK_MODE       (0xd4 << 24)
2094 #define EA_DUALCHANNEL_XOR_BANK_MODE            (0xf4 << 24)
2095 #define EA_DUALCHANNEL_BANK_RANK_MODE           (0xc2 << 24)
2096 #define EA_DUALCHANNEL_BANK_MODE                (0xe2 << 24)
2097 #define EA_SINGLECHANNEL_XOR_BANK_RANK_MODE     (0x91 << 24)
2098 #define EA_SINGLECHANNEL_XOR_BANK_MODE          (0xb1 << 24)
2099 #define EA_SINGLECHANNEL_BANK_RANK_MODE         (0x80 << 24)
2100 #define EA_SINGLECHANNEL_BANK_MODE              (0xa0 << 24)
2101
2102 static void sdram_enhanced_addressing_mode(struct sys_info *sysinfo)
2103 {
2104         u32 chan0 = 0, chan1 = 0;
2105         int chan0_dualsided, chan1_dualsided, chan0_populated, chan1_populated;
2106
2107         chan0_populated =  (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED ||
2108                         sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED);
2109         chan1_populated = (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED ||
2110                         sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED);
2111         chan0_dualsided = (sysinfo->banksize[1] || sysinfo->banksize[3]);
2112         chan1_dualsided = (sysinfo->banksize[5] || sysinfo->banksize[7]);
2113
2114         if (sdram_capabilities_enhanced_addressing_xor()) {
2115                 if (!sysinfo->interleaved) {
2116                         /* Single Channel & Dual Channel Assymetric */
2117                         if (chan0_populated) {
2118                                 if (chan0_dualsided) {
2119                                         chan0 = EA_SINGLECHANNEL_XOR_BANK_RANK_MODE;
2120                                 } else {
2121                                         chan0 = EA_SINGLECHANNEL_XOR_BANK_MODE;
2122                                 }
2123                         }
2124                         if (chan1_populated) {
2125                                 if (chan1_dualsided) {
2126                                         chan1 = EA_SINGLECHANNEL_XOR_BANK_RANK_MODE;
2127                                 } else {
2128                                         chan1 = EA_SINGLECHANNEL_XOR_BANK_MODE;
2129                                 }
2130                         }
2131                 } else {
2132                         /* Interleaved has always both channels populated */
2133                         if (chan0_dualsided) {
2134                                 chan0 = EA_DUALCHANNEL_XOR_BANK_RANK_MODE;
2135                         } else {
2136                                 chan0 = EA_DUALCHANNEL_XOR_BANK_MODE;
2137                         }
2138
2139                         if (chan1_dualsided) {
2140                                 chan1 = EA_DUALCHANNEL_XOR_BANK_RANK_MODE;
2141                         } else {
2142                                 chan1 = EA_DUALCHANNEL_XOR_BANK_MODE;
2143                         }
2144                 }
2145         } else {
2146                 if (!sysinfo->interleaved) {
2147                         /* Single Channel & Dual Channel Assymetric */
2148                         if (chan0_populated) {
2149                                 if (chan0_dualsided) {
2150                                         chan0 = EA_SINGLECHANNEL_BANK_RANK_MODE;
2151                                 } else {
2152                                         chan0 = EA_SINGLECHANNEL_BANK_MODE;
2153                                 }
2154                         }
2155                         if (chan1_populated) {
2156                                 if (chan1_dualsided) {
2157                                         chan1 = EA_SINGLECHANNEL_BANK_RANK_MODE;
2158                                 } else {
2159                                         chan1 = EA_SINGLECHANNEL_BANK_MODE;
2160                                 }
2161                         }
2162                 } else {
2163                         /* Interleaved has always both channels populated */
2164                         if (chan0_dualsided) {
2165                                 chan0 = EA_DUALCHANNEL_BANK_RANK_MODE;
2166                         } else {
2167                                 chan0 = EA_DUALCHANNEL_BANK_MODE;
2168                         }
2169
2170                         if (chan1_dualsided) {
2171                                 chan1 = EA_DUALCHANNEL_BANK_RANK_MODE;
2172                         } else {
2173                                 chan1 = EA_DUALCHANNEL_BANK_MODE;
2174                         }
2175                 }
2176         }
2177
2178         MCHBAR32(C0DRC1) &= 0x00ffffff;
2179         MCHBAR32(C0DRC1) |= chan0;
2180         MCHBAR32(C1DRC1) &= 0x00ffffff;
2181         MCHBAR32(C1DRC1) |= chan1;
2182 }
2183
2184 static void sdram_post_jedec_initialization(struct sys_info *sysinfo)
2185 {
2186         u32 reg32;
2187
2188         /* Enable Channel XORing for Dual Channel Interleave */
2189         if (sysinfo->interleaved) {
2190
2191                 reg32 = MCHBAR32(DCC);
2192 #if CHANNEL_XOR_RANDOMIZATION
2193                 reg32 &= ~(1 << 10);
2194                 reg32 |= (1 << 9);
2195 #else
2196                 reg32 &= ~(1 << 9);
2197 #endif
2198                 MCHBAR32(DCC) = reg32;
2199         }
2200
2201         /* DRAM mode optimizations */
2202         sdram_enhanced_addressing_mode(sysinfo);
2203
2204         reg32 = MCHBAR32(FSBPMC3);
2205         reg32 &= ~(1 << 1);
2206         MCHBAR32(FSBPMC3) = reg32;
2207
2208         reg32 = MCHBAR32(SBTEST);
2209         reg32 &= ~(1 << 2);
2210         MCHBAR32(SBTEST) = reg32;
2211
2212         reg32 = MCHBAR32(SBOCC);
2213         reg32 &= 0xffbdb6ff;
2214         reg32 |= (0xbdb6 << 8) | (1 << 0);
2215         MCHBAR32(SBOCC) = reg32;
2216 }
2217
2218 static void sdram_power_management(struct sys_info *sysinfo)
2219 {
2220         u8 reg8;
2221         u16 reg16;
2222         u32 reg32;
2223         int integrated_graphics = 1;
2224         int i;
2225
2226         reg32 = MCHBAR32(C0DRT2);
2227         reg32 &= 0xffffff00;
2228         /* Idle timer = 8 clocks, CKE idle timer = 16 clocks */
2229         reg32 |= (1 << 5) | (1 << 4);
2230         MCHBAR32(C0DRT2) = reg32;
2231
2232         reg32 = MCHBAR32(C1DRT2);
2233         reg32 &= 0xffffff00;
2234         /* Idle timer = 8 clocks, CKE idle timer = 16 clocks */
2235         reg32 |= (1 << 5) | (1 << 4);
2236         MCHBAR32(C1DRT2) = reg32;
2237
2238         reg32 = MCHBAR32(C0DRC1);
2239
2240         reg32 |= (1 << 12) | (1 << 11);
2241         MCHBAR32(C0DRC1) = reg32;
2242
2243         reg32 = MCHBAR32(C1DRC1);
2244
2245         reg32 |= (1 << 12) | (1 << 11);
2246         MCHBAR32(C1DRC1) = reg32;
2247
2248         if (i945_silicon_revision()>1) {
2249                 /* FIXME bits 5 and 0 only if PCIe graphics is disabled */
2250                 u16 peg_bits = (1 << 5) | (1 << 0);
2251
2252                 MCHBAR16(UPMC1) = 0x1010 | peg_bits;
2253         } else {
2254                 /* FIXME bits 5 and 0 only if PCIe graphics is disabled */
2255                 u16 peg_bits = (1 << 5) | (1 << 0);
2256
2257                 /* Rev 0 and 1 */
2258                 MCHBAR16(UPMC1) = 0x0010 | peg_bits;
2259         }
2260
2261         reg16 = MCHBAR16(UPMC2);
2262         reg16 &= 0xfc00;
2263         reg16 |= 0x0100;
2264         MCHBAR16(UPMC2) = reg16;
2265
2266         MCHBAR32(UPMC3) = 0x000f06ff;
2267
2268         for (i=0; i<5; i++) {
2269                 MCHBAR32(UPMC3) &= ~(1 << 16);
2270                 MCHBAR32(UPMC3) |= (1 << 16);
2271         }
2272
2273         MCHBAR32(GIPMC1) = 0x8000000c;
2274
2275         reg16 = MCHBAR16(CPCTL);
2276         reg16 &= ~(7 << 11);
2277         if (i945_silicon_revision()>2) {
2278                 reg16 |= (6 << 11);
2279         } else {
2280                 reg16 |= (4 << 11);
2281         }
2282         MCHBAR16(CPCTL) = reg16;
2283
2284 #if 0
2285         if ((MCHBAR32(ECO) & (1 << 16)) != 0) {
2286 #else
2287         if (i945_silicon_revision() != 0) {
2288 #endif
2289                 switch (sysinfo->fsb_frequency) {
2290                 case 667: MCHBAR32(HGIPMC2) = 0x0d590d59; break;
2291                 case 533: MCHBAR32(HGIPMC2) = 0x155b155b; break;
2292                 }
2293         } else {
2294                 switch (sysinfo->fsb_frequency) {
2295                 case 667: MCHBAR32(HGIPMC2) = 0x09c409c4; break;
2296                 case 533: MCHBAR32(HGIPMC2) = 0x0fa00fa0; break;
2297                 }
2298         }
2299
2300         MCHBAR32(FSBPMC1) = 0x8000000c;
2301
2302         reg32 = MCHBAR32(C2C3TT);
2303         reg32 &= 0xffff0000;
2304         switch (sysinfo->fsb_frequency) {
2305         case 667: reg32 |= 0x0600; break;
2306         case 533: reg32 |= 0x0480; break;
2307         }
2308         MCHBAR32(C2C3TT) = reg32;
2309
2310         reg32 = MCHBAR32(C3C4TT);
2311         reg32 &= 0xffff0000;
2312         switch (sysinfo->fsb_frequency) {
2313         case 667: reg32 |= 0x0b80; break;
2314         case 533: reg32 |= 0x0980; break;
2315         }
2316         MCHBAR32(C3C4TT) = reg32;
2317
2318         if (i945_silicon_revision() == 0) {
2319                 MCHBAR32(ECO) &= ~(1 << 16);
2320         } else {
2321                 MCHBAR32(ECO) |= (1 << 16);
2322         }
2323
2324 #if 0
2325
2326         if (i945_silicon_revision() == 0) {
2327                 MCHBAR32(FSBPMC3) &= ~(1 << 29);
2328         } else {
2329                 MCHBAR32(FSBPMC3) |= (1 << 29);
2330         }
2331 #endif
2332         MCHBAR32(FSBPMC3) &= ~(1 << 29);
2333
2334         MCHBAR32(FSBPMC3) |= (1 << 21);
2335
2336         MCHBAR32(FSBPMC3) &= ~(1 << 19);
2337
2338         MCHBAR32(FSBPMC3) &= ~(1 << 13);
2339
2340         reg32 = MCHBAR32(FSBPMC4);
2341         reg32 &= ~(3 << 24);
2342         reg32 |= ( 2 << 24);
2343         MCHBAR32(FSBPMC4) = reg32;
2344
2345         MCHBAR32(FSBPMC4) |= (1 << 21);
2346
2347         MCHBAR32(FSBPMC4) |= (1 << 5);
2348
2349         if ((i945_silicon_revision() < 2) /* || cpuid() = 0x6e8 */ ) {
2350                 /* stepping 0 and 1 or CPUID 6e8 */
2351                 MCHBAR32(FSBPMC4) &= ~(1 << 4);
2352         } else {
2353                 MCHBAR32(FSBPMC4) |= (1 << 4);
2354         }
2355
2356         reg8 = pci_read_config8(PCI_DEV(0,0x0,0), 0xfc);
2357         reg8 |= (1 << 4);
2358         pci_write_config8(PCI_DEV(0, 0x0, 0), 0xfc, reg8);
2359
2360         reg8 = pci_read_config8(PCI_DEV(0,0x2,0), 0xc1);
2361         reg8 |= (1 << 2);
2362         pci_write_config8(PCI_DEV(0, 0x2, 0), 0xc1, reg8);
2363
2364 #if C2_SELF_REFRESH_DISABLE
2365
2366         if (integrated_graphics) {
2367                 printk_debug("C2 self-refresh with IGD\n");
2368                 MCHBAR16(MIPMC4) = 0x0468;
2369                 MCHBAR16(MIPMC5) = 0x046c;
2370                 MCHBAR16(MIPMC6) = 0x046c;
2371         } else {
2372                 MCHBAR16(MIPMC4) = 0x6468;
2373                 MCHBAR16(MIPMC5) = 0x646c;
2374                 MCHBAR16(MIPMC6) = 0x646c;
2375         }
2376 #else
2377         if (integrated_graphics) {
2378                 MCHBAR16(MIPMC4) = 0x04f8;
2379                 MCHBAR16(MIPMC5) = 0x04fc;
2380                 MCHBAR16(MIPMC6) = 0x04fc;
2381         } else {
2382                 MCHBAR16(MIPMC4) = 0x64f8;
2383                 MCHBAR16(MIPMC5) = 0x64fc;
2384                 MCHBAR16(MIPMC6) = 0x64fc;
2385         }
2386
2387 #endif
2388
2389         reg32 = MCHBAR32(PMCFG);
2390         reg32 &= ~(3 << 17);
2391         reg32 |= (2 << 17);
2392         MCHBAR32(PMCFG) = reg32;
2393
2394         MCHBAR32(PMCFG) |= (1 << 4);
2395
2396         reg32 = MCHBAR32(0xc30);
2397         reg32 &= 0xffffff00;
2398         reg32 |= 0x01;
2399         MCHBAR32(0xc30) = reg32;
2400
2401         MCHBAR32(0xb18) &= ~(1 << 21);
2402 }
2403
2404 static void sdram_thermal_management(void)
2405 {
2406
2407         MCHBAR8(TCO1) = 0x00;
2408         MCHBAR8(TCO0) = 0x00;
2409
2410         /* The Thermal Sensors for DIMMs at 0x50, 0x52 are at I2C addr
2411          * 0x30/0x32.
2412          */
2413
2414 }
2415
2416 static void sdram_save_receive_enable(void)
2417 {
2418         int i;
2419         u32 reg32;
2420         u8 values[4];
2421
2422         /* The following values are stored to an unused CMOS
2423          * area and restored instead of recalculated in case
2424          * of an S3 resume.
2425          *
2426          * C0WL0REOST [7:0]             -> 8 bit
2427          * C1WL0REOST [7:0]             -> 8 bit
2428          * RCVENMT    [11:8] [3:0]      -> 8 bit
2429          * C0DRT1     [27:24]           -> 4 bit
2430          * C1DRT1     [27:24]           -> 4 bit
2431          */
2432
2433         values[0] = MCHBAR8(C0WL0REOST);
2434         values[1] = MCHBAR8(C1WL0REOST);
2435
2436         reg32 = MCHBAR32(RCVENMT);
2437         values[2] = (u8)((reg32 >> (8 - 4)) & 0xf0) | (reg32 & 0x0f);
2438
2439         reg32 = MCHBAR32(C0DRT1);
2440         values[3] = (reg32 >> 24) & 0x0f;
2441         reg32 = MCHBAR32(C1DRT1);
2442         values[3] |= (reg32 >> (24 - 4)) & 0xf0;
2443
2444         /* coreboot only uses bytes 0 - 127 for its CMOS values so far
2445          * so we grad bytes 128 - 131 to save the receive enable values
2446          */
2447
2448         for (i=0; i<4; i++)
2449                 cmos_write(values[i], 128 + i);
2450 }
2451
2452 static void sdram_recover_receive_enable(void)
2453 {
2454         int i;
2455         u32 reg32;
2456         u8 values[4];
2457
2458         for (i=0; i<4; i++)
2459                 values[i] = cmos_read(128 + i);
2460
2461         MCHBAR8(C0WL0REOST) = values[0];
2462         MCHBAR8(C1WL0REOST) = values[1];
2463
2464         reg32 = MCHBAR32(RCVENMT);
2465         reg32 &= ~((0x0f << 8) | (0x0f << 0));
2466         reg32 |= ((u32)(values[2] & 0xf0) << (8 - 4)) | (values[2] & 0x0f);
2467         MCHBAR32(RCVENMT) = reg32;
2468
2469         reg32 = MCHBAR32(C0DRT1) & ~(0x0f << 24);
2470         reg32 |= (u32)(values[3] & 0x0f) << 24;
2471         MCHBAR32(C0DRT1) = reg32;
2472
2473         reg32 = MCHBAR32(C1DRT1) & ~(0x0f << 24);
2474         reg32 |= (u32)(values[3] & 0xf0) << (24 - 4);
2475         MCHBAR32(C1DRT1) = reg32;
2476 }
2477
2478 #include "rcven.c"
2479
2480 static void sdram_program_receive_enable(struct sys_info *sysinfo)
2481 {
2482         MCHBAR32(REPC) |= (1 << 0);
2483
2484         /* enable upper CMOS */
2485         RCBA32(0x3400) = (1 << 2);
2486
2487         /* Program Receive Enable Timings */
2488         if (sysinfo->boot_path == BOOT_PATH_RESUME) {
2489                 sdram_recover_receive_enable();
2490         } else {
2491                 receive_enable_adjust(sysinfo);
2492                 sdram_save_receive_enable();
2493         }
2494
2495         MCHBAR32(C0DRC1) |= (1 << 6);
2496         MCHBAR32(C1DRC1) |= (1 << 6);
2497         MCHBAR32(C0DRC1) &= ~(1 << 6);
2498         MCHBAR32(C1DRC1) &= ~(1 << 6);
2499
2500         MCHBAR32(MIPMC3) |= (0x0f << 0);
2501 }
2502
2503 /**
2504  * @brief Enable On-Die Termination for DDR2.
2505  *
2506  */
2507
2508 static void sdram_on_die_termination(struct sys_info *sysinfo)
2509 {
2510         static const u32 odt[] = {
2511                 0x00024911, 0xe0010000,
2512                 0x00049211, 0xe0020000,
2513                 0x0006db11, 0xe0030000,
2514         };
2515
2516         u32 reg32;
2517         int cas;
2518
2519         reg32 = MCHBAR32(ODTC);
2520         reg32 &= ~(3 << 16);
2521         reg32 |= (1 << 14) | (1 << 6) | (2 << 16);
2522         MCHBAR32(ODTC) = reg32;
2523
2524         if ( !(sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED &&
2525                         sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED) ) {
2526                 printk_debug("one dimm per channel config.. \n");
2527
2528                 reg32 = MCHBAR32(C0ODT);
2529                 reg32 &= ~(7 << 28);
2530                 MCHBAR32(C0ODT) = reg32;
2531                 reg32 = MCHBAR32(C1ODT);
2532                 reg32 &= ~(7 << 28);
2533                 MCHBAR32(C1ODT) = reg32;
2534         }
2535
2536         cas = sysinfo->cas;
2537
2538         reg32 = MCHBAR32(C0ODT) & 0xfff00000;
2539         reg32 |= odt[(cas-3) * 2];
2540         MCHBAR32(C0ODT) = reg32;
2541
2542         reg32 = MCHBAR32(C1ODT) & 0xfff00000;
2543         reg32 |= odt[(cas-3) * 2];
2544         MCHBAR32(C1ODT) = reg32;
2545
2546         reg32 = MCHBAR32(C0ODT + 4) & 0x1fc8ffff;
2547         reg32 |= odt[((cas-3) * 2) + 1];
2548         MCHBAR32(C0ODT + 4) = reg32;
2549
2550         reg32 = MCHBAR32(C1ODT + 4) & 0x1fc8ffff;
2551         reg32 |= odt[((cas-3) * 2) + 1];
2552         MCHBAR32(C1ODT + 4) = reg32;
2553 }
2554
2555 /**
2556  * @brief Enable clocks to populated sockets
2557  */
2558
2559 static void sdram_enable_memory_clocks(struct sys_info *sysinfo)
2560 {
2561         u8 clocks[2] = { 0, 0 };
2562
2563         if (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED)
2564                 clocks[0] |= (1 << 0) | (1 << 1);
2565
2566         if (sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED)
2567                 clocks[0] |= (1 << 2) | (1 << 3);
2568
2569         if (sysinfo->dimm[2] != SYSINFO_DIMM_NOT_POPULATED)
2570                 clocks[1] |= (1 << 0) | (1 << 1);
2571
2572         if (sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED)
2573                 clocks[1] |= (1 << 2) | (1 << 3);
2574
2575 #ifdef OVERRIDE_CLOCK_DISABLE
2576         /* Usually system firmware turns off system memory clock signals
2577          * to unused SO-DIMM slots to reduce EMI and power consumption.
2578          * However, the Kontron 986LCD-M does not like unused clock
2579          * signals to be disabled.
2580          * If other similar mainboard occur, it would make sense to make
2581          * this an entry in the sysinfo structure, and pre-initialize that
2582          * structure in the mainboard's auto.c main() function.
2583          * For now an #ifdef will do.
2584          */
2585
2586         clocks[0] = 0xf; /* force all clock gate pairs to enable */
2587         clocks[1] = 0xf; /* force all clock gate pairs to enable */
2588 #endif
2589
2590         MCHBAR8(C0DCLKDIS) = clocks[0];
2591         MCHBAR8(C1DCLKDIS) = clocks[1];
2592 }
2593
2594 #define RTT_ODT_NONE    0
2595 #define RTT_ODT_50_OHM  ( (1 << 9) | (1 << 5) )
2596 #define RTT_ODT_75_OHM  (1 << 5)
2597 #define RTT_ODT_150_OHM (1 << 9)
2598
2599 #define EMRS_OCD_DEFAULT        ( (1 << 12) | (1 << 11) | (1 << 10) )
2600
2601 #define MRS_CAS_3       (3 << 7)
2602 #define MRS_CAS_4       (4 << 7)
2603 #define MRS_CAS_5       (5 << 7)
2604
2605 #define MRS_TWR_3       (2 << 12)
2606 #define MRS_TWR_4       (3 << 12)
2607 #define MRS_TWR_5       (4 << 12)
2608
2609 #define MRS_BT          (1 << 6)
2610
2611 #define MRS_BL4         (2 << 3)
2612 #define MRS_BL8         (3 << 3)
2613
2614 static void sdram_jedec_enable(struct sys_info *sysinfo)
2615 {
2616         int i, nonzero;
2617         u32 bankaddr = 0, tmpaddr, mrsaddr = 0;
2618
2619         for (i = 0, nonzero = -1; i < 8; i++) {
2620                 if (sysinfo->banksize[i]  == 0) {
2621                         continue;
2622                 }
2623
2624                 printk_debug("jedec enable sequence: bank %d\n", i);
2625                 switch (i) {
2626                 case 0:
2627                         /* Start at address 0 */
2628                         bankaddr = 0;
2629                         break;
2630                 case 4:
2631                         if (sysinfo->interleaved) {
2632                                 bankaddr = 0x40;
2633                                 break;
2634                         }
2635                 default:
2636                         if (nonzero != -1) {
2637                                 printk_debug("bankaddr from bank size of rank %d\n", nonzero);
2638                                 bankaddr += sysinfo->banksize[nonzero] <<
2639                                         (sysinfo->interleaved ? 26 : 25);
2640                                 break;
2641                         }
2642                         /* No populated bank hit before. Start at address 0 */
2643                         bankaddr = 0;
2644                 }
2645
2646                 /* We have a bank with a non-zero size.. Remember it
2647                  * for the next offset we have to calculate
2648                  */
2649                 nonzero = i;
2650
2651                 /* Get CAS latency set up */
2652                 switch (sysinfo->cas) {
2653                 case 5: mrsaddr = MRS_CAS_5; break;
2654                 case 4: mrsaddr = MRS_CAS_4; break;
2655                 case 3: mrsaddr = MRS_CAS_3; break;
2656                 default: die("Jedec Error (CAS).\n");
2657                 }
2658
2659                 /* Get tWR set */
2660                 switch (sysinfo->twr) {
2661                 case 5: mrsaddr |= MRS_TWR_5; break;
2662                 case 4: mrsaddr |= MRS_TWR_4; break;
2663                 case 3: mrsaddr |= MRS_TWR_3; break;
2664                 default: die("Jedec Error (tWR).\n");
2665                 }
2666
2667                 /* Set "Burst Type" */
2668                 mrsaddr |= MRS_BT;
2669
2670                 /* Interleaved */
2671                 if (sysinfo->interleaved) {
2672                         mrsaddr = mrsaddr << 1;
2673                 }
2674
2675                 /* Only burst length 8 supported */
2676                 mrsaddr |= MRS_BL8;
2677
2678                 /* Apply NOP */
2679                 PRINTK_DEBUG("Apply NOP\n");
2680                 do_ram_command(RAM_COMMAND_NOP);
2681                 ram_read32(bankaddr);
2682
2683                 /* Precharge all banks */
2684                 PRINTK_DEBUG("All Banks Precharge\n");
2685                 do_ram_command(RAM_COMMAND_PRECHARGE);
2686                 ram_read32(bankaddr);
2687
2688                 /* Extended Mode Register Set (2) */
2689                 PRINTK_DEBUG("Extended Mode Register Set(2)\n");
2690                 do_ram_command(RAM_COMMAND_EMRS | RAM_EMRS_2);
2691                 ram_read32(bankaddr);
2692
2693                 /* Extended Mode Register Set (3) */
2694                 PRINTK_DEBUG("Extended Mode Register Set(3)\n");
2695                 do_ram_command(RAM_COMMAND_EMRS | RAM_EMRS_3);
2696                 ram_read32(bankaddr);
2697
2698                 /* Extended Mode Register Set */
2699                 PRINTK_DEBUG("Extended Mode Register Set\n");
2700                 do_ram_command(RAM_COMMAND_EMRS | RAM_EMRS_1);
2701                 tmpaddr = bankaddr;
2702                 if (!sdram_capabilities_dual_channel()) {
2703                         tmpaddr |= RTT_ODT_75_OHM;
2704                 } else if (sysinfo->interleaved) {
2705                         tmpaddr |= (RTT_ODT_150_OHM << 1);
2706                 } else {
2707                         tmpaddr |= RTT_ODT_150_OHM;
2708                 }
2709                 ram_read32(tmpaddr);
2710
2711                 /* Mode Register Set: Reset DLLs */
2712                 PRINTK_DEBUG("MRS: Reset DLLs\n");
2713                 do_ram_command(RAM_COMMAND_MRS);
2714                 tmpaddr = bankaddr;
2715                 tmpaddr |= mrsaddr;
2716                 /* Set DLL reset bit */
2717                 if (sysinfo->interleaved)
2718                         tmpaddr |= (1 << 12);
2719                 else
2720                         tmpaddr |= (1 << 11);
2721                 ram_read32(tmpaddr);
2722
2723                 /* Precharge all banks */
2724                 PRINTK_DEBUG("All Banks Precharge\n");
2725                 do_ram_command(RAM_COMMAND_PRECHARGE);
2726                 ram_read32(bankaddr);
2727
2728                 /* CAS before RAS Refresh */
2729                 PRINTK_DEBUG("CAS before RAS\n");
2730                 do_ram_command(RAM_COMMAND_CBR);
2731
2732                 /* CBR wants two READs */
2733                 ram_read32(bankaddr);
2734                 ram_read32(bankaddr);
2735
2736                 /* Mode Register Set: Enable DLLs */
2737                 PRINTK_DEBUG("MRS: Enable DLLs\n");
2738                 do_ram_command(RAM_COMMAND_MRS);
2739
2740                 tmpaddr = bankaddr;
2741                 tmpaddr |= mrsaddr;
2742                 ram_read32(tmpaddr);
2743
2744                 /* Extended Mode Register Set */
2745                 PRINTK_DEBUG("Extended Mode Register Set: ODT/OCD\n");
2746                 do_ram_command(RAM_COMMAND_EMRS | RAM_EMRS_1);
2747
2748                 tmpaddr = bankaddr;
2749                 if (!sdram_capabilities_dual_channel()) {
2750
2751                         tmpaddr |= RTT_ODT_75_OHM | EMRS_OCD_DEFAULT;
2752                 } else if (sysinfo->interleaved) {
2753                         tmpaddr |= ((RTT_ODT_150_OHM | EMRS_OCD_DEFAULT) << 1);
2754                 } else {
2755                         tmpaddr |= RTT_ODT_150_OHM | EMRS_OCD_DEFAULT;
2756                 }
2757                 ram_read32(tmpaddr);
2758
2759                 /* Extended Mode Register Set */
2760                 PRINTK_DEBUG("Extended Mode Register Set: OCD Exit\n");
2761                 do_ram_command(RAM_COMMAND_EMRS | RAM_EMRS_1);
2762
2763                 tmpaddr = bankaddr;
2764                 if (!sdram_capabilities_dual_channel()) {
2765                         tmpaddr |= RTT_ODT_75_OHM;
2766                 } else if (sysinfo->interleaved) {
2767                         tmpaddr |= (RTT_ODT_150_OHM << 1);
2768                 } else {
2769                         tmpaddr |= RTT_ODT_150_OHM;
2770                 }
2771                 ram_read32(tmpaddr);
2772         }
2773 }
2774
2775 static void sdram_init_complete(void)
2776 {
2777         PRINTK_DEBUG("Normal Operation\n");
2778         do_ram_command(RAM_COMMAND_NORMAL);
2779 }
2780
2781 static void sdram_setup_processor_side(void)
2782 {
2783         if (i945_silicon_revision() == 0)
2784                 MCHBAR32(FSBPMC3) |= (1 << 2);
2785
2786         MCHBAR8(0xb00) |= 1;
2787
2788         if (i945_silicon_revision() == 0)
2789                 MCHBAR32(SLPCTL) |= (1 << 8);
2790 }
2791
2792 /**
2793  * @param boot_path: 0 = normal, 1 = reset, 2 = resume from s3
2794  */
2795 void sdram_initialize(int boot_path)
2796 {
2797         struct sys_info sysinfo;
2798         u8 reg8, cas_mask;
2799
2800         sdram_detect_errors();
2801
2802         printk_debug ("Setting up RAM controller.\n");
2803
2804         memset(&sysinfo, 0, sizeof(sysinfo));
2805
2806         sysinfo.boot_path = boot_path;
2807
2808         /* Look at the type of DIMMs and verify all DIMMs are x8 or x16 width */
2809         sdram_get_dram_configuration(&sysinfo);
2810
2811         /* Check whether we have stacked DIMMs */
2812         sdram_verify_package_type(&sysinfo);
2813
2814         /* Determine common CAS */
2815         cas_mask = sdram_possible_cas_latencies(&sysinfo);
2816
2817         /* Choose Common Frequency */
2818         sdram_detect_cas_latency_and_ram_speed(&sysinfo, cas_mask);
2819
2820         /* Determine smallest common tRAS */
2821         sdram_detect_smallest_tRAS(&sysinfo);
2822
2823         /* Determine tRP */
2824         sdram_detect_smallest_tRP(&sysinfo);
2825
2826         /* Determine tRCD */
2827         sdram_detect_smallest_tRCD(&sysinfo);
2828
2829         /* Determine smallest refresh period */
2830         sdram_detect_smallest_refresh(&sysinfo);
2831
2832         /* Verify all DIMMs support burst length 8 */
2833         sdram_verify_burst_length(&sysinfo);
2834
2835         /* determine tWR */
2836         sdram_detect_smallest_tWR(&sysinfo);
2837
2838         /* Determine DIMM size parameters (rows, columns banks) */
2839         sdram_detect_dimm_size(&sysinfo);
2840
2841         /* determine tRFC */
2842         sdram_detect_smallest_tRFC(&sysinfo);
2843
2844         /* Program PLL settings */
2845         sdram_program_pll_settings(&sysinfo);
2846
2847         /* Program Graphics Frequency */
2848         sdram_program_graphics_frequency(&sysinfo);
2849
2850         /* Program System Memory Frequency */
2851         sdram_program_memory_frequency(&sysinfo);
2852
2853         /* Determine Mode of Operation (Interleaved etc) */
2854         sdram_set_channel_mode(&sysinfo);
2855
2856         /* Program Clock Crossing values */
2857         sdram_program_clock_crossing();
2858
2859         /* Disable fast dispatch */
2860         sdram_disable_fast_dispatch();
2861
2862         /* Enable WIODLL Power Down in ACPI states */
2863         MCHBAR32(C0DMC) |= (1 << 24);
2864         MCHBAR32(C1DMC) |= (1 << 24);
2865
2866         /* Program DRAM Row Boundary/Attribute Registers */
2867
2868         /* program row size DRB and set TOLUD */
2869         sdram_program_row_boundaries(&sysinfo);
2870
2871         /* program page size DRA */
2872         sdram_set_row_attributes(&sysinfo);
2873
2874         /* Program CxBNKARC */
2875         sdram_set_bank_architecture(&sysinfo);
2876
2877         /* Program DRAM Timing and Control registers based on SPD */
2878         sdram_set_timing_and_control(&sysinfo);
2879
2880         /* On-Die Termination Adjustment */
2881         sdram_on_die_termination(&sysinfo);
2882
2883         /* Pre Jedec Initialization */
2884         sdram_pre_jedec_initialization();
2885
2886         /* Perform System Memory IO Initialization */
2887         sdram_initialize_system_memory_io(&sysinfo);
2888
2889         /* Perform System Memory IO Buffer Enable */
2890         sdram_enable_system_memory_io(&sysinfo);
2891
2892         /* Enable System Memory Clocks */
2893         sdram_enable_memory_clocks(&sysinfo);
2894
2895         if (boot_path == BOOT_PATH_NORMAL) {
2896                 /* Jedec Initialization sequence */
2897                 sdram_jedec_enable(&sysinfo);
2898         }
2899
2900         /* Program Power Management Registers */
2901         sdram_power_management(&sysinfo);
2902
2903         /* Post Jedec Init */
2904         sdram_post_jedec_initialization(&sysinfo);
2905
2906         /* Program DRAM Throttling */
2907         sdram_thermal_management();
2908
2909         /* Normal Operations */
2910         sdram_init_complete();
2911
2912         /* Program Receive Enable Timings */
2913         sdram_program_receive_enable(&sysinfo);
2914
2915         /* Enable Periodic RCOMP */
2916         sdram_enable_rcomp();
2917
2918         /* Tell ICH7 that we're done */
2919         reg8 = pci_read_config8(PCI_DEV(0,0x1f,0), 0xa2);
2920         reg8 &= ~(1 << 7);
2921         pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8);
2922
2923         printk_debug("RAM initialization finished.\n");
2924
2925         sdram_setup_processor_side();
2926 }
2927
2928 unsigned long get_top_of_ram(void)
2929 {
2930         /* This will not work if TSEG is in place! */
2931         u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c);
2932
2933         return (unsigned long) tom;
2934 }
2935