src/northbridge/intel/i945/raminit.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007-2008 coresystems GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18  */
  19
  20
  21 #include <cpu/x86/mem.h>
  22 #include <cpu/x86/mtrr.h>
  23 #include <cpu/x86/cache.h>
  24 #include <spd.h>
  25 #include "raminit.h"
  26 #include "i945.h"
  27
  28 #define DEBUG_RAM_SETUP
  29
  30 /* Debugging macros. */
  31 #if defined(DEBUG_RAM_SETUP)
  32 #define PRINTK_DEBUG(x...)      printk_debug(x)
  33 #else
  34 #define PRINTK_DEBUG(x...)
  35 #endif
  36
  37
  38 #define RAM_INITIALIZATION_COMPLETE     (1 << 19)
  39
  40 #define RAM_COMMAND_SELF_REFRESH        (0x0 << 16)
  41 #define RAM_COMMAND_NOP                 (0x1 << 16)
  42 #define RAM_COMMAND_PRECHARGE           (0x2 << 16)
  43 #define RAM_COMMAND_MRS                 (0x3 << 16)
  44 #define RAM_COMMAND_EMRS                (0x4 << 16)
  45 #define RAM_COMMAND_CBR                 (0x6 << 16)
  46 #define RAM_COMMAND_NORMAL              (0x7 << 16)
  47
  48 #define RAM_EMRS_1                      (0x0 << 21)
  49 #define RAM_EMRS_2                      (0x1 << 21)
  50 #define RAM_EMRS_3                      (0x2 << 21)
  51
  52 static void do_ram_command(u32 command)
  53 {
  54         u32 reg32;
  55
  56         reg32 = MCHBAR32(DCC);
  57         reg32 &= ~( (3<<21) | (1<<20) | (1<<19) | (7 << 16) );
  58         reg32 |= command;
  59
  60         /* Also set Init Complete */
  61         if (command == RAM_COMMAND_NORMAL)
  62                 reg32 |= RAM_INITIALIZATION_COMPLETE;
  63
  64         PRINTK_DEBUG("   Sending RAM command 0x%08x", reg32);
  65
  66         MCHBAR32(DCC) = reg32;  /* This is the actual magic */
  67
  68         PRINTK_DEBUG("...done\n");
  69 }
  70
  71
  72 static void ram_read32(u32 offset)
  73 {
  74         PRINTK_DEBUG("   ram read: %08x\n", offset);
  75
  76         read32(offset);
  77 }
  78
  79 #ifdef DEBUG_RAM_SETUP
  80 static void sdram_dump_mchbar_registers(void)
  81 {
  82         int i;
  83         printk_debug("Dumping MCHBAR Registers\n");
  84
  85         for (i=0; i<0xfff; i+=4) {
  86                 if (MCHBAR32(i) == 0)
  87                         continue;
  88                 printk_debug("0x%04x: 0x%08x\n", i, MCHBAR32(i));
  89         }
  90 }
  91 #endif
  92
  93 static int sdram_capabilities_max_supported_memory_frequency(void)
  94 {
  95         u32 reg32;
  96
  97         reg32 = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xe4);
  98         reg32 &= (7 << 0);
  99
 100         switch (reg32) {
 101         case 4: return 400;
 102         case 3: return 533;
 103         case 2: return 667;
 104         }
 105         /* Newer revisions of this chipset rather support faster memory clocks,
 106          * so if it's a reserved value, return the fastest memory clock that we
 107          * know of and can handle
 108          */
 109         return 667;
 110 }
 111
 112 /**
 113  * @brief determine whether chipset is capable of dual channel interleaved mode
 114  *
 115  * @return 1 if interleaving is supported, 0 otherwise
 116  */
 117 static int sdram_capabilities_interleave(void)
 118 {
 119         u32 reg32;
 120
 121         reg32 = pci_read_config8(PCI_DEV(0, 0x00,0), 0xe4);
 122         reg32 >>= 25;
 123         reg32 &= 1;
 124
 125         return (!reg32);
 126 }
 127
 128 /**
 129  * @brief determine whether chipset is capable of two memory channels
 130  *
 131  * @return 1 if dual channel operation is supported, 0 otherwise
 132  */
 133 static int sdram_capabilities_dual_channel(void)
 134 {
 135         u32 reg32;
 136
 137         reg32 = pci_read_config8(PCI_DEV(0, 0x00,0), 0xe4);
 138         reg32 >>= 24;
 139         reg32 &= 1;
 140
 141         return (!reg32);
 142 }
 143
 144 static int sdram_capabilities_enhanced_addressing_xor(void)
 145 {
 146         u8 reg8;
 147
 148         reg8 = pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe5); /* CAPID0 + 5 */
 149         reg8 &= (1 << 7);
 150
 151         return (!reg8);
 152 }
 153
 154 static int sdram_capabilities_two_dimms_per_channel(void)
 155 {
 156         u8 reg8;
 157
 158         reg8 = pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe8); /* CAPID0 + 8 */
 159         reg8 &= (1 << 0);
 160
 161         return (reg8 != 0);
 162 }
 163
 164 static int sdram_capabilities_MEM4G_disable(void)
 165 {
 166         u8 reg8;
 167
 168         reg8 = pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe5);
 169         reg8 &= (1 << 0);
 170
 171         return (reg8 != 0);
 172 }
 173
 174 static void sdram_detect_errors(void)
 175 {
 176         u8 reg8;
 177
 178         reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2);
 179
 180         if (reg8 & ((1<<7)|(1<<2))) {
 181                 if (reg8 & (1<<2)) {
 182                         printk_debug("SLP S4# Assertion Width Violation.\n");
 183
 184                         pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8);
 185                 }
 186
 187                 if (reg8 & (1<<7)) {
 188                         printk_debug("DRAM initialization was interrupted.\n");
 189                         reg8 &= ~(1<<7);
 190                         pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8);
 191                 }
 192
 193                 /* Set SLP_S3# Assertion Stretch Enable */
 194                 reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); /* GEN_PMCON_3 */
 195                 reg8 |= (1 << 3);
 196                 pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8);
 197
 198                 printk_debug("Reset required.\n");
 199                 outb(0x00, 0xcf9);
 200                 outb(0x0e, 0xcf9);
 201                 for (;;) ; /* Wait for reset! */
 202         }
 203
 204         /* Set DRAM initialization bit in ICH7 */
 205         reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2);
 206         reg8 |= (1<<7);
 207         pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8);
 208
 209 }
 210
 211
 212 /**
 213  * @brief Get generic DIMM parameters.
 214  * @param sysinfo Central memory controller information structure
 215  *
 216  * This function gathers several pieces of information for each system DIMM:
 217  *  o DIMM width (x8 / x16)
 218  *  o DIMM sides (single sided / dual sided)
 219  *
 220  *  Also, some non-supported scenarios are detected.
 221  */
 222
 223 static void sdram_get_dram_configuration(struct sys_info *sysinfo)
 224 {
 225         u32 dimm_mask = 0;
 226         int i;
 227
 228         /**
 229          * i945 supports two DIMMs, in two configurations:
 230          *
 231          * - single channel with two dimms
 232          * - dual channel with one dimm per channel
 233          *
 234          * In practice dual channel mainboards have their spd at 0x50, 0x52
 235          * whereas single channel configurations have their spd at 0x50/x51
 236          *
 237          * The capability register knows a lot about the channel configuration
 238          * but for now we stick with the information we gather from the SPD
 239          * ROMs
 240          */
 241
 242         if (sdram_capabilities_dual_channel()) {
 243                 sysinfo->dual_channel = 1;
 244                 printk_debug("This mainboard supports Dual Channel Operation.\n");
 245         } else {
 246                 sysinfo->dual_channel = 0;
 247                 printk_debug("This mainboard supports only Single Channel Operation.\n");
 248         }
 249
 250         /**
 251          * Since we only support two DIMMs in total, there is a limited number
 252          * of combinations. This function returns the type of DIMMs.
 253          * return value:
 254          *   [0:7]  lower DIMM population
 255          *   [8-15] higher DIMM population
 256          *   [16]   dual channel?
 257          *
 258          * There are 5 different possible populations for a DIMM socket:
 259          * 1. x16 double sided (X16DS)
 260          * 2. x8 double sided  (X8DS)
 261          * 3. x16 single sided (X16SS)
 262          * 4. x8 double stacked (X8DDS)
 263          * 5. not populated (NC)
 264          *
 265          * For the return value we start counting at zero.
 266          *
 267          */
 268
 269         for (i=0; i<(2 * DIMM_SOCKETS); i++) {
 270                 u8 reg8, device = DIMM_SPD_BASE + i;
 271
 272                 /* Initialize the socket information with a sane value */
 273                 sysinfo->dimm[i] = SYSINFO_DIMM_NOT_POPULATED;
 274
 275                 if (!sdram_capabilities_dual_channel() && (i >> 1))
 276                         continue;
 277                 if (!sdram_capabilities_two_dimms_per_channel() && (i& 1))
 278                         continue;
 279
 280                 printk_debug("DDR II Channel %d Socket %d: ", (i >> 1), (i & 1));
 281
 282                 if (spd_read_byte(device, SPD_MEMORY_TYPE) != SPD_MEMORY_TYPE_SDRAM_DDR2) {
 283                         printk_debug("N/A\n");
 284                         continue;
 285                 }
 286
 287                 reg8 = spd_read_byte(device, SPD_DIMM_CONFIG_TYPE);
 288                 if (reg8 == ERROR_SCHEME_ECC)
 289                         die("Error: ECC memory not supported by this chipset\n");
 290
 291                 reg8 = spd_read_byte(device, SPD_MODULE_ATTRIBUTES);
 292                 if (reg8 & MODULE_BUFFERED)
 293                         die("Error: Buffered memory not supported by this chipset\n");
 294                 if (reg8 & MODULE_REGISTERED)
 295                         die("Error: Registered memory not supported by this chipset\n");
 296
 297                 switch (spd_read_byte(device, SPD_PRIMARY_SDRAM_WIDTH)) {
 298                 case 0x08:
 299                         switch (spd_read_byte(device, SPD_NUM_DIMM_BANKS) & 0x0f) {
 300                         case 1:
 301                                 printk_debug("x8DDS\n");
 302                                 sysinfo->dimm[i] = SYSINFO_DIMM_X8DDS;
 303                                 break;
 304                         case 0:
 305                                 printk_debug("x8DS\n");
 306                                 sysinfo->dimm[i] = SYSINFO_DIMM_X8DS;
 307                                 break;
 308                         default:
 309                                 printk_debug ("Unsupported.\n");
 310                         }
 311                         break;
 312                 case 0x10:
 313                         switch (spd_read_byte(device, SPD_NUM_DIMM_BANKS) & 0x0f) {
 314                         case 1:
 315                                 printk_debug("x16DS\n");
 316                                 sysinfo->dimm[i] = SYSINFO_DIMM_X16DS;
 317                                 break;
 318                         case 0:
 319                                 printk_debug("x16SS\n");
 320                                 sysinfo->dimm[i] = SYSINFO_DIMM_X16SS;
 321                                 break;
 322                         default:
 323                                 printk_debug ("Unsupported.\n");
 324                         }
 325                         break;
 326                 default:
 327                         die("Unsupported DDR-II memory width.\n");
 328                 }
 329
 330                 dimm_mask |= (1 << i);
 331         }
 332
 333         if (!dimm_mask) {
 334                 die("No memory installed.\n");
 335         }
 336
 337         /* The chipset might be able to do this. What the heck, legacy bios
 338          * just beeps when a single DIMM is in the Channel 1 socket. So let's
 339          * not bother until someone needs this enough to cope with it.
 340          */
 341         if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) {
 342                 printk_err("Channel 0 has no memory populated. This setup is not usable. Please move the DIMM.\n");
 343         }
 344 }
 345
 346 /**
 347  * @brief determine if any DIMMs are stacked
 348  *
 349  * @param sysinfo central sysinfo data structure.
 350  */
 351 static void sdram_verify_package_type(struct sys_info * sysinfo)
 352 {
 353         int i;
 354
 355         /* Assume no stacked DIMMs are available until we find one */
 356         sysinfo->package = 0;
 357         for (i=0; i<2*DIMM_SOCKETS; i++) {
 358                 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
 359                         continue;
 360
 361                 /* Is the current DIMM a stacked DIMM? */
 362                 if (spd_read_byte(DIMM_SPD_BASE + i, SPD_NUM_DIMM_BANKS) & (1 << 4))
 363                         sysinfo->package = 1;
 364         }
 365 }
 366
 367 static u8 sdram_possible_cas_latencies(struct sys_info * sysinfo)
 368 {
 369         int i;
 370         u8 cas_mask;
 371
 372         /* Setup CAS mask with all supported CAS Latencies */
 373         cas_mask = SPD_CAS_LATENCY_DDR2_3 |
 374                    SPD_CAS_LATENCY_DDR2_4 |
 375                    SPD_CAS_LATENCY_DDR2_5;
 376
 377         for (i=0; i<2*DIMM_SOCKETS; i++) {
 378                 if (sysinfo->dimm[i] != SYSINFO_DIMM_NOT_POPULATED)
 379                         cas_mask &= spd_read_byte(DIMM_SPD_BASE + i, SPD_ACCEPTABLE_CAS_LATENCIES);
 380         }
 381
 382         if(!cas_mask) {
 383                 die("No DDR-II modules with accepted CAS latencies found.\n");
 384         }
 385
 386         return cas_mask;
 387 }
 388
 389 static void sdram_detect_cas_latency_and_ram_speed(struct sys_info * sysinfo, u8 cas_mask)
 390 {
 391         int i, j, idx;
 392         int lowest_common_cas = 0;
 393         int max_ram_speed;
 394
 395         const u8 ddr2_speeds_table[] = {
 396                 0x50, 0x60,     /* DDR2 400: tCLK = 5.0ns  tAC = 0.6ns  */
 397                 0x3d, 0x50,     /* DDR2 533: tCLK = 3.75ns tAC = 0.5ns  */
 398                 0x30, 0x45,     /* DDR2 667: tCLK = 3.0ns  tAC = 0.45ns */
 399         };
 400
 401         const u8 spd_lookup_table[] = {
 402                 SPD_MIN_CYCLE_TIME_AT_CAS_MAX,  SPD_ACCESS_TIME_FROM_CLOCK,
 403                 SPD_SDRAM_CYCLE_TIME_2ND,       SPD_ACCESS_TIME_FROM_CLOCK_2ND,
 404                 SPD_SDRAM_CYCLE_TIME_3RD,       SPD_ACCESS_TIME_FROM_CLOCK_3RD
 405         };
 406
 407         switch (sdram_capabilities_max_supported_memory_frequency()) {
 408         case 400: max_ram_speed = 0; break;
 409         case 533: max_ram_speed = 1; break;
 410         case 667: max_ram_speed = 2; break;
 411         }
 412
 413         sysinfo->memory_frequency = 0;
 414         sysinfo->cas = 0;
 415
 416         if (cas_mask & SPD_CAS_LATENCY_DDR2_3) {
 417                 lowest_common_cas = 3;
 418         } else if (cas_mask & SPD_CAS_LATENCY_DDR2_4) {
 419                 lowest_common_cas = 4;
 420         } else if (cas_mask & SPD_CAS_LATENCY_DDR2_5) {
 421                 lowest_common_cas = 5;
 422         }
 423         PRINTK_DEBUG("lowest common cas = %d\n", lowest_common_cas);
 424
 425         for (j = max_ram_speed; j>=0; j--) {
 426                 int freq_cas_mask = cas_mask;
 427
 428                 PRINTK_DEBUG("Probing Speed %d\n", j);
 429                 for (i=0; i<2*DIMM_SOCKETS; i++) {
 430                         int current_cas_mask;
 431
 432                         PRINTK_DEBUG("  DIMM: %d\n", i);
 433                         if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) {
 434                                 continue;
 435                         }
 436
 437                         current_cas_mask = spd_read_byte(DIMM_SPD_BASE + i, SPD_ACCEPTABLE_CAS_LATENCIES);
 438
 439                         while (current_cas_mask) {
 440                                 int highest_supported_cas = 0, current_cas = 0;
 441                                 PRINTK_DEBUG("    Current CAS mask: %04x; ", current_cas_mask);
 442                                 if (current_cas_mask & SPD_CAS_LATENCY_DDR2_5) {
 443                                         highest_supported_cas = 5;
 444                                 } else if (current_cas_mask & SPD_CAS_LATENCY_DDR2_4) {
 445                                         highest_supported_cas = 4;
 446                                 } else if (current_cas_mask & SPD_CAS_LATENCY_DDR2_3) {
 447                                         highest_supported_cas = 3;
 448                                 }
 449                                 if (current_cas_mask & SPD_CAS_LATENCY_DDR2_3) {
 450                                         current_cas = 3;
 451                                 } else if (current_cas_mask & SPD_CAS_LATENCY_DDR2_4) {
 452                                         current_cas = 4;
 453                                 } else if (current_cas_mask & SPD_CAS_LATENCY_DDR2_5) {
 454                                         current_cas = 5;
 455                                 }
 456
 457                                 idx = highest_supported_cas - current_cas;
 458                                 PRINTK_DEBUG("idx=%d, ", idx);
 459                                 PRINTK_DEBUG("tCLK=%x, ", spd_read_byte(DIMM_SPD_BASE + i, spd_lookup_table[2*idx]));
 460                                 PRINTK_DEBUG("tAC=%x", spd_read_byte(DIMM_SPD_BASE + i, spd_lookup_table[(2*idx)+1]));
 461
 462                                 if (spd_read_byte(DIMM_SPD_BASE + i, spd_lookup_table[2*idx]) <= ddr2_speeds_table[2*j] &&
 463                                                 spd_read_byte(DIMM_SPD_BASE + i, spd_lookup_table[(2*idx)+1]) <= ddr2_speeds_table[(2*j)+1]) {
 464                                         PRINTK_DEBUG(":    OK\n");
 465                                         break;
 466                                 }
 467
 468                                 PRINTK_DEBUG(":    Not fast enough!\n");
 469
 470                                 current_cas_mask &= ~(1 << (current_cas));
 471                         }
 472
 473                         freq_cas_mask &= current_cas_mask;
 474                         if (!current_cas_mask) {
 475                                 PRINTK_DEBUG("    No valid CAS for this speed on DIMM %d\n", i);
 476                                 break;
 477                         }
 478                 }
 479                 PRINTK_DEBUG("  freq_cas_mask for speed %d: %04x\n", j, freq_cas_mask);
 480                 if (freq_cas_mask) {
 481                         switch (j) {
 482                         case 0: sysinfo->memory_frequency = 400; break;
 483                         case 1: sysinfo->memory_frequency = 533; break;
 484                         case 2: sysinfo->memory_frequency = 667; break;
 485                         }
 486                         if (freq_cas_mask & SPD_CAS_LATENCY_DDR2_3) {
 487                                 sysinfo->cas = 3;
 488                         } else if (freq_cas_mask & SPD_CAS_LATENCY_DDR2_4) {
 489                                 sysinfo->cas = 4;
 490                         } else if (freq_cas_mask & SPD_CAS_LATENCY_DDR2_5) {
 491                                 sysinfo->cas = 5;
 492                         }
 493                         break;
 494                 }
 495         }
 496
 497         if (sysinfo->memory_frequency && sysinfo->cas) {
 498                 printk_debug("Memory will be driven at %dMHz with CAS=%d clocks\n",
 499                                 sysinfo->memory_frequency, sysinfo->cas);
 500         } else {
 501                 die("Could not find common memory frequency and CAS\n");
 502         }
 503 }
 504
 505 static void sdram_detect_smallest_tRAS(struct sys_info * sysinfo)
 506 {
 507         int i;
 508         int tRAS_time;
 509         int tRAS_cycles;
 510         int freq_multiplier = 0;
 511
 512         switch (sysinfo->memory_frequency) {
 513         case 400: freq_multiplier = 0x14; break; /* 5ns */
 514         case 533: freq_multiplier = 0x0f; break; /* 3.75ns */
 515         case 667: freq_multiplier = 0x0c; break; /* 3ns */
 516         }
 517
 518         tRAS_cycles = 4; /* 4 clocks minimum */
 519         tRAS_time = tRAS_cycles * freq_multiplier;
 520
 521         for (i=0; i<2*DIMM_SOCKETS; i++) {
 522                 u8 reg8;
 523
 524                 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
 525                         continue;
 526
 527                 reg8 = spd_read_byte(DIMM_SPD_BASE + i, SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY);
 528                 if (!reg8) {
 529                         die("Invalid tRAS value.\n");
 530                 }
 531
 532                 while ((tRAS_time >> 2) < reg8) {
 533                         tRAS_time += freq_multiplier;
 534                         tRAS_cycles++;
 535                 }
 536         }
 537         if(tRAS_cycles > 0x18) {
 538                 die("DDR-II Module does not support this frequency (tRAS error)\n");
 539         }
 540
 541         printk_debug("tRAS = %d cycles\n", tRAS_cycles);
 542         sysinfo->tras = tRAS_cycles;
 543 }
 544
 545 static void sdram_detect_smallest_tRP(struct sys_info * sysinfo)
 546 {
 547         int i;
 548         int tRP_time;
 549         int tRP_cycles;
 550         int freq_multiplier = 0;
 551
 552         switch (sysinfo->memory_frequency) {
 553         case 400: freq_multiplier = 0x14; break; /* 5ns */
 554         case 533: freq_multiplier = 0x0f; break; /* 3.75ns */
 555         case 667: freq_multiplier = 0x0c; break; /* 3ns */
 556         }
 557
 558         tRP_cycles = 2; /* 2 clocks minimum */
 559         tRP_time = tRP_cycles * freq_multiplier;
 560
 561         for (i=0; i<2*DIMM_SOCKETS; i++) {
 562                 u8 reg8;
 563
 564                 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
 565                         continue;
 566
 567                 reg8 = spd_read_byte(DIMM_SPD_BASE + i, SPD_MIN_ROW_PRECHARGE_TIME);
 568                 if (!reg8) {
 569                         die("Invalid tRP value.\n");
 570                 }
 571
 572                 while (tRP_time < reg8) {
 573                         tRP_time += freq_multiplier;
 574                         tRP_cycles++;
 575                 }
 576         }
 577
 578         if(tRP_cycles > 6) {
 579                 die("DDR-II Module does not support this frequency (tRP error)\n");
 580         }
 581
 582         printk_debug("tRP = %d cycles\n", tRP_cycles);
 583         sysinfo->trp = tRP_cycles;
 584 }
 585
 586 static void sdram_detect_smallest_tRCD(struct sys_info * sysinfo)
 587 {
 588         int i;
 589         int tRCD_time;
 590         int tRCD_cycles;
 591         int freq_multiplier = 0;
 592
 593         switch (sysinfo->memory_frequency) {
 594         case 400: freq_multiplier = 0x14; break; /* 5ns */
 595         case 533: freq_multiplier = 0x0f; break; /* 3.75ns */
 596         case 667: freq_multiplier = 0x0c; break; /* 3ns */
 597         }
 598
 599         tRCD_cycles = 2;
 600         tRCD_time = tRCD_cycles * freq_multiplier;
 601
 602         for (i=0; i<2*DIMM_SOCKETS; i++) {
 603                 u8 reg8;
 604
 605                 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
 606                         continue;
 607
 608                 reg8 = spd_read_byte(DIMM_SPD_BASE + i, SPD_MIN_RAS_TO_CAS_DELAY);
 609                 if (!reg8) {
 610                         die("Invalid tRCD value.\n");
 611                 }
 612
 613                 while (tRCD_time < reg8) {
 614                         tRCD_time += freq_multiplier;
 615                         tRCD_cycles++;
 616                 }
 617         }
 618         if(tRCD_cycles > 6) {
 619                 die("DDR-II Module does not support this frequency (tRCD error)\n");
 620         }
 621
 622         printk_debug("tRCD = %d cycles\n", tRCD_cycles);
 623         sysinfo->trcd = tRCD_cycles;
 624 }
 625
 626 static void sdram_detect_smallest_tWR(struct sys_info * sysinfo)
 627 {
 628         int i;
 629         int tWR_time;
 630         int tWR_cycles;
 631         int freq_multiplier = 0;
 632
 633         switch (sysinfo->memory_frequency) {
 634         case 400: freq_multiplier = 0x14; break; /* 5ns */
 635         case 533: freq_multiplier = 0x0f; break; /* 3.75ns */
 636         case 667: freq_multiplier = 0x0c; break; /* 3ns */
 637         }
 638
 639         tWR_cycles = 2; /* 2 clocks minimum */
 640         tWR_time = tWR_cycles * freq_multiplier;
 641
 642         for (i=0; i<2*DIMM_SOCKETS; i++) {
 643                 u8 reg8;
 644
 645                 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
 646                         continue;
 647
 648                 reg8 = spd_read_byte(DIMM_SPD_BASE + i, SPD_WRITE_RECOVERY_TIME);
 649                 if (!reg8) {
 650                         die("Invalid tWR value.\n");
 651                 }
 652
 653                 while (tWR_time < reg8) {
 654                         tWR_time += freq_multiplier;
 655                         tWR_cycles++;
 656                 }
 657         }
 658         if(tWR_cycles > 5) {
 659                 die("DDR-II Module does not support this frequency (tWR error)\n");
 660         }
 661
 662         printk_debug("tWR = %d cycles\n", tWR_cycles);
 663         sysinfo->twr = tWR_cycles;
 664 }
 665
 666 static void sdram_detect_smallest_tRFC(struct sys_info * sysinfo)
 667 {
 668         int i, index = 0;
 669
 670         const u8 tRFC_cycles[] = {
 671              /* 75 105 127.5 */
 672                 15, 21, 26,     /* DDR2-400 */
 673                 20, 28, 34,     /* DDR2-533 */
 674                 25, 35, 43      /* DDR2-667 */
 675         };
 676
 677         for (i=0; i<2*DIMM_SOCKETS; i++) {
 678                 u8 reg8;
 679
 680                 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
 681                         continue;
 682
 683                 reg8 = sysinfo->banksize[i*2];
 684                 switch (reg8) {
 685                 case 0x04: reg8 = 0; break;
 686                 case 0x08: reg8 = 1; break;
 687                 case 0x10: reg8 = 2; break;
 688                 case 0x20: reg8 = 3; break;
 689                 }
 690
 691                 if (sysinfo->dimm[i] == SYSINFO_DIMM_X16DS || sysinfo->dimm[i] == SYSINFO_DIMM_X16SS)
 692                         reg8++;
 693
 694                 if (reg8 > 3) {
 695                         /* Can this happen? Go back to 127.5ns just to be sure
 696                          * we don't run out of the array. This may be wrong
 697                          */
 698                         printk_debug("DIMM %d is 1Gb x16.. Please report.\n", i);
 699                         reg8 = 3;
 700                 }
 701
 702                 if (reg8 > index)
 703                         index = reg8;
 704
 705         }
 706         index--;
 707         switch (sysinfo->memory_frequency) {
 708         case 667: index += 3;
 709         case 533: index += 3;
 710         case 400: break;
 711         }
 712
 713         sysinfo->trfc = tRFC_cycles[index];
 714         printk_debug("tRFC = %d cycles\n", tRFC_cycles[index]);
 715 }
 716
 717
 718 static void sdram_detect_smallest_refresh(struct sys_info * sysinfo)
 719 {
 720         int i;
 721
 722         sysinfo->refresh = 0;
 723
 724         for (i=0; i<2*DIMM_SOCKETS; i++) {
 725                 int refresh;
 726
 727                 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
 728                         continue;
 729
 730                 refresh = spd_read_byte(DIMM_SPD_BASE + i, SPD_REFRESH) & ~(1 << 7);
 731
 732                 /* 15.6us */
 733                 if (!refresh)
 734                         continue;
 735
 736                 /* Refresh is slower than 15.6us, use 15.6us */
 737                 if (refresh > 2)
 738                         continue;
 739
 740                 if (refresh == 2) {
 741                         sysinfo->refresh = 1;
 742                         break;
 743                 }
 744
 745                 die("DDR-II module has unsupported refresh value\n");
 746         }
 747         printk_debug("Refresh: %s\n", sysinfo->refresh?"7.8us":"15.6us");
 748 }
 749
 750 static void sdram_verify_burst_length(struct sys_info * sysinfo)
 751 {
 752         int i;
 753
 754         for (i=0; i<2*DIMM_SOCKETS; i++) {
 755                 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
 756                         continue;
 757
 758                 if (!(spd_read_byte(DIMM_SPD_BASE + i, SPD_SUPPORTED_BURST_LENGTHS) & SPD_BURST_LENGTH_8))
 759                         die("Only DDR-II RAM with burst length 8 is supported by this chipset.\n");
 760         }
 761 }
 762
 763 static void sdram_program_dram_width(struct sys_info * sysinfo)
 764 {
 765         u16 c0dramw=0, c1dramw=0;
 766         int idx;
 767
 768         if (sysinfo->dual_channel)
 769                 idx = 2;
 770         else
 771                 idx = 1;
 772
 773         switch (sysinfo->dimm[0]) {
 774         case 0: c0dramw = 0x0000; break; /* x16DS */
 775         case 1: c0dramw = 0x0001; break; /* x8DS */
 776         case 2: c0dramw = 0x0000; break; /* x16SS */
 777         case 3: c0dramw = 0x0005; break; /* x8DDS */
 778         case 4: c0dramw = 0x0000; break; /* NC */
 779         }
 780
 781         switch (sysinfo->dimm[idx]) {
 782         case 0: c1dramw = 0x0000; break; /* x16DS */
 783         case 1: c1dramw = 0x0010; break; /* x8DS */
 784         case 2: c1dramw = 0x0000; break; /* x16SS */
 785         case 3: c1dramw = 0x0050; break; /* x8DDS */
 786         case 4: c1dramw = 0x0000; break; /* NC */
 787         }
 788
 789         if ( !sdram_capabilities_dual_channel() ) {
 790                 /* Single Channel */
 791                 c0dramw |= c1dramw;
 792                 c1dramw = 0;
 793         }
 794
 795         MCHBAR16(C0DRAMW) = c0dramw;
 796         MCHBAR16(C1DRAMW) = c1dramw;
 797 }
 798
 799 static void sdram_write_slew_rates(u32 offset, const u32 *slew_rate_table)
 800 {
 801         int i;
 802
 803         for (i=0; i<16; i++)
 804                 MCHBAR32(offset+(i*4)) = slew_rate_table[i];
 805 }
 806
 807 static void sdram_rcomp_buffer_strength_and_slew(struct sys_info *sysinfo)
 808 {
 809         static const u32 dq2030[] = {
 810                 0x08070706, 0x0a090908, 0x0d0c0b0a, 0x12100f0e,
 811                 0x1a181614, 0x22201e1c, 0x2a282624, 0x3934302d,
 812                 0x0a090908, 0x0c0b0b0a, 0x0e0d0d0c, 0x1211100f,
 813                 0x19171513, 0x211f1d1b, 0x2d292623, 0x3f393531
 814         };
 815
 816         static const u32 dq2330[] = {
 817                 0x08070706, 0x0a090908, 0x0d0c0b0a, 0x12100f0e,
 818                 0x1a181614, 0x22201e1c, 0x2a282624, 0x3934302d,
 819                 0x0a090908, 0x0c0b0b0a, 0x0e0d0d0c, 0x1211100f,
 820                 0x19171513, 0x211f1d1b, 0x2d292623, 0x3f393531
 821         };
 822
 823         static const u32 cmd2710[] = {
 824                 0x07060605, 0x0f0d0b09, 0x19171411, 0x1f1f1d1b,
 825                 0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f,
 826
 827                 0x1110100f, 0x0f0d0b09, 0x19171411, 0x1f1f1d1b,
 828                 0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f
 829         };
 830
 831         static const u32 cmd3210[] = {
 832                 0x0f0d0b0a, 0x17151311, 0x1f1d1b19, 0x1f1f1f1f,
 833                 0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f,
 834                 0x18171615, 0x1f1f1c1a, 0x1f1f1f1f, 0x1f1f1f1f,
 835                 0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f
 836         };
 837
 838         static const u32 clk2030[] = {
 839                 0x0e0d0d0c, 0x100f0f0e, 0x100f0e0d, 0x15131211,
 840                 0x1d1b1917, 0x2523211f, 0x2a282927, 0x32302e2c,
 841                 0x17161514, 0x1b1a1918, 0x1f1e1d1c, 0x23222120,
 842                 0x27262524, 0x2d2b2928, 0x3533312f, 0x3d3b3937
 843         };
 844
 845         static const u32 ctl3215[] = {
 846                 0x01010000, 0x03020101, 0x07060504, 0x0b0a0908,
 847                 0x100f0e0d, 0x14131211, 0x18171615, 0x1c1b1a19,
 848                 0x05040403, 0x07060605, 0x0a090807, 0x0f0d0c0b,
 849                 0x14131211, 0x18171615, 0x1c1b1a19, 0x201f1e1d
 850         };
 851
 852         static const u32 ctl3220[] = {
 853                 0x05040403, 0x07060505, 0x0e0c0a08, 0x1a171411,
 854                 0x2825221f, 0x35322f2b, 0x3e3e3b38, 0x3e3e3e3e,
 855                 0x09080807, 0x0b0a0a09, 0x0f0d0c0b, 0x1b171311,
 856                 0x2825221f, 0x35322f2b, 0x3e3e3b38, 0x3e3e3e3e
 857         };
 858
 859         static const u32 nc[] = {
 860                 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 861                 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 862                 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 863                 0x00000000, 0x00000000, 0x00000000, 0x00000000
 864         };
 865
 866         static const u32 const * const dual_channel_slew_group_lookup[] = {
 867                 dq2030, cmd3210, ctl3215, ctl3215, clk2030, clk2030, dq2030, cmd3210,
 868                 dq2030, cmd3210, ctl3215, ctl3215, clk2030, clk2030, dq2030, cmd3210,
 869                 dq2030, cmd3210, nc,      ctl3215, nc,      clk2030, dq2030, cmd3210,
 870                 dq2030, cmd3210, ctl3215, ctl3215, clk2030, clk2030, dq2030, cmd2710,
 871                 dq2030, cmd3210, nc,      ctl3215, nc,      clk2030, nc,     nc,
 872
 873                 dq2030, cmd3210, ctl3215, ctl3215, clk2030, clk2030, dq2030, cmd3210,
 874                 dq2030, cmd3210, ctl3215, nc,      clk2030, nc,      dq2030, cmd3210,
 875                 dq2030, cmd3210, ctl3215, ctl3215, clk2030, clk2030, dq2030, cmd3210,
 876                 dq2030, cmd3210, ctl3215, nc,      clk2030, nc,      dq2030, cmd2710,
 877                 dq2030, cmd3210, ctl3215, nc,      clk2030, nc,      nc,     nc,
 878
 879                 dq2030, cmd3210, nc,      ctl3215, nc,      clk2030, dq2030, cmd3210,
 880                 dq2030, cmd3210, ctl3215, ctl3215, clk2030, clk2030, dq2030, cmd3210,
 881                 dq2030, cmd3210, nc,      ctl3215, nc,      clk2030, dq2030, cmd3210,
 882                 dq2030, cmd3210, ctl3215, ctl3215, clk2030, clk2030, dq2030, cmd2710,
 883                 dq2030, cmd3210, nc,      ctl3215, nc,      clk2030, nc,     nc,
 884
 885                 dq2030, cmd2710, ctl3215, ctl3215, clk2030, clk2030, dq2030, cmd3210,
 886                 dq2030, cmd2710, ctl3215, nc,      clk2030, nc,      dq2030, cmd3210,
 887                 dq2030, cmd2710, ctl3215, ctl3215, clk2030, clk2030, dq2030, cmd3210,
 888                 dq2030, cmd2710, ctl3215, nc,      clk2030, nc,      dq2030, cmd2710,
 889                 dq2030, cmd2710, ctl3215, nc,      clk2030, nc,      nc,     nc,
 890
 891                 nc,     nc,      nc,      ctl3215, nc,      clk2030, dq2030, cmd3210,
 892                 nc,     nc,      ctl3215, nc,      clk2030, nc,      dq2030, cmd3210,
 893                 nc,     nc,      nc,      ctl3215, nc,      clk2030, dq2030, cmd3210,
 894                 nc,     nc,      ctl3215, nc,      clk2030, clk2030, dq2030, cmd2710
 895         };
 896
 897         static const u32 const * const single_channel_slew_group_lookup[] = {
 898                 dq2330, cmd3210, ctl3215, ctl3215, clk2030, clk2030, dq2330, cmd3210,
 899                 dq2330, cmd3210, ctl3215, ctl3215, clk2030, clk2030, dq2330, cmd3210,
 900                 dq2330, cmd3210, nc,      ctl3215, nc,      clk2030, dq2330, cmd3210,
 901                 dq2330, cmd3210, ctl3215, ctl3215, clk2030, clk2030, dq2330, cmd3210,
 902                 dq2330, cmd3210, nc,      ctl3215, nc,      clk2030, nc,     nc,
 903
 904                 dq2330, cmd3210, ctl3215, ctl3215, clk2030, clk2030, dq2330, cmd3210,
 905                 dq2330, cmd3210, ctl3215, nc,      clk2030, nc,      dq2330, cmd3210,
 906                 dq2330, cmd3210, ctl3215, ctl3215, clk2030, clk2030, dq2330, cmd3210,
 907                 dq2330, cmd3210, ctl3215, nc,      clk2030, nc,      dq2330, cmd3210,
 908                 dq2330, cmd3210, ctl3215, nc,      clk2030, nc,      nc,     nc,
 909
 910                 dq2330, cmd3210, nc,      ctl3215, nc,      clk2030, dq2330, cmd3210,
 911                 dq2330, cmd3210, ctl3215, ctl3215, clk2030, clk2030, dq2330, cmd3210,
 912                 dq2330, cmd3210, nc,      ctl3215, nc,      clk2030, dq2330, cmd3210,
 913                 dq2330, cmd3210, ctl3215, ctl3215, clk2030, clk2030, dq2330, cmd3210,
 914                 dq2330, cmd3210, nc,      ctl3215, nc,      clk2030, nc,     nc,
 915
 916                 dq2330, cmd3210, ctl3215, ctl3215, clk2030, clk2030, dq2330, cmd3210,
 917                 dq2330, cmd3210, ctl3215, nc,      clk2030, nc,      dq2330, cmd3210,
 918                 dq2330, cmd3210, ctl3215, ctl3215, clk2030, clk2030, dq2330, cmd3210,
 919                 dq2330, cmd3210, ctl3215, nc,      clk2030, nc,      dq2330, cmd3210,
 920                 dq2330, cmd3210, ctl3215, nc,      clk2030, nc,      nc,     nc,
 921
 922                 dq2330, nc,      nc,      ctl3215, nc,      clk2030, dq2030, cmd3210,
 923                 dq2330, nc,      ctl3215, nc,      clk2030, nc,      dq2030, cmd3210,
 924                 dq2330, nc,      nc,      ctl3215, nc,      clk2030, dq2030, cmd3210,
 925                 dq2330, nc,      ctl3215, nc,      clk2030, clk2030, dq2030, cmd3210
 926         };
 927
 928
 929         /* Strength multiplier tables */
 930         static const u8 dual_channel_strength_multiplier[] = {
 931                 0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11,
 932                 0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11,
 933                 0x44, 0x11, 0x00, 0x11, 0x00, 0x44, 0x44, 0x11,
 934                 0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x22,
 935                 0x44, 0x11, 0x00, 0x11, 0x00, 0x44, 0x00, 0x00,
 936                 0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11,
 937                 0x44, 0x11, 0x11, 0x00, 0x44, 0x00, 0x44, 0x11,
 938                 0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11,
 939                 0x44, 0x11, 0x11, 0x00, 0x44, 0x00, 0x44, 0x22,
 940                 0x44, 0x11, 0x11, 0x00, 0x44, 0x00, 0x00, 0x00,
 941                 0x44, 0x11, 0x00, 0x11, 0x00, 0x44, 0x44, 0x11,
 942                 0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11,
 943                 0x44, 0x11, 0x00, 0x11, 0x00, 0x44, 0x44, 0x11,
 944                 0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x22,
 945                 0x44, 0x11, 0x00, 0x11, 0x00, 0x44, 0x00, 0x00,
 946                 0x44, 0x22, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11,
 947                 0x44, 0x22, 0x11, 0x00, 0x44, 0x00, 0x44, 0x11,
 948                 0x44, 0x22, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11,
 949                 0x44, 0x22, 0x11, 0x00, 0x44, 0x00, 0x44, 0x22,
 950                 0x44, 0x22, 0x11, 0x00, 0x44, 0x00, 0x00, 0x00,
 951                 0x00, 0x00, 0x00, 0x11, 0x00, 0x44, 0x44, 0x11,
 952                 0x00, 0x00, 0x11, 0x00, 0x44, 0x00, 0x44, 0x11,
 953                 0x00, 0x00, 0x00, 0x11, 0x00, 0x44, 0x44, 0x11,
 954                 0x00, 0x00, 0x11, 0x00, 0x44, 0x44, 0x44, 0x22
 955         };
 956
 957         static const u8 single_channel_strength_multiplier[] = {
 958                 0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11,
 959                 0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11,
 960                 0x33, 0x11, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11,
 961                 0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11,
 962                 0x33, 0x11, 0x00, 0x11, 0x00, 0x44, 0x00, 0x00,
 963                 0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11,
 964                 0x33, 0x11, 0x11, 0x00, 0x44, 0x00, 0x33, 0x11,
 965                 0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11,
 966                 0x33, 0x11, 0x11, 0x00, 0x44, 0x00, 0x33, 0x11,
 967                 0x33, 0x11, 0x11, 0x00, 0x44, 0x00, 0x00, 0x00,
 968                 0x33, 0x11, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11,
 969                 0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11,
 970                 0x33, 0x11, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11,
 971                 0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11,
 972                 0x33, 0x11, 0x00, 0x11, 0x00, 0x44, 0x00, 0x00,
 973                 0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11,
 974                 0x33, 0x11, 0x11, 0x00, 0x44, 0x00, 0x33, 0x11,
 975                 0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11,
 976                 0x33, 0x11, 0x11, 0x00, 0x44, 0x00, 0x33, 0x11,
 977                 0x33, 0x11, 0x11, 0x00, 0x44, 0x00, 0x00, 0x00,
 978                 0x33, 0x00, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11,
 979                 0x33, 0x00, 0x11, 0x00, 0x44, 0x00, 0x33, 0x11,
 980                 0x33, 0x00, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11,
 981                 0x33, 0x00, 0x11, 0x00, 0x44, 0x44, 0x33, 0x11
 982         };
 983
 984         const u8 * strength_multiplier;
 985         const u32* const * slew_group_lookup;
 986         int idx;
 987
 988         /* Set Strength Multipliers */
 989
 990         /* Dual Channel needs different tables. */
 991         if (sdram_capabilities_dual_channel()) {
 992                 printk_debug("Programming Dual Channel RCOMP\n");
 993                 strength_multiplier = dual_channel_strength_multiplier;
 994                 slew_group_lookup   = dual_channel_slew_group_lookup;
 995                 idx = 5 * sysinfo->dimm[0] +  sysinfo->dimm[2];
 996         } else {
 997                 printk_debug("Programming Single Channel RCOMP\n");
 998                 strength_multiplier = single_channel_strength_multiplier;
 999                 slew_group_lookup   = single_channel_slew_group_lookup;
1000                 idx = 5 * sysinfo->dimm[0] + sysinfo->dimm[1];
1001         }
1002
1003         printk_debug("Table Index: %d\n", idx);
1004
1005         MCHBAR8(G1SC) = strength_multiplier[idx * 8 + 0];
1006         MCHBAR8(G2SC) = strength_multiplier[idx * 8 + 1];
1007         MCHBAR8(G3SC) = strength_multiplier[idx * 8 + 2];
1008         MCHBAR8(G4SC) = strength_multiplier[idx * 8 + 3];
1009         MCHBAR8(G5SC) = strength_multiplier[idx * 8 + 4];
1010         MCHBAR8(G6SC) = strength_multiplier[idx * 8 + 5];
1011         MCHBAR8(G7SC) = strength_multiplier[idx * 8 + 6];
1012         MCHBAR8(G8SC) = strength_multiplier[idx * 8 + 7];
1013
1014         /* Channel 0 */
1015         sdram_write_slew_rates(G1SRPUT, slew_group_lookup[idx * 8 + 0]);
1016         sdram_write_slew_rates(G2SRPUT, slew_group_lookup[idx * 8 + 1]);
1017         if ((slew_group_lookup[idx * 8 + 2] != nc) && (sysinfo->package == SYSINFO_PACKAGE_STACKED)) {
1018
1019
1020                 sdram_write_slew_rates(G3SRPUT, ctl3220);
1021         } else {
1022                 sdram_write_slew_rates(G3SRPUT, slew_group_lookup[idx * 8 + 2]);
1023         }
1024         sdram_write_slew_rates(G4SRPUT, slew_group_lookup[idx * 8 + 3]);
1025         sdram_write_slew_rates(G5SRPUT, slew_group_lookup[idx * 8 + 4]);
1026         sdram_write_slew_rates(G6SRPUT, slew_group_lookup[idx * 8 + 5]);
1027
1028         /* Channel 1 */
1029         if (sysinfo->dual_channel) {
1030                 sdram_write_slew_rates(G7SRPUT, slew_group_lookup[idx * 8 + 6]);
1031                 sdram_write_slew_rates(G8SRPUT, slew_group_lookup[idx * 8 + 7]);
1032         } else {
1033                 sdram_write_slew_rates(G7SRPUT, nc);
1034                 sdram_write_slew_rates(G8SRPUT, nc);
1035         }
1036 }
1037
1038 static void sdram_enable_rcomp(void)
1039 {
1040         u32 reg32;
1041
1042         udelay(300);
1043         reg32 = MCHBAR32(GBRCOMPCTL);
1044         reg32 &= ~(1 << 23);
1045         MCHBAR32(GBRCOMPCTL) = reg32;
1046 }
1047
1048 static void sdram_program_dll_timings(struct sys_info *sysinfo)
1049 {
1050         u32 chan0dll = 0, chan1dll = 0;
1051         int i;
1052
1053         printk_debug ("Programming DLL Timings... \n");
1054
1055         MCHBAR16(DQSMT) &= ~( (3 << 12) | (1 << 10) | ( 0xf << 0) );
1056         MCHBAR16(DQSMT) |= (1 << 13) | (0xc << 0);
1057
1058         /* We drive both channels with the same speed */
1059         switch (sysinfo->memory_frequency) {
1060         case 400: chan0dll = 0x26262626; chan1dll=0x26262626; break; /* 400MHz */
1061         case 533: chan0dll = 0x22222222; chan1dll=0x22222222; break; /* 533MHz */
1062         case 667: chan0dll = 0x11111111; chan1dll=0x11111111; break; /* 667MHz */
1063         }
1064
1065         for (i=0; i < 4; i++) {
1066                 MCHBAR32(C0R0B00DQST + (i * 0x10) + 0) = chan0dll;
1067                 MCHBAR32(C0R0B00DQST + (i * 0x10) + 4) = chan0dll;
1068                 MCHBAR32(C1R0B00DQST + (i * 0x10) + 0) = chan1dll;
1069                 MCHBAR32(C1R0B00DQST + (i * 0x10) + 4) = chan1dll;
1070         }
1071 }
1072
1073 static void sdram_force_rcomp(void)
1074 {
1075         u32 reg32;
1076         u8 reg8;
1077
1078         reg32 = MCHBAR32(ODTC);
1079         reg32 |= (1 << 28);
1080         MCHBAR32(ODTC) = reg32;
1081
1082         reg32 = MCHBAR32(SMSRCTL);
1083         reg32 |= (1 << 0);
1084         MCHBAR32(SMSRCTL) = reg32;
1085
1086         reg32 = MCHBAR32(GBRCOMPCTL);
1087         reg32 |= (1 << 8);
1088         MCHBAR32(GBRCOMPCTL) = reg32;
1089
1090         reg8 = i945_silicon_revision();
1091         if ((reg8 == 0 && (MCHBAR32(DCC) & (3 << 0)) == 0) || (reg8 == 1)) {
1092                 reg32 = MCHBAR32(GBRCOMPCTL);
1093                 reg32 |= (3 << 5);
1094                 MCHBAR32(GBRCOMPCTL) = reg32;
1095         }
1096 }
1097
1098 static void sdram_initialize_system_memory_io(struct sys_info *sysinfo)
1099 {
1100         u8 reg8;
1101         u32 reg32;
1102
1103         printk_debug ("Initializing System Memory IO... \n");
1104
1105         reg8 = MCHBAR8(C0HCTC);
1106         reg8 &= ~0x1f;
1107         reg8 |= ( 1 << 0);
1108         MCHBAR8(C0HCTC) = reg8;
1109
1110         reg8 = MCHBAR8(C1HCTC);
1111         reg8 &= ~0x1f;
1112         reg8 |= ( 1 << 0);
1113         MCHBAR8(C1HCTC) = reg8;
1114
1115
1116         MCHBAR16(WDLLBYPMODE) &= ~( (1 << 9) | (1 << 6) | (1 << 4) | (1 << 3) | (1 << 1) );
1117         MCHBAR16(WDLLBYPMODE) |= (1 << 8) | (1 << 7) | (1 << 5) | (1 << 2) | (1 << 0);
1118
1119         MCHBAR8(C0WDLLCMC) = 0;
1120         MCHBAR8(C1WDLLCMC) = 0;
1121
1122         sdram_program_dram_width(sysinfo);
1123
1124         sdram_rcomp_buffer_strength_and_slew(sysinfo);
1125
1126         reg32 = MCHBAR32(GBRCOMPCTL);
1127         reg32 &= ~( (1 << 29) | (1 << 26) | (3 << 21) | (3 << 2) );
1128         reg32 |= (3 << 27) | (3 << 0);
1129         MCHBAR32(GBRCOMPCTL) = reg32;
1130
1131         MCHBAR32(GBRCOMPCTL) |= (1 << 10);
1132
1133         sdram_program_dll_timings(sysinfo);
1134
1135         sdram_force_rcomp();
1136 }
1137
1138 static void sdram_enable_system_memory_io(struct sys_info *sysinfo)
1139 {
1140         u32 reg32;
1141
1142         printk_debug ("Enabling System Memory IO... \n");
1143
1144         reg32 = MCHBAR32(RCVENMT);
1145         reg32 &= ~(0x3f << 6);
1146         MCHBAR32(RCVENMT) = reg32;
1147
1148         reg32 |= (1 << 11) | (1 << 9);
1149         MCHBAR32(RCVENMT) = reg32;
1150
1151         reg32 = MCHBAR32(DRTST);
1152         reg32 |= (1 << 3) | (1 << 2);
1153         MCHBAR32(DRTST) = reg32;
1154
1155         reg32 = MCHBAR32(DRTST);
1156         reg32 |= (1 << 6) | (1 << 4);
1157         MCHBAR32(DRTST) = reg32;
1158
1159         asm volatile ("nop; nop;");
1160
1161         reg32 = MCHBAR32(DRTST);
1162
1163         /* Is channel 0 populated? */
1164         if (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED ||
1165                         sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED)
1166                 reg32 |= (1 << 7) | (1 << 5);
1167         else
1168                 reg32 |= (1 << 31);
1169
1170         /* Is channel 1 populated? */
1171         if (sysinfo->dimm[2] != SYSINFO_DIMM_NOT_POPULATED ||
1172                         sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED)
1173                 reg32 |= (1 << 9) | (1 << 8);
1174         else
1175                 reg32 |= (1 << 30);
1176
1177         MCHBAR32(DRTST) = reg32;
1178
1179         if (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED ||
1180                         sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED) {
1181                 reg32 = MCHBAR32(C0DRC1);
1182                 reg32 |= (1 << 8);
1183                 MCHBAR32(C0DRC1) = reg32;
1184         }
1185         if (sysinfo->dimm[2] != SYSINFO_DIMM_NOT_POPULATED ||
1186                         sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED) {
1187                 reg32 = MCHBAR32(C1DRC1);
1188                 reg32 |= (1 << 8);
1189                 MCHBAR32(C1DRC1) = reg32;
1190         }
1191 }
1192
1193 struct dimm_size {
1194         unsigned long side1;
1195         unsigned long side2;
1196 };
1197
1198 static struct dimm_size sdram_get_dimm_size(u16 device)
1199 {
1200         /* Calculate the log base 2 size of a DIMM in bits */
1201         struct dimm_size sz;
1202         int value, low, rows, columns;
1203
1204         sz.side1 = 0;
1205         sz.side2 = 0;
1206
1207         rows = spd_read_byte(device, SPD_NUM_ROWS);     /* rows */
1208         if (rows < 0) goto hw_err;
1209         if ((rows & 0xf) == 0) goto val_err;
1210         sz.side1 += rows & 0xf;
1211
1212         columns = spd_read_byte(device, SPD_NUM_COLUMNS);       /* columns */
1213         if (columns < 0) goto hw_err;
1214         if ((columns & 0xf) == 0) goto val_err;
1215         sz.side1 += columns & 0xf;
1216
1217         value = spd_read_byte(device, SPD_NUM_BANKS_PER_SDRAM); /* banks */
1218         if (value < 0) goto hw_err;
1219         if ((value & 0xff) == 0) goto val_err;
1220         sz.side1 += log2(value & 0xff);
1221
1222         /* Get the module data width and convert it to a power of two */
1223         value = spd_read_byte(device, SPD_MODULE_DATA_WIDTH_MSB);       /* (high byte) */
1224         if (value < 0) goto hw_err;
1225         value &= 0xff;
1226         value <<= 8;
1227
1228         low = spd_read_byte(device, SPD_MODULE_DATA_WIDTH_LSB); /* (low byte) */
1229         if (low < 0) goto hw_err;
1230         value = value | (low & 0xff);
1231         if ((value != 72) && (value != 64)) goto val_err;
1232         sz.side1 += log2(value);
1233
1234         /* side 2 */
1235         value = spd_read_byte(device, SPD_NUM_DIMM_BANKS);      /* number of physical banks */
1236
1237         if (value < 0) goto hw_err;
1238         value &= 7;
1239         value++;
1240         if (value == 1) goto out;
1241         if (value != 2) goto val_err;
1242
1243         /* Start with the symmetrical case */
1244         sz.side2 = sz.side1;
1245
1246         if ((rows & 0xf0) == 0) goto out;       /* If symmetrical we are done */
1247
1248         /* Don't die here, I have not come across any of these to test what
1249          * actually happens.
1250          */
1251         printk_err("Assymetric DIMMs are not supported by this chipset\n");
1252
1253         sz.side2 -= (rows & 0x0f);              /* Subtract out rows on side 1 */
1254         sz.side2 += ((rows >> 4) & 0x0f);       /* Add in rows on side 2 */
1255
1256         sz.side2 -= (columns & 0x0f);           /* Subtract out columns on side 1 */
1257         sz.side2 += ((columns >> 4) & 0x0f);    /* Add in columns on side 2 */
1258
1259         goto out;
1260
1261  val_err:
1262         die("Bad SPD value\n");
1263  hw_err:
1264         /* If a hardware error occurs the spd rom probably does not exist.
1265          * In this case report that there is no memory
1266          */
1267         sz.side1 = 0;
1268         sz.side2 = 0;
1269  out:
1270         return sz;
1271 }
1272
1273 static void sdram_detect_dimm_size(struct sys_info * sysinfo)
1274 {
1275         int i;
1276
1277         for(i = 0; i < 2 * DIMM_SOCKETS; i++) {
1278                 struct dimm_size sz;
1279
1280                 sysinfo->banksize[i * 2] = 0;
1281                 sysinfo->banksize[(i * 2) + 1] = 0;
1282
1283                 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
1284                         continue;
1285
1286                 sz = sdram_get_dimm_size(DIMM_SPD_BASE + i);
1287
1288                 sysinfo->banks[i] = spd_read_byte(DIMM_SPD_BASE + i, SPD_NUM_BANKS_PER_SDRAM);  /* banks */
1289
1290                 if (sz.side1 < 30)
1291                         die("DDR-II rank size smaller than 128MB is not supported.\n");
1292
1293                 sysinfo->banksize[i * 2] = sz.side1 - 30;
1294
1295                 printk_debug("DIMM %d side 0 = %d MB\n", i, (1 << sysinfo->banksize[i * 2]) * 128 );
1296
1297                 if (!sz.side2)
1298                         continue;
1299
1300                 /* If there is a second side, it has to have at least 128M, too */
1301                 if (sz.side2 < 30)
1302                         die("DDR-II rank size smaller than 128MB is not supported.\n");
1303
1304                 sysinfo->banksize[(i * 2) + 1] = sz.side2 - 30;
1305
1306                 printk_debug("DIMM %d side 1 = %d MB\n", i, (1 << sysinfo->banksize[(i * 2) + 1]) * 128);
1307         }
1308 }
1309
1310 static int sdram_program_row_boundaries(struct sys_info *sysinfo)
1311 {
1312         int i;
1313         int cum0, cum1, tolud;
1314
1315         printk_debug ("Setting RAM size... \n");
1316
1317         cum0 = 0;
1318         for(i = 0; i < 2 * DIMM_SOCKETS; i++) {
1319                 cum0 += (sysinfo->banksize[i] << 3);
1320                 MCHBAR8(C0DRB0+i) = cum0;
1321         }
1322
1323         /* Assume we continue in Channel 1 where we stopped in Channel 0 */
1324         cum1 = cum0;
1325
1326         /* Exception: Interleaved starts from the beginning */
1327         if (sysinfo->interleaved)
1328                 cum1 = 0;
1329
1330         /* Exception: Channel 1 is not populated. C1DRB stays zero */
1331         if (sysinfo->dimm[2] == SYSINFO_DIMM_NOT_POPULATED &&
1332                         sysinfo->dimm[3] == SYSINFO_DIMM_NOT_POPULATED)
1333                 cum1 = 0;
1334
1335         for(i = 0; i < 2 * DIMM_SOCKETS; i++) {
1336                 cum1 += (sysinfo->banksize[i + 4] << 3);
1337                 MCHBAR8(C1DRB0+i) = cum1;
1338         }
1339
1340         /* Set TOLUD Top Of Low Usable DRAM */
1341         if (sysinfo->interleaved)
1342                 tolud = (cum0 + cum1) << 1;
1343         else
1344                 tolud = (cum1 ? cum1 : cum0)  << 1;
1345
1346         /* Some extra checks needed. See 4.1.26 in the
1347          * 82945G MCH datasheet (30750203)
1348          */
1349         pci_write_config16(PCI_DEV(0,0,0), TOLUD, tolud);
1350
1351         printk_debug("C0DRB = 0x%08x\n", MCHBAR32(C0DRB0));
1352         printk_debug("C1DRB = 0x%08x\n", MCHBAR32(C1DRB0));
1353         printk_debug("TOLUD = 0x%04x\n", tolud);
1354
1355         pci_write_config16(PCI_DEV(0,0,0), TOM, tolud>>3);
1356
1357         return 0;
1358 }
1359
1360
1361 static int sdram_set_row_attributes(struct sys_info *sysinfo)
1362 {
1363         int i, value;
1364         u16 dra0=0, dra1=0, dra = 0;
1365
1366         printk_debug ("Setting row attributes... \n");
1367         for(i=0; i < 2 * DIMM_SOCKETS; i++) {
1368                 u16 device;
1369                 u8 columnsrows;
1370
1371                 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) {
1372                         continue;
1373                 }
1374
1375                 device = DIMM_SPD_BASE + i;
1376                 columnsrows = 0;
1377
1378                 value = spd_read_byte(device, SPD_NUM_ROWS);    /* rows */
1379                 columnsrows = (value & 0x0f);
1380
1381                 value = spd_read_byte(device, SPD_NUM_COLUMNS); /* columns */
1382                 columnsrows |= (value & 0xf) << 4;
1383
1384                 switch (columnsrows) {
1385                 case 0x9d: dra = 2; break;
1386                 case 0xad: dra = 3; break;
1387                 case 0xbd: dra = 4; break;
1388                 case 0xae: dra = 3; break;
1389                 case 0xbe: dra = 4; break;
1390                 default: die("Unsupported Rows/Columns. (DRA)");
1391                 }
1392
1393                 /* Double Sided DIMMs? */
1394                 if (sysinfo->banksize[(2 * i) + 1] != 0) {
1395                         dra = (dra << 4) | dra;
1396                 }
1397
1398                 if (i < DIMM_SOCKETS)
1399                         dra0 |= (dra << (i*8));
1400                 else
1401                         dra1 |= (dra << ((i - DIMM_SOCKETS)*8));
1402         }
1403
1404         MCHBAR16(C0DRA0) = dra0;
1405         MCHBAR16(C1DRA0) = dra1;
1406
1407         printk_debug("C0DRA = 0x%04x\n", dra0);
1408         printk_debug("C1DRA = 0x%04x\n", dra1);
1409
1410         return 0;
1411 }
1412
1413 static void sdram_set_bank_architecture(struct sys_info *sysinfo)
1414 {
1415         u32 off32;
1416         int i;
1417
1418         MCHBAR16(C1BNKARC) &= 0xff00;
1419         MCHBAR16(C0BNKARC) &= 0xff00;
1420
1421         off32 = C0BNKARC;
1422         for (i=0; i < 2 * DIMM_SOCKETS; i++) {
1423                 /* Switch to second channel */
1424                 if (i == DIMM_SOCKETS)
1425                         off32 = C1BNKARC;
1426
1427                 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
1428                         continue;
1429
1430                 if (sysinfo->banks[i] != 8)
1431                         continue;
1432
1433                 printk_spew("DIMM%d has 8 banks.\n");
1434
1435                 if (i & 1)
1436                         MCHBAR16(off32) |= 0x50;
1437                 else
1438                         MCHBAR16(off32) |= 0x05;
1439         }
1440 }
1441
1442 #define REFRESH_7_8US   1
1443 #define REFRESH_15_6US  0
1444 static void sdram_program_refresh_rate(struct sys_info *sysinfo)
1445 {
1446         u32 reg32;
1447
1448         if (sysinfo->refresh == REFRESH_7_8US) {
1449                 reg32 = (2 << 8); /* Refresh enabled at 7.8us */
1450         } else {
1451                 reg32 = (1 << 8); /* Refresh enabled at 15.6us */
1452         }
1453
1454         MCHBAR32(C0DRC0) &= ~(7 << 8);
1455         MCHBAR32(C0DRC0) |= reg32;
1456
1457         MCHBAR32(C1DRC0) &= ~(7 << 8);
1458         MCHBAR32(C1DRC0) |= reg32;
1459 }
1460
1461 static void sdram_program_cke_tristate(struct sys_info *sysinfo)
1462 {
1463         u32 reg32;
1464         int i;
1465
1466         reg32 = MCHBAR32(C0DRC1);
1467
1468         for (i=0; i < 4; i++) {
1469                 if (sysinfo->banksize[i] == 0) {
1470                         reg32 |= (1 << (16 + i));
1471                 }
1472         }
1473
1474         reg32 |= (1 << 12);
1475
1476         reg32 |= (1 << 11);
1477         MCHBAR32(C0DRC1) = reg32;
1478
1479         /* Do we have to do this if we're in Single Channel Mode?  */
1480         reg32 = MCHBAR32(C1DRC1);
1481
1482         for (i=4; i < 8; i++) {
1483                 if (sysinfo->banksize[i] == 0) {
1484                         reg32 |= (1 << (12 + i));
1485                 }
1486         }
1487
1488         reg32 |= (1 << 12);
1489
1490         reg32 |= (1 << 11);
1491         MCHBAR32(C1DRC1) = reg32;
1492 }
1493
1494 static void sdram_program_odt_tristate(struct sys_info *sysinfo)
1495 {
1496         u32 reg32;
1497         int i;
1498
1499         reg32 = MCHBAR32(C0DRC2);
1500
1501         for (i=0; i < 4; i++) {
1502                 if (sysinfo->banksize[i] == 0) {
1503                         reg32 |= (1 << (24 + i));
1504                 }
1505         }
1506         MCHBAR32(C0DRC2) = reg32;
1507
1508         reg32 = MCHBAR32(C1DRC2);
1509
1510         for (i=4; i < 8; i++) {
1511                 if (sysinfo->banksize[i] == 0) {
1512                         reg32 |= (1 << (20 + i));
1513                 }
1514         }
1515         MCHBAR32(C1DRC2) = reg32;
1516 }
1517
1518 static void sdram_set_timing_and_control(struct sys_info *sysinfo)
1519 {
1520         u32 reg32, off32;
1521         u32 tWTR;
1522         u32 temp_drt;
1523         int i, page_size;
1524
1525         static const u8 const drt0_table[] = {
1526           /* CL 3, 4, 5 */
1527                 3, 4, 5,        /* FSB533/400, DDR533/400 */
1528                 4, 5, 6,        /* FSB667, DDR533/400 */
1529                 4, 5, 6,        /* FSB667, DDR667 */
1530         };
1531
1532         static const u8 const cas_table[] = {
1533                 2, 1, 0, 3
1534         };
1535
1536         reg32 = MCHBAR32(C0DRC0);
1537         reg32 |= (1 << 2);      /* Burst Length 8 */
1538         reg32 &= ~( (1 << 13) | (1 << 12) );
1539         MCHBAR32(C0DRC0) = reg32;
1540
1541         reg32 = MCHBAR32(C1DRC0);
1542         reg32 |= (1 << 2);      /* Burst Length 8 */
1543         reg32 &= ~( (1 << 13) | (1 << 12) );
1544         MCHBAR32(C1DRC0) = reg32;
1545
1546         if (!sysinfo->dual_channel && sysinfo->dimm[1] !=
1547                         SYSINFO_DIMM_NOT_POPULATED) {
1548                 reg32 = MCHBAR32(C0DRC0);
1549                 reg32 |= (1 << 15);
1550                 MCHBAR32(C0DRC0) = reg32;
1551         }
1552
1553         sdram_program_refresh_rate(sysinfo);
1554
1555         sdram_program_cke_tristate(sysinfo);
1556
1557         sdram_program_odt_tristate(sysinfo);
1558
1559         /* Calculate DRT0 */
1560
1561         temp_drt = 0;
1562
1563         /* B2B Write Precharge (same bank) = CL-1 + BL/2 + tWR */
1564         reg32 = (sysinfo->cas - 1) + (BURSTLENGTH / 2) + sysinfo->twr;
1565         temp_drt |= (reg32 << 28);
1566
1567         /* Write Auto Precharge (same bank) = CL-1 + BL/2 + tWR + tRP */
1568         reg32 += sysinfo->trp;
1569         temp_drt |= (reg32 << 4);
1570
1571         if (sysinfo->memory_frequency == 667) {
1572                 tWTR = 3; /* 667MHz */
1573         } else {
1574                 tWTR = 2; /* 400 and 533 */
1575         }
1576
1577         /* B2B Write to Read Command Spacing */
1578         reg32 = (sysinfo->cas - 1) + (BURSTLENGTH / 2) + tWTR;
1579         temp_drt |= (reg32 << 24);
1580
1581
1582         temp_drt |= ( (1 << 22) | (3 << 20) | (1 << 18) | (0 << 16) );
1583
1584         /* Program Write Auto Precharge to Activate */
1585         off32 = 0;
1586         if (sysinfo->fsb_frequency == 667) { /* 667MHz FSB */
1587                 off32 += 3;
1588         }
1589         if (sysinfo->memory_frequency == 667) {
1590                 off32 += 3;
1591         }
1592         off32 += sysinfo->cas - 3;
1593         reg32 = drt0_table[off32];
1594         temp_drt |= (reg32 << 11);
1595
1596         /* Read Auto Precharge to Activate */
1597
1598         temp_drt |= (8 << 0);
1599
1600         MCHBAR32(C0DRT0) = temp_drt;
1601         MCHBAR32(C1DRT0) = temp_drt;
1602
1603         /* Calculate DRT1 */
1604
1605         temp_drt = MCHBAR32(C0DRT1) & 0x00020088;
1606
1607         /* DRAM RASB Precharge */
1608         temp_drt |= (sysinfo->trp - 2) << 0;
1609
1610         /* DRAM RASB to CASB Delay */
1611         temp_drt |= (sysinfo->trcd - 2) << 4;
1612
1613         /* CASB Latency */
1614         temp_drt |= (cas_table[sysinfo->cas - 3]) << 8;
1615
1616         /* Refresh Cycle Time */
1617         temp_drt |= (sysinfo->trfc) << 10;
1618
1619         /* Pre-All to Activate Delay */
1620         temp_drt |= (0 << 16);
1621
1622         /* Precharge to Precharge Delay stays at 1 clock */
1623         temp_drt |= (0 << 18);
1624
1625         /* Activate to Precharge Delay */
1626         temp_drt |= (sysinfo->tras << 19);
1627
1628         /* Read to Precharge (tRTP) */
1629         if (sysinfo->memory_frequency == 667) {
1630                 temp_drt |= (1 << 28);
1631         } else {
1632                 temp_drt |= (0 << 28);
1633         }
1634
1635         /* Determine page size */
1636         reg32 = 0;
1637         page_size = 1; /* Default: 1k pagesize */
1638         for (i=0; i< 2*DIMM_SOCKETS; i++) {
1639                 if (sysinfo->dimm[i] == SYSINFO_DIMM_X16DS ||
1640                                 sysinfo->dimm[i] == SYSINFO_DIMM_X16SS)
1641                         page_size = 2; /* 2k pagesize */
1642         }
1643
1644         if (sysinfo->memory_frequency == 533 && page_size == 2) {
1645                 reg32 = 1;
1646         }
1647         if (sysinfo->memory_frequency == 667) {
1648                 reg32 = page_size;
1649         }
1650
1651         temp_drt |= (reg32 << 30);
1652
1653         MCHBAR32(C0DRT1) = temp_drt;
1654         MCHBAR32(C1DRT1) = temp_drt;
1655
1656         /* Program DRT2 */
1657         reg32 = MCHBAR32(C0DRT2);
1658         reg32 &= ~(1 << 8);
1659         MCHBAR32(C0DRT2) = reg32;
1660
1661         reg32 = MCHBAR32(C1DRT2);
1662         reg32 &= ~(1 << 8);
1663         MCHBAR32(C1DRT2) = reg32;
1664
1665         /* Calculate DRT3 */
1666         temp_drt = MCHBAR32(C0DRT3) & ~0x07ffffff;
1667
1668         /* Get old tRFC value */
1669         reg32 = MCHBAR32(C0DRT1) >> 10;
1670         reg32 &= 0x3f;
1671
1672         /* 788nS - tRFC */
1673         switch (sysinfo->memory_frequency) {
1674         case 400: /* 5nS */
1675                 reg32 = ((78800 / 500) - reg32) & 0x1ff;
1676                 reg32 |= (0x8c << 16) | (0x0c << 10); /* 1 us */
1677                 break;
1678         case 533: /* 3.75nS */
1679                 reg32 = ((78800 / 375) - reg32) & 0x1ff;
1680                 reg32 |= (0xba << 16) | (0x10 << 10); /* 1 us */
1681                 break;
1682         case 667: /* 3nS */
1683                 reg32 = ((78800 / 300) - reg32) & 0x1ff;
1684                 reg32 |= (0xe9 << 16) | (0x14 << 10); /* 1 us */
1685                 break;
1686         }
1687
1688         temp_drt |= reg32;
1689
1690         MCHBAR32(C0DRT3) = temp_drt;
1691         MCHBAR32(C1DRT3) = temp_drt;
1692 }
1693
1694 static void sdram_set_channel_mode(struct sys_info *sysinfo)
1695 {
1696         u32 reg32;
1697
1698         printk_debug("Setting mode of operation for memory channels...");
1699
1700         if (sdram_capabilities_interleave() &&
1701                     ( ( sysinfo->banksize[0] + sysinfo->banksize[1] +
1702                         sysinfo->banksize[2] + sysinfo->banksize[3] ) ==
1703                       ( sysinfo->banksize[4] + sysinfo->banksize[5] +
1704                         sysinfo->banksize[6] + sysinfo->banksize[7] ) ) ) {
1705                 /* Both channels equipped with DIMMs of the same size */
1706
1707                 sysinfo->interleaved = 1;
1708         } else {
1709                 sysinfo->interleaved = 0;
1710         }
1711
1712         reg32 = MCHBAR32(DCC);
1713         reg32 &= ~(7 << 0);
1714
1715         if(sysinfo->interleaved) {
1716                 /* Dual Channel Interleaved */
1717                 printk_debug("Dual Channel Interleaved.\n");
1718                 reg32 |= (1 << 1);
1719         } else if (sysinfo->dimm[0] == SYSINFO_DIMM_NOT_POPULATED &&
1720                         sysinfo->dimm[1] == SYSINFO_DIMM_NOT_POPULATED) {
1721                 /* Channel 1 only */
1722                 printk_debug("Single Channel 1 only.\n");
1723                 reg32 |= (1 << 2);
1724         } else if (sdram_capabilities_dual_channel() && sysinfo->dimm[2] !=
1725                         SYSINFO_DIMM_NOT_POPULATED) {
1726                 /* Dual Channel Assymetric */
1727                 printk_debug("Dual Channel Assymetric.\n");
1728                 reg32 |= (1 << 0);
1729         } else {
1730                 /* All bits 0 means Single Channel 0 operation */
1731                 printk_debug("Single Channel 0 only.\n");
1732         }
1733
1734         reg32 |= (1 << 10);
1735
1736         MCHBAR32(DCC) = reg32;
1737
1738         PRINTK_DEBUG("DCC=0x%08x\n", MCHBAR32(DCC));
1739 }
1740
1741 static void sdram_program_pll_settings(void)
1742 {
1743         volatile u16 reg16;
1744         volatile u32 reg32;
1745
1746         const u8 HPLLGPLLPowerDown[] = {
1747                 0x90, /* 400MHz */
1748                 0x95, /* 533MHz */
1749                 0x00, /* --- */
1750                 0x8d, /* 667MHz */
1751         };
1752
1753         MCHBAR32(PLLMON) = 0x80800000;
1754
1755         reg32 = MCHBAR32(CLKCFG);
1756         reg32 &= (7 << 0);
1757
1758         reg16 = MCHBAR16(CPCTL);
1759         reg16 &= 0xff00;
1760         reg16 |= HPLLGPLLPowerDown[reg32];
1761         MCHBAR16(CPCTL) = reg16;
1762
1763         reg16 &= ~(1 << 11);
1764         MCHBAR16(CPCTL) = reg16;
1765
1766         reg16 = MCHBAR16(CPCTL);
1767 }
1768
1769 static void sdram_program_graphics_frequency(struct sys_info *sysinfo)
1770 {
1771         u8  reg8;
1772         u16 reg16;
1773         u8  freq, second_vco;
1774
1775 #define CRCLK_166MHz    0x00
1776 #define CRCLK_200MHz    0x01
1777 #define CRCLK_250MHz    0x03
1778 #define CRCLK_400MHz    0x05
1779
1780 #define CDCLK_200MHz    0x00
1781 #define CDCLK_320MHz    0x40
1782
1783         printk_debug ("Setting Graphics Frequency... \n");
1784
1785         reg16 = pci_read_config16(PCI_DEV(0,2,0), GCFC);
1786         reg16 |= (1<<11) | (1<<9);
1787         pci_write_config16(PCI_DEV(0,2,0), GCFC, reg16);
1788
1789         /* Program CPCTL according to FSB speed */
1790         reg16 = MCHBAR16(CPCTL);
1791         reg16 &= 0xff00;
1792
1793         switch (MCHBAR32(CLKCFG) & 0x7) {
1794         case 0: sysinfo->fsb_frequency = 400; break;    /* FSB400 */
1795         case 1: sysinfo->fsb_frequency = 533; break;    /* FSB533 */
1796         case 3: sysinfo->fsb_frequency = 667; break;    /* FSB667 */
1797         default: die("Unsupported FSB speed");
1798         }
1799
1800         switch (sysinfo->fsb_frequency) {
1801         case 533: reg16 |= 0x95; break; /* FSB533 */
1802         case 667: reg16 |= 0x8d; break; /* FSB667 */
1803         }
1804         MCHBAR16(CPCTL) = reg16;
1805
1806         /* Get graphics frequency capabilities */
1807         reg8 = (pci_read_config8(PCI_DEV(0, 0x00,0), 0xe5) & 0x0e) >> 1;
1808
1809         freq = CRCLK_250MHz;
1810         switch (reg8) {
1811         case 0:
1812                 if (MCHBAR32(DFT_STRAP1) & (1 << 20))
1813                         freq = CRCLK_250MHz;
1814                 else
1815                         freq = CRCLK_400MHz;
1816                 break;
1817         case 2: freq = CRCLK_250MHz; break;
1818         case 3: freq = CRCLK_200MHz; break;
1819         case 4: freq = CRCLK_166MHz; break;
1820         }
1821
1822         if (freq != CRCLK_400MHz) {
1823
1824                 reg8 = (pci_read_config8(PCI_DEV(0, 0x00,0), 0xe7) & 0x70) >> 4;
1825                 if (reg8==2)
1826                         freq = CRCLK_166MHz;
1827         }
1828
1829         if (i945_silicon_revision() == 0) {
1830                 sysinfo->mvco4x = 1;
1831         } else {
1832                 sysinfo->mvco4x = 0;
1833         }
1834
1835
1836         second_vco = 0;
1837
1838         if (MCHBAR32(DFT_STRAP1) & (1 << 20)) {
1839                 second_vco = 1;
1840         } else if ((i945_silicon_revision() > 0) && (freq == CRCLK_250MHz))  {
1841                 u16 mem = sysinfo->memory_frequency;
1842                 u16 fsb = sysinfo->fsb_frequency;
1843
1844                 if ( (fsb == 667 && mem == 533) ||
1845                      (fsb == 533 && mem == 533) ||
1846                      (fsb == 533 && mem == 400)) {
1847                         second_vco = 1;
1848                 }
1849
1850                 if (fsb == 667 && mem == 533)
1851                         sysinfo->mvco4x = 1;
1852         }
1853
1854         if (second_vco) {
1855                 printk_debug("Programming second TCO\n");
1856                 sysinfo->clkcfg_bit7=1;
1857         } else {
1858                 sysinfo->clkcfg_bit7=0;
1859         }
1860
1861         reg16 = pci_read_config16(PCI_DEV(0,2,0), GCFC);
1862         reg16 &= ~( (7 << 0) | (1 << 13) );
1863         reg16 |= freq;
1864         pci_write_config16(PCI_DEV(0,2,0), GCFC, reg16);
1865
1866         reg16 = pci_read_config16(PCI_DEV(0,2,0), GCFC);
1867         reg16 &= ~( (1<<7) | (7<<4) );
1868         if (MCHBAR32(DFT_STRAP1) & (1 << 20)) {
1869                 reg16 |= CDCLK_200MHz;
1870         } else {
1871                 reg16 |= CDCLK_320MHz;
1872         }
1873         pci_write_config16(PCI_DEV(0,2,0), GCFC, reg16);
1874
1875         reg16 = pci_read_config16(PCI_DEV(0,2,0), GCFC);
1876         reg16 &= ~( (1<<10) | (1<<8) );
1877         pci_write_config16(PCI_DEV(0,2,0), GCFC, reg16);
1878         reg16 |= (1<<10) | (1<<8);
1879         pci_write_config16(PCI_DEV(0,2,0), GCFC, reg16);
1880
1881         reg16 &= 0xf0ff;
1882         pci_write_config16(PCI_DEV(0,2,0), GCFC, reg16);
1883 }
1884
1885 static void sdram_program_memory_frequency(struct sys_info *sysinfo)
1886 {
1887         u32 clkcfg;
1888         u8 reg8;
1889
1890         printk_debug ("Setting Memory Frequency... ");
1891
1892         clkcfg = MCHBAR32(CLKCFG);
1893
1894         printk_debug("CLKCFG=0x%08x, ", clkcfg);
1895
1896         clkcfg &= ~( (1 << 12) | (1 << 7) | ( 7 << 4) );
1897
1898         if (sysinfo->mvco4x) {
1899                 printk_debug("MVCO 4x, ");
1900                 clkcfg &= ~(1 << 12);
1901         }
1902
1903         if (sysinfo->clkcfg_bit7) {
1904                 printk_debug("second VCO, ");
1905
1906                 clkcfg |= (1 << 7);
1907         }
1908
1909         switch (sysinfo->memory_frequency) {
1910         case 400: clkcfg |= (2 << 4); break;
1911         case 533: clkcfg |= (3 << 4); break;
1912         case 667: clkcfg |= (4 << 4); break;
1913         default: die("Target Memory Frequency Error");
1914         }
1915
1916         if (MCHBAR32(CLKCFG) == clkcfg) {
1917                 printk_debug ("ok (unchanged)\n");
1918                 return;
1919         }
1920
1921         MCHBAR32(CLKCFG) = clkcfg;
1922
1923         /* Make sure the following code is in the
1924          * cache before we execute it.
1925          */
1926         goto cache_code;
1927 vco_update:
1928         reg8 = pci_read_config8(PCI_DEV(0,0x1f,0), 0xa2);
1929         reg8 &= ~(1 << 7);
1930         pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8);
1931
1932
1933         clkcfg &= ~(1 << 10);
1934         MCHBAR32(CLKCFG) = clkcfg;
1935         clkcfg |= (1 << 10);
1936         MCHBAR32(CLKCFG) = clkcfg;
1937
1938
1939         __asm__ __volatile__ (
1940                 "       movl $0x100, %%ecx\n"
1941                 "delay_update:\n"
1942                 "       nop\n"
1943                 "       nop\n"
1944                 "       nop\n"
1945                 "       nop\n"
1946                 "       loop delay_update\n"
1947                 : /* No outputs */
1948                 : /* No inputs */
1949                 : "%ecx"
1950                 );
1951
1952
1953         clkcfg &= ~(1 << 10);
1954         MCHBAR32(CLKCFG) = clkcfg;
1955
1956         goto out;
1957 cache_code:
1958         goto vco_update;
1959 out:
1960
1961         printk_debug("CLKCFG=0x%08x, ", MCHBAR32(CLKCFG));
1962         printk_debug ("ok\n");
1963 }
1964
1965 static void sdram_program_clock_crossing(void)
1966 {
1967         u32 reg32;
1968         int idx = 0;
1969
1970         /**
1971          * The first two lines of each of these tables are for FSB533,
1972          * the following three lines are for FSB667. We ignore FSB400.
1973          * Thus we add the indices according to our clocks from CLKCFG.
1974          */
1975
1976         static const u32 data_clock_crossing[] = {
1977                 0x08040120, 0x00000000, /* DDR400 FSB533 */
1978                 0x00100401, 0x00000000, /* DDR533 FSB533 */
1979
1980                 0x04020120, 0x00000010, /* DDR400 FSB667 */
1981                 0x10040280, 0x00000040, /* DDR533 FSB667 */
1982                 0x00100401, 0x00000000  /* DDR667 FSB667 */
1983         };
1984
1985         static const u32 command_clock_crossing[] = {
1986                 0x00060108, 0x00000000, /* DDR400 FSB533 */
1987                 0x04020108, 0x00000000, /* DDR533 FSB533 */
1988
1989                 0x00040318, 0x00000000, /* DDR400 FSB667 */
1990                 0x04020118, 0x00000000, /* DDR533 FSB667 */
1991                 0x02010804, 0x00000000  /* DDR667 FSB667 */
1992         };
1993
1994         printk_debug("Programming Clock Crossing...");
1995         reg32 = MCHBAR32(CLKCFG);
1996
1997         printk_debug("MEM=");
1998         switch ((reg32 >> 4) & 7) {
1999         case 2: printk_debug("400"); idx += 0; break;
2000         case 3: printk_debug("533"); idx += 2; break;
2001         case 4: printk_debug("667"); idx += 4; break;
2002         default: printk_debug("RSVD\n"); return;
2003         }
2004
2005         printk_debug(" FSB=");
2006         switch (reg32 & 7) {
2007         case 0: printk_debug("400\n"); return;
2008         case 1: printk_debug("533"); idx += 0; break;
2009         case 3: printk_debug("667"); idx += 4; break;
2010         default: printk_debug("RSVD\n"); return;
2011         }
2012
2013         MCHBAR32(C0DCCFT + 0) = data_clock_crossing[idx];
2014         MCHBAR32(C0DCCFT + 4) = data_clock_crossing[idx + 1];
2015         MCHBAR32(C1DCCFT + 0) = data_clock_crossing[idx];
2016         MCHBAR32(C1DCCFT + 4) = data_clock_crossing[idx + 1];
2017
2018         MCHBAR32(CCCFT + 0) = command_clock_crossing[idx];
2019         MCHBAR32(CCCFT + 4) = command_clock_crossing[idx + 1];
2020
2021         printk_debug("... ok\n");
2022 }
2023
2024 static void sdram_disable_fast_dispatch(void)
2025 {
2026         u32 reg32;
2027
2028         reg32 = MCHBAR32(FSBPMC3);
2029         reg32 |= (1 << 1);
2030         MCHBAR32(FSBPMC3) = reg32;
2031
2032         reg32 = MCHBAR32(SBTEST);
2033         reg32 |= (3 << 1);
2034         MCHBAR32(SBTEST) = reg32;
2035 }
2036
2037 static void sdram_pre_jedec_initialization(void)
2038 {
2039         u32 reg32;
2040
2041         reg32 = MCHBAR32(WCC);
2042         reg32 &= 0x113ff3ff;
2043         reg32 |= (4 << 29) | (3 << 25) | (1 << 10);
2044         MCHBAR32(WCC) = reg32;
2045
2046         MCHBAR32(SMVREFC) |= (1 << 6);
2047
2048         MCHBAR32(MMARB0) &= ~(3 << 17);
2049         MCHBAR32(MMARB0) |= (1 << 21) | (1 << 16);
2050
2051         MCHBAR32(MMARB1) &= ~(7 << 8);
2052         MCHBAR32(MMARB1) |= (3 << 8);
2053
2054         MCHBAR32(C0AIT) = 0x000006c4;
2055         MCHBAR32(C0AIT+4) = 0x871a066d;
2056
2057         MCHBAR32(C1AIT) = 0x000006c4;
2058         MCHBAR32(C1AIT+4) = 0x871a066d;
2059 }
2060
2061 #define EA_DUALCHANNEL_XOR_BANK_RANK_MODE       (0xd4 << 24)
2062 #define EA_DUALCHANNEL_XOR_BANK_MODE            (0xf4 << 24)
2063 #define EA_DUALCHANNEL_BANK_RANK_MODE           (0xc2 << 24)
2064 #define EA_DUALCHANNEL_BANK_MODE                (0xe2 << 24)
2065 #define EA_SINGLECHANNEL_XOR_BANK_RANK_MODE     (0x91 << 24)
2066 #define EA_SINGLECHANNEL_XOR_BANK_MODE          (0xb1 << 24)
2067 #define EA_SINGLECHANNEL_BANK_RANK_MODE         (0x80 << 24)
2068 #define EA_SINGLECHANNEL_BANK_MODE              (0xa0 << 24)
2069
2070 static void sdram_enhanced_addressing_mode(struct sys_info *sysinfo)
2071 {
2072         u32 chan0 = 0, chan1 = 0;
2073         int chan0_dualsided, chan1_dualsided, chan0_populated, chan1_populated;
2074
2075         chan0_populated =  (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED ||
2076                         sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED);
2077         chan1_populated = (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED ||
2078                         sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED);
2079         chan0_dualsided = (sysinfo->banksize[1] || sysinfo->banksize[3]);
2080         chan1_dualsided = (sysinfo->banksize[5] || sysinfo->banksize[7]);
2081
2082         if (sdram_capabilities_enhanced_addressing_xor()) {
2083                 if (!sysinfo->interleaved) {
2084                         /* Single Channel & Dual Channel Assymetric */
2085                         if (chan0_populated) {
2086                                 if (chan0_dualsided) {
2087                                         chan0 = EA_SINGLECHANNEL_XOR_BANK_RANK_MODE;
2088                                 } else {
2089                                         chan0 = EA_SINGLECHANNEL_XOR_BANK_MODE;
2090                                 }
2091                         }
2092                         if (chan1_populated) {
2093                                 if (chan1_dualsided) {
2094                                         chan1 = EA_SINGLECHANNEL_XOR_BANK_RANK_MODE;
2095                                 } else {
2096                                         chan1 = EA_SINGLECHANNEL_XOR_BANK_MODE;
2097                                 }
2098                         }
2099                 } else {
2100                         /* Interleaved has always both channels populated */
2101                         if (chan0_dualsided) {
2102                                 chan0 = EA_DUALCHANNEL_XOR_BANK_RANK_MODE;
2103                         } else {
2104                                 chan0 = EA_DUALCHANNEL_XOR_BANK_MODE;
2105                         }
2106
2107                         if (chan1_dualsided) {
2108                                 chan1 = EA_DUALCHANNEL_XOR_BANK_RANK_MODE;
2109                         } else {
2110                                 chan1 = EA_DUALCHANNEL_XOR_BANK_MODE;
2111                         }
2112                 }
2113         } else {
2114                 if (!sysinfo->interleaved) {
2115                         /* Single Channel & Dual Channel Assymetric */
2116                         if (chan0_populated) {
2117                                 if (chan0_dualsided) {
2118                                         chan0 = EA_SINGLECHANNEL_BANK_RANK_MODE;
2119                                 } else {
2120                                         chan0 = EA_SINGLECHANNEL_BANK_MODE;
2121                                 }
2122                         }
2123                         if (chan1_populated) {
2124                                 if (chan1_dualsided) {
2125                                         chan1 = EA_SINGLECHANNEL_BANK_RANK_MODE;
2126                                 } else {
2127                                         chan1 = EA_SINGLECHANNEL_BANK_MODE;
2128                                 }
2129                         }
2130                 } else {
2131                         /* Interleaved has always both channels populated */
2132                         if (chan0_dualsided) {
2133                                 chan0 = EA_DUALCHANNEL_BANK_RANK_MODE;
2134                         } else {
2135                                 chan0 = EA_DUALCHANNEL_BANK_MODE;
2136                         }
2137
2138                         if (chan1_dualsided) {
2139                                 chan1 = EA_DUALCHANNEL_BANK_RANK_MODE;
2140                         } else {
2141                                 chan1 = EA_DUALCHANNEL_BANK_MODE;
2142                         }
2143                 }
2144         }
2145
2146         MCHBAR32(C0DRC1) &= 0x00ffffff;
2147         MCHBAR32(C0DRC1) |= chan0;
2148         MCHBAR32(C1DRC1) &= 0x00ffffff;
2149         MCHBAR32(C1DRC1) |= chan1;
2150 }
2151
2152 static void sdram_post_jedec_initialization(struct sys_info *sysinfo)
2153 {
2154         u32 reg32;
2155
2156         /* Enable Channel XORing for Dual Channel Interleave */
2157         if (sysinfo->interleaved) {
2158                 reg32 = MCHBAR32(DCC);
2159 #if CHANNEL_XOR_RANDOMIZATION
2160                 reg32 &= ~(1 << 10);
2161                 reg32 |= (1 << 9);
2162 #else
2163                 reg32 &= ~(1 << 9);
2164 #endif
2165                 MCHBAR32(DCC) = reg32;
2166         }
2167
2168         /* DRAM mode optimizations */
2169         sdram_enhanced_addressing_mode(sysinfo);
2170
2171         reg32 = MCHBAR32(FSBPMC3);
2172         reg32 &= ~(1 << 1);
2173         MCHBAR32(FSBPMC3) = reg32;
2174
2175         reg32 = MCHBAR32(SBTEST);
2176         reg32 &= ~(1 << 2);
2177         MCHBAR32(SBTEST) = reg32;
2178
2179         reg32 = MCHBAR32(SBOCC);
2180         reg32 &= 0xffbdb6ff;
2181         reg32 |= (0xbdb6 << 8) | (1 << 0);
2182         MCHBAR32(SBOCC) = reg32;
2183 }
2184
2185 static void sdram_power_management(struct sys_info *sysinfo)
2186 {
2187         u8 reg8;
2188         u16 reg16;
2189         u32 reg32;
2190         int integrated_graphics = 1;
2191         int i;
2192
2193         reg32 = MCHBAR32(C0DRT2);
2194         reg32 &= 0xffffff00;
2195         /* Idle timer = 8 clocks, CKE idle timer = 16 clocks */
2196         reg32 |= (1 << 5) | (1 << 4);
2197         MCHBAR32(C0DRT2) = reg32;
2198
2199         reg32 = MCHBAR32(C1DRT2);
2200         reg32 &= 0xffffff00;
2201         /* Idle timer = 8 clocks, CKE idle timer = 16 clocks */
2202         reg32 |= (1 << 5) | (1 << 4);
2203         MCHBAR32(C1DRT2) = reg32;
2204
2205         reg32 = MCHBAR32(C0DRC1);
2206
2207         reg32 |= (1 << 12) | (1 << 11);
2208         MCHBAR32(C0DRC1) = reg32;
2209
2210         reg32 = MCHBAR32(C1DRC1);
2211
2212         reg32 |= (1 << 12) | (1 << 11);
2213         MCHBAR32(C1DRC1) = reg32;
2214
2215         if (i945_silicon_revision()>1) {
2216                 MCHBAR16(UPMC1) = 0x1010;
2217         } else {
2218                 /* Rev 0 and 1 */
2219                 MCHBAR16(UPMC1) = 0x0010;
2220         }
2221
2222         reg16 = MCHBAR16(UPMC2);
2223         reg16 &= 0xfc00;
2224         reg16 |= 0x0100;
2225         MCHBAR16(UPMC2) = reg16;
2226
2227         MCHBAR32(UPMC3) = 0x000f06ff;
2228
2229         for (i=0; i<5; i++) {
2230                 MCHBAR32(UPMC3) &= ~(1 << 16);
2231                 MCHBAR32(UPMC3) |= (1 << 16);
2232         }
2233
2234         MCHBAR32(GIPMC1) = 0x8000000c;
2235
2236         reg16 = MCHBAR16(CPCTL);
2237         reg16 &= ~(7 << 11);
2238         if (i945_silicon_revision()>2) {
2239                 reg16 |= (6 << 11);
2240         } else {
2241                 reg16 |= (4 << 11);
2242         }
2243         MCHBAR16(CPCTL) = reg16;
2244
2245 #if 0
2246         /* This is set later in the game */
2247         if ((MCHBAR32(ECO) & (1 << 16)) != 0) {
2248 #else
2249         if (i945_silicon_revision() != 0) {
2250 #endif
2251                 switch (sysinfo->fsb_frequency) {
2252                 case 667: MCHBAR32(HGIPMC2) = 0x0d590d59; break;
2253                 case 533: MCHBAR32(HGIPMC2) = 0x155b155b; break;
2254                 }
2255         } else {
2256                 switch (sysinfo->fsb_frequency) {
2257                 case 667: MCHBAR32(HGIPMC2) = 0x09c409c4; break;
2258                 case 533: MCHBAR32(HGIPMC2) = 0x0fa00fa0; break;
2259                 }
2260         }
2261
2262         MCHBAR32(FSBPMC1) = 0x8000000c;
2263
2264         reg32 = MCHBAR32(C2C3TT);
2265         reg32 &= 0xffff0000;
2266         switch (sysinfo->fsb_frequency) {
2267         case 667: reg32 |= 0x0600; break;
2268         case 533: reg32 |= 0x0480; break;
2269         }
2270         MCHBAR32(C2C3TT) = reg32;
2271
2272         reg32 = MCHBAR32(C3C4TT);
2273         reg32 &= 0xffff0000;
2274         switch (sysinfo->fsb_frequency) {
2275         case 667: reg32 |= 0x0b80; break;
2276         case 533: reg32 |= 0x0980; break;
2277         }
2278         MCHBAR32(C3C4TT) = reg32;
2279
2280         if (i945_silicon_revision() == 0) {
2281                 MCHBAR32(ECO) &= ~(1 << 16);
2282         } else {
2283                 MCHBAR32(ECO) |= (1 << 16);
2284         }
2285
2286 #if 0
2287         if (i945_silicon_revision() == 0) {
2288                 MCHBAR32(FSBPMC3) &= ~(1 << 29);
2289         } else {
2290                 MCHBAR32(FSBPMC3) |= (1 << 29);
2291         }
2292 #endif
2293         MCHBAR32(FSBPMC3) &= ~(1 << 29);
2294
2295         MCHBAR32(FSBPMC3) |= (1 << 21);
2296
2297         MCHBAR32(FSBPMC3) &= ~(1 << 19);
2298
2299         MCHBAR32(FSBPMC3) &= ~(1 << 13);
2300
2301         reg32 = MCHBAR32(FSBPMC4);
2302         reg32 &= ~(3 << 24);
2303         reg32 |= ( 2 << 24);
2304         MCHBAR32(FSBPMC4) = reg32;
2305
2306         MCHBAR32(FSBPMC4) |= (1 << 21);
2307
2308         MCHBAR32(FSBPMC4) |= (1 << 5);
2309
2310         if (i945_silicon_revision() < 2) {
2311                 /* stepping 0 and 1 */
2312                 MCHBAR32(FSBPMC4) &= ~(1 << 4);
2313         } else {
2314                 MCHBAR32(FSBPMC4) |= (1 << 4);
2315         }
2316
2317         reg8 = pci_read_config8(PCI_DEV(0,0x0,0), 0xfc);
2318         reg8 |= (1 << 4);
2319         pci_write_config8(PCI_DEV(0, 0x0, 0), 0xfc, reg8);
2320
2321         reg8 = pci_read_config8(PCI_DEV(0,0x2,0), 0xc1);
2322         reg8 |= (1 << 2);
2323         pci_write_config8(PCI_DEV(0, 0x2, 0), 0xc1, reg8);
2324
2325         if (integrated_graphics) {
2326                 MCHBAR16(MIPMC4) = 0x0468;
2327                 MCHBAR16(MIPMC5) = 0x046c;
2328                 MCHBAR16(MIPMC6) = 0x046c;
2329         } else {
2330                 MCHBAR16(MIPMC4) = 0x6468;
2331                 MCHBAR16(MIPMC5) = 0x646c;
2332                 MCHBAR16(MIPMC6) = 0x646c;
2333         }
2334
2335         reg32 = MCHBAR32(PMCFG);
2336         reg32 &= ~(3 << 17);
2337         reg32 |= (2 << 17);
2338         reg32 |= (1 << 4);
2339         MCHBAR32(PMCFG) = reg32;
2340
2341         reg32 = MCHBAR32(0xc30);
2342         reg32 &= 0xffffff00;
2343         reg32 |= 0x01;
2344         MCHBAR32(0xc30) = reg32;
2345
2346         MCHBAR32(0xb18) &= ~(1 << 21);
2347 }
2348
2349 static void sdram_thermal_management(void)
2350 {
2351         /* The Thermal Sensors for DIMMs at 0x50, 0x52 are at I2C addr
2352          * 0x30/0x32.
2353          */
2354
2355         /* Explicitly set to 0 */
2356         MCHBAR8(TCO1) = 0x00;
2357         MCHBAR8(TCO0) = 0x00;
2358 }
2359
2360 #include "rcven.c"
2361
2362 static void sdram_program_receive_enable(struct sys_info *sysinfo)
2363 {
2364         MCHBAR32(REPC) |= (1 << 0);
2365
2366         receive_enable_adjust(sysinfo);
2367
2368         MCHBAR32(C0DRC1) |= (1 << 6);
2369         MCHBAR32(C1DRC1) |= (1 << 6);
2370         MCHBAR32(C0DRC1) &= ~(1 << 6);
2371         MCHBAR32(C1DRC1) &= ~(1 << 6);
2372
2373         MCHBAR32(MIPMC3) |= (0x0f << 0);
2374 }
2375
2376 /**
2377  * @brief Enable On-Die Termination for DDR2.
2378  *
2379  */
2380
2381 static void sdram_on_die_termination(struct sys_info *sysinfo)
2382 {
2383         static const u32 odt[] = {
2384                 0x00024911, 0xe0010000,
2385                 0x00049211, 0xe0020000,
2386                 0x0006db11, 0xe0030000,
2387         };
2388
2389         u32 reg32;
2390         int cas;
2391
2392         reg32 = MCHBAR32(ODTC);
2393         reg32 &= ~(3 << 16);
2394         reg32 |= (1 << 14) | (1 << 6) | (2 << 16);
2395         MCHBAR32(ODTC) = reg32;
2396
2397         if ( !(sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED &&
2398                         sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED) ) {
2399                 printk_debug("one dimm per channel config.. \n");
2400
2401                 reg32 = MCHBAR32(C0ODT);
2402                 reg32 &= ~(7 << 28);
2403                 MCHBAR32(C0ODT) = reg32;
2404                 reg32 = MCHBAR32(C1ODT);
2405                 reg32 &= ~(7 << 28);
2406                 MCHBAR32(C1ODT) = reg32;
2407         }
2408
2409         cas = sysinfo->cas;
2410
2411         reg32 = MCHBAR32(C0ODT) & 0xfff00000;
2412         reg32 |= odt[(cas-3) * 2];
2413         MCHBAR32(C0ODT) = reg32;
2414
2415         reg32 = MCHBAR32(C1ODT) & 0xfff00000;
2416         reg32 |= odt[(cas-3) * 2];
2417         MCHBAR32(C1ODT) = reg32;
2418
2419         reg32 = MCHBAR32(C0ODT + 4) & 0x1fc8ffff;
2420         reg32 |= odt[((cas-3) * 2) + 1];
2421         MCHBAR32(C0ODT + 4) = reg32;
2422
2423         reg32 = MCHBAR32(C1ODT + 4) & 0x1fc8ffff;
2424         reg32 |= odt[((cas-3) * 2) + 1];
2425         MCHBAR32(C1ODT + 4) = reg32;
2426 }
2427
2428 /**
2429  * @brief Enable clocks to populated sockets
2430  */
2431
2432 static void sdram_enable_memory_clocks(struct sys_info *sysinfo)
2433 {
2434         u8 clocks[2] = { 0, 0 };
2435
2436         if (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED)
2437                 clocks[0] |= (1 << 0) | (1 << 1);
2438
2439         if (sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED)
2440                 clocks[0] |= (1 << 2) | (1 << 3);
2441
2442         if (sysinfo->dimm[2] != SYSINFO_DIMM_NOT_POPULATED)
2443                 clocks[1] |= (1 << 0) | (1 << 1);
2444
2445         if (sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED)
2446                 clocks[1] |= (1 << 2) | (1 << 3);
2447
2448 #ifdef OVERRIDE_CLOCK_DISABLE
2449         clocks[0] = 0xf;
2450         clocks[1] = 0xf;
2451 #endif
2452
2453         MCHBAR8(C0DCLKDIS) = clocks[0];
2454         MCHBAR8(C1DCLKDIS) = clocks[1];
2455 }
2456
2457 #define RTT_ODT_75_OHM  (1 << 5)
2458 #define RTT_ODT_150_OHM (1 << 9)
2459
2460 #define EMRS_OCD_DEFAULT        ( (1 << 12) | (1 << 11) | (1 << 10) )
2461
2462 #define MRS_CAS_3       (3 << 7)
2463 #define MRS_CAS_4       (4 << 7)
2464 #define MRS_CAS_5       (5 << 7)
2465
2466 #define MRS_TWR_3       (2 << 12)
2467 #define MRS_TWR_4       (3 << 12)
2468 #define MRS_TWR_5       (4 << 12)
2469
2470 #define MRS_BT          (1 << 6)
2471
2472 #define MRS_BL4         (2 << 3)
2473 #define MRS_BL8         (3 << 3)
2474
2475 static void sdram_jedec_enable(struct sys_info *sysinfo)
2476 {
2477         int i, nonzero;
2478         u32 bankaddr = 0, tmpaddr, mrsaddr = 0;
2479
2480         for (i = 0, nonzero = -1; i < 8; i++) {
2481                 if (sysinfo->banksize[i]  == 0) {
2482                         continue;
2483                 }
2484
2485                 printk_debug("jedec enable sequence: bank %d\n", i);
2486                 switch (i) {
2487                 case 0:
2488                         /* Start at address 0 */
2489                         bankaddr = 0;
2490                         break;
2491                 case 4:
2492                         if (sysinfo->interleaved) {
2493                                 bankaddr = 0x40;
2494                                 break;
2495                         }
2496                 default:
2497                         if (nonzero != -1) {
2498                                 printk_debug("bankaddr from bank size of rank %d\n", nonzero);
2499                                 bankaddr += (1 << sysinfo->banksize[nonzero]) << (sysinfo->interleaved?28:27);
2500                                 break;
2501                         }
2502                         /* No populated bank hit before. Start at address 0 */
2503                         bankaddr = 0;
2504                 }
2505
2506                 /* We have a bank with a non-zero size.. Remember it
2507                  * for the next offset we have to calculate
2508                  */
2509                 nonzero = i;
2510
2511                 /* Get CAS latency set up */
2512                 switch (sysinfo->cas) {
2513                 case 5: mrsaddr = MRS_CAS_5; break;
2514                 case 4: mrsaddr = MRS_CAS_4; break;
2515                 case 3: mrsaddr = MRS_CAS_3; break;
2516                 default: die("Jedec Error (CAS).\n");
2517                 }
2518
2519                 /* Get tWR set */
2520                 switch (sysinfo->twr) {
2521                 case 5: mrsaddr |= MRS_TWR_5; break;
2522                 case 4: mrsaddr |= MRS_TWR_4; break;
2523                 case 3: mrsaddr |= MRS_TWR_3; break;
2524                 default: die("Jedec Error (tWR).\n");
2525                 }
2526
2527                 /* Interleaved */
2528                 if (sysinfo->interleaved) {
2529                         mrsaddr |= MRS_BT;
2530                         mrsaddr = mrsaddr << 1;
2531                 }
2532
2533                 /* Only burst length 8 supported */
2534                 mrsaddr |= MRS_BL8;
2535
2536                 /* Apply NOP */
2537                 PRINTK_DEBUG("Apply NOP\n");
2538                 do_ram_command(RAM_COMMAND_NOP);
2539                 ram_read32(bankaddr);
2540
2541                 /* Precharge all banks */
2542                 PRINTK_DEBUG("All Banks Precharge\n");
2543                 do_ram_command(RAM_COMMAND_PRECHARGE);
2544                 ram_read32(bankaddr);
2545
2546                 /* Extended Mode Register Set (2) */
2547                 PRINTK_DEBUG("Extended Mode Register Set(2)\n");
2548                 do_ram_command(RAM_COMMAND_EMRS | RAM_EMRS_2);
2549                 ram_read32(bankaddr);
2550
2551                 /* Extended Mode Register Set (3) */
2552                 PRINTK_DEBUG("Extended Mode Register Set(3)\n");
2553                 do_ram_command(RAM_COMMAND_EMRS | RAM_EMRS_3);
2554                 ram_read32(bankaddr);
2555
2556                 /* Extended Mode Register Set */
2557                 PRINTK_DEBUG("Extended Mode Register Set\n");
2558                 do_ram_command(RAM_COMMAND_EMRS | RAM_EMRS_1);
2559                 tmpaddr = bankaddr;
2560                 if (!sdram_capabilities_dual_channel()) {
2561                         tmpaddr |= RTT_ODT_75_OHM;
2562                 } else if (sysinfo->interleaved) {
2563                         tmpaddr |= (RTT_ODT_150_OHM << 1);
2564                 } else {
2565                         tmpaddr |= RTT_ODT_150_OHM;
2566                 }
2567                 ram_read32(tmpaddr);
2568
2569                 /* Mode Register Set: Reset DLLs */
2570                 PRINTK_DEBUG("MRS: Reset DLLs\n");
2571                 do_ram_command(RAM_COMMAND_MRS);
2572                 tmpaddr = bankaddr;
2573                 tmpaddr |= mrsaddr;
2574                 /* Set DLL reset bit */
2575                 if (sysinfo->interleaved)
2576                         tmpaddr |= (1 << 12);
2577                 else
2578                         tmpaddr |= (1 << 11);
2579                 ram_read32(tmpaddr);
2580
2581                 /* Precharge all banks */
2582                 PRINTK_DEBUG("All Banks Precharge\n");
2583                 do_ram_command(RAM_COMMAND_PRECHARGE);
2584                 ram_read32(bankaddr);
2585
2586                 /* CAS before RAS Refresh */
2587                 PRINTK_DEBUG("CAS before RAS\n");
2588                 do_ram_command(RAM_COMMAND_CBR);
2589
2590                 /* CBR wants two READs */
2591                 ram_read32(bankaddr);
2592                 ram_read32(bankaddr);
2593
2594                 /* Mode Register Set: Enable DLLs */
2595                 PRINTK_DEBUG("MRS: Enable DLLs\n");
2596                 do_ram_command(RAM_COMMAND_MRS);
2597
2598                 tmpaddr = bankaddr;
2599                 tmpaddr |= mrsaddr;
2600                 ram_read32(tmpaddr);
2601
2602                 /* Extended Mode Register Set */
2603                 PRINTK_DEBUG("Extended Mode Register Set: ODT/OCD\n");
2604                 do_ram_command(RAM_COMMAND_EMRS | RAM_EMRS_1);
2605
2606                 tmpaddr = bankaddr;
2607                 if (!sdram_capabilities_dual_channel()) {
2608
2609                         tmpaddr |= RTT_ODT_75_OHM | EMRS_OCD_DEFAULT;
2610                 } else if (sysinfo->interleaved) {
2611                         tmpaddr |= ((RTT_ODT_150_OHM | EMRS_OCD_DEFAULT) << 1);
2612                 } else {
2613                         tmpaddr |= RTT_ODT_150_OHM | EMRS_OCD_DEFAULT;
2614                 }
2615                 ram_read32(tmpaddr);
2616
2617                 /* Extended Mode Register Set */
2618                 PRINTK_DEBUG("Extended Mode Register Set: OCD Exit\n");
2619                 do_ram_command(RAM_COMMAND_EMRS | RAM_EMRS_1);
2620
2621                 tmpaddr = bankaddr;
2622                 if (!sdram_capabilities_dual_channel()) {
2623                         tmpaddr |= RTT_ODT_75_OHM;
2624                 } else if (sysinfo->interleaved) {
2625                         tmpaddr |= (RTT_ODT_150_OHM << 1);
2626                 } else {
2627                         tmpaddr |= RTT_ODT_150_OHM;
2628                 }
2629                 ram_read32(tmpaddr);
2630         }
2631 }
2632
2633 static void sdram_init_complete(void)
2634 {
2635         PRINTK_DEBUG("Normal Operation\n");
2636         do_ram_command(RAM_COMMAND_NORMAL);
2637 }
2638
2639 static void sdram_setup_processor_side(void)
2640 {
2641         if (i945_silicon_revision() == 0)
2642                 MCHBAR32(FSBPMC3) |= (1 << 2);
2643
2644         MCHBAR8(0xb00) |= 1;
2645
2646         if (i945_silicon_revision() == 0)
2647                 MCHBAR32(SLPCTL) |= (1 << 8);
2648 }
2649
2650 #define BOOT_MODE_RESUME        1
2651 #define BOOT_MODE_NORMAL        0
2652
2653 /**
2654  * @param boot_mode: 0 = normal, 1 = resume
2655  */
2656 void sdram_initialize(int boot_mode)
2657 {
2658         struct sys_info sysinfo;
2659         u8 reg8, cas_mask;
2660
2661         sdram_detect_errors();
2662
2663         printk_debug ("Setting up RAM controller.\n");
2664
2665         memset(&sysinfo, 0, sizeof(sysinfo));
2666
2667         /* Look at the type of DIMMs and verify all DIMMs are x8 or x16 width */
2668         sdram_get_dram_configuration(&sysinfo);
2669
2670         /* Check whether we have stacked DIMMs */
2671         sdram_verify_package_type(&sysinfo);
2672
2673         /* Determine common CAS */
2674         cas_mask = sdram_possible_cas_latencies(&sysinfo);
2675
2676         /* Choose Common Frequency */
2677         sdram_detect_cas_latency_and_ram_speed(&sysinfo, cas_mask);
2678
2679         /* Determine smallest common tRAS */
2680         sdram_detect_smallest_tRAS(&sysinfo);
2681
2682         /* Determine tRP */
2683         sdram_detect_smallest_tRP(&sysinfo);
2684
2685         /* Determine tRCD */
2686         sdram_detect_smallest_tRCD(&sysinfo);
2687
2688         /* Determine smallest refresh period */
2689         sdram_detect_smallest_refresh(&sysinfo);
2690
2691         /* Verify all DIMMs support burst length 8 */
2692         sdram_verify_burst_length(&sysinfo);
2693
2694         /* determine tWR */
2695         sdram_detect_smallest_tWR(&sysinfo);
2696
2697         /* Determine DIMM size parameters (rows, columns banks) */
2698         sdram_detect_dimm_size(&sysinfo);
2699
2700         /* determine tRFC */
2701         sdram_detect_smallest_tRFC(&sysinfo);
2702
2703         /* Program PLL settings */
2704         sdram_program_pll_settings();
2705
2706         /* Program Graphics Frequency */
2707         sdram_program_graphics_frequency(&sysinfo);
2708
2709         /* Program System Memory Frequency */
2710         sdram_program_memory_frequency(&sysinfo);
2711
2712         /* Determine Mode of Operation (Interleaved etc) */
2713         sdram_set_channel_mode(&sysinfo);
2714
2715         /* Program Clock Crossing values */
2716         sdram_program_clock_crossing();
2717
2718         /* Disable fast dispatch */
2719         sdram_disable_fast_dispatch();
2720
2721         /* Enable WIODLL Power Down in ACPI states */
2722         MCHBAR32(C0DMC) |= (1 << 24);
2723         MCHBAR32(C1DMC) |= (1 << 24);
2724
2725         /* Program DRAM Row Boundary/Attribute Registers */
2726
2727         if (boot_mode != BOOT_MODE_RESUME) {
2728                 /* program row size DRB and set TOLUD */
2729                 sdram_program_row_boundaries(&sysinfo);
2730
2731                 /* program page size DRA */
2732                 sdram_set_row_attributes(&sysinfo);
2733         }
2734
2735         /* Program CxBNKARC */
2736         sdram_set_bank_architecture(&sysinfo);
2737
2738         /* Program DRAM Timing and Control registers based on SPD */
2739         sdram_set_timing_and_control(&sysinfo);
2740
2741         /* On-Die Termination Adjustment */
2742         sdram_on_die_termination(&sysinfo);
2743
2744         /* Pre Jedec Initialization */
2745         sdram_pre_jedec_initialization();
2746
2747         /* Perform System Memory IO Initialization */
2748         sdram_initialize_system_memory_io(&sysinfo);
2749
2750         /* Perform System Memory IO Buffer Enable */
2751         sdram_enable_system_memory_io(&sysinfo);
2752
2753         /* Enable System Memory Clocks */
2754         sdram_enable_memory_clocks(&sysinfo);
2755
2756         if (boot_mode != BOOT_MODE_RESUME) {
2757                 /* Jedec Initialization sequence */
2758                 sdram_jedec_enable(&sysinfo);
2759         }
2760
2761         /* Program Power Management Registers */
2762         sdram_power_management(&sysinfo);
2763
2764         /* Post Jedec Init */
2765         sdram_post_jedec_initialization(&sysinfo);
2766
2767         /* Program DRAM Throttling */
2768         sdram_thermal_management();
2769
2770         /* Normal Operations */
2771         sdram_init_complete();
2772
2773         /* Program Receive Enable Timings */
2774         sdram_program_receive_enable(&sysinfo);
2775
2776         /* Enable Periodic RCOMP */
2777         sdram_enable_rcomp();
2778
2779         /* Tell ICH7 that we're done */
2780         reg8 = pci_read_config8(PCI_DEV(0,0x1f,0), 0xa2);
2781         reg8 &= ~(1 << 7);
2782         pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8);
2783
2784         printk_debug("RAM initialization finished.\n");
2785
2786         sdram_setup_processor_side();
2787 }
2788