2 * This file is part of the coreboot project.
4 * Copyright (C) 2007-2009 coresystems GmbH
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <console/console.h>
23 #include <device/device.h>
24 #include <device/pci.h>
25 #include <device/pci_ids.h>
26 #include <device/hypertransport.h>
31 #include <boot/tables.h>
35 int get_pcie_bar(u32 *base, u32 *len)
43 dev = dev_find_slot(0, PCI_DEVFN(0, 0));
47 pciexbar_reg = pci_read_config32(dev, 0x48);
49 if (!(pciexbar_reg & (1 << 0)))
52 switch ((pciexbar_reg >> 1) & 3) {
54 *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28));
55 *len = 256 * 1024 * 1024;
58 *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));
59 *len = 128 * 1024 * 1024;
62 *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26));
63 *len = 64 * 1024 * 1024;
70 /* in arch/i386/boot/tables.c */
71 extern uint64_t high_tables_base, high_tables_size;
74 uint64_t uma_memory_base=0, uma_memory_size=0;
76 int add_northbridge_resources(struct lb_memory *mem)
78 u32 pcie_config_base, pcie_config_size;
80 printk_debug("Adding UMA memory area\n");
81 lb_add_memory_range(mem, LB_MEM_RESERVED,
82 uma_memory_base, uma_memory_size);
84 printk_debug("Adding PCIe config bar\n");
85 get_pcie_bar(&pcie_config_base, &pcie_config_size);
86 lb_add_memory_range(mem, LB_MEM_RESERVED,
87 pcie_config_base, pcie_config_size);
92 static void ram_resource(device_t dev, unsigned long index, unsigned long basek,
95 struct resource *resource;
97 resource = new_resource(dev, index);
98 resource->base = ((resource_t) basek) << 10;
99 resource->size = ((resource_t) sizek) << 10;
100 resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE |
101 IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
104 static void tolm_test(void *gp, struct device *dev, struct resource *new)
106 struct resource **best_p = gp;
107 struct resource *best;
109 if (!best || (best->base > new->base)) {
115 static uint32_t find_pci_tolm(struct bus *bus)
117 struct resource *min;
120 search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test,
123 if (min && tolm > min->base) {
129 #if CONFIG_HAVE_HIGH_TABLES==1
130 #define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB
131 extern uint64_t high_tables_base, high_tables_size;
134 static void pci_domain_set_resources(device_t dev)
139 unsigned long long tomk;
141 /* Can we find out how much memory we can use at most
144 pci_tolm = find_pci_tolm(&dev->link[0]);
145 printk_debug("pci_tolm: 0x%x\n", pci_tolm);
147 printk_spew("Base of stolen memory: 0x%08x\n",
148 pci_read_config32(dev_find_slot(0, PCI_DEVFN(2, 0)), 0x5c));
150 tolud = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), 0x9c);
151 printk_spew("Top of Low Used DRAM: 0x%08x\n", tolud << 24);
155 /* Note: subtract IGD device and TSEG */
156 reg8 = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), 0x9e);
159 printk_debug("TSEG decoded, subtracting ");
165 break; /* TSEG = 1M */
168 break; /* TSEG = 2M */
171 break; /* TSEG = 8M */
174 printk_debug("%dM\n", tseg_size >> 10);
178 reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)), GGC);
181 printk_debug("IGD decoded, subtracting ");
193 printk_debug("%dM UMA\n", uma_size >> 10);
196 /* For reserving UMA memory in the memory map */
197 uma_memory_base = tomk * 1024ULL;
198 uma_memory_size = uma_size * 1024ULL;
201 /* The following needs to be 2 lines, otherwise the second
204 printk_info("Available memory: %dK", (uint32_t)tomk);
205 printk_info(" (%dM)\n", (uint32_t)(tomk >> 10));
207 /* Report the memory regions */
208 ram_resource(dev, 3, 0, 640);
209 ram_resource(dev, 4, 768, (tomk - 768));
210 if (tomk > 4 * 1024 * 1024) {
211 ram_resource(dev, 5, 4096 * 1024, tomk - 4 * 1024 * 1024);
214 assign_resources(&dev->link[0]);
216 #if CONFIG_HAVE_HIGH_TABLES==1
217 /* Leave some space for ACPI, PIRQ and MP tables */
218 high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024;
219 high_tables_size = HIGH_TABLES_SIZE * 1024;
223 /* TODO We could determine how many PCIe busses we need in
224 * the bar. For now that number is hardcoded to a max of 64.
225 * See e7525/northbridge.c for an example.
227 static struct device_operations pci_domain_ops = {
228 .read_resources = pci_domain_read_resources,
229 .set_resources = pci_domain_set_resources,
230 .enable_resources = enable_childrens_resources,
232 .scan_bus = pci_domain_scan_bus,
233 #if CONFIG_MMCONF_SUPPORT_DEFAULT
234 .ops_pci_bus = &pci_ops_mmconf,
236 .ops_pci_bus = &pci_cf8_conf1,
240 static void mc_read_resources(device_t dev)
242 struct resource *resource;
244 pci_dev_read_resources(dev);
246 /* So, this is one of the big mysteries in the coreboot resource
247 * allocator. This resource should make sure that the address space
248 * of the PCIe memory mapped config space bar. But it does not.
251 /* We use 0xcf as an unused index for our PCIe bar so that we find it again */
252 resource = new_resource(dev, 0xcf);
253 resource->base = DEFAULT_PCIEXBAR;
254 resource->size = 64 * 1024 * 1024; /* 64MB hard coded PCIe config space */
256 IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED |
258 printk_debug("Adding PCIe enhanced config space BAR 0x%08lx-0x%08lx.\n",
259 (unsigned long)(resource->base), (unsigned long)(resource->base + resource->size));
262 static void mc_set_resources(device_t dev)
264 struct resource *resource;
266 /* Report the PCIe BAR */
267 resource = find_resource(dev, 0xcf);
269 report_resource_stored(dev, resource, "<mmconfig>");
272 /* And call the normal set_resources */
273 pci_dev_set_resources(dev);
276 static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device)
278 if (!vendor || !device) {
279 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
280 pci_read_config32(dev, PCI_VENDOR_ID));
282 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
283 ((device & 0xffff) << 16) | (vendor & 0xffff));
287 static struct pci_operations intel_pci_ops = {
288 .set_subsystem = intel_set_subsystem,
291 static struct device_operations mc_ops = {
292 .read_resources = mc_read_resources,
293 .set_resources = mc_set_resources,
294 .enable_resources = pci_dev_enable_resources,
297 .ops_pci = &intel_pci_ops,
300 static const struct pci_driver mc_driver __pci_driver = {
302 .vendor = PCI_VENDOR_ID_INTEL,
306 static void cpu_bus_init(device_t dev)
308 initialize_cpus(&dev->link[0]);
311 static void cpu_bus_noop(device_t dev)
315 static struct device_operations cpu_bus_ops = {
316 .read_resources = cpu_bus_noop,
317 .set_resources = cpu_bus_noop,
318 .enable_resources = cpu_bus_noop,
319 .init = cpu_bus_init,
323 static void enable_dev(device_t dev)
325 /* Set the operations if it is a special bus type */
326 if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
327 dev->ops = &pci_domain_ops;
328 } else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
329 dev->ops = &cpu_bus_ops;
333 struct chip_operations northbridge_intel_i945_ops = {
334 CHIP_NAME("Intel i945 Northbridge")
335 .enable_dev = enable_dev,