2 * This file is part of the coreboot project.
4 * Copyright (C) 2007-2008 coresystems GmbH
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <console/console.h>
23 #include <device/device.h>
24 #include <device/pci.h>
25 #include <device/pci_ids.h>
26 #include <device/hypertransport.h>
34 static void ram_resource(device_t dev, unsigned long index, unsigned long basek,
37 struct resource *resource;
39 resource = new_resource(dev, index);
40 resource->base = ((resource_t) basek) << 10;
41 resource->size = ((resource_t) sizek) << 10;
42 resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE |
43 IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
46 static void pci_domain_read_resources(device_t dev)
48 struct resource *resource;
50 /* Initialize the system wide io space constraints */
51 resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
56 resource->limit = 0xffffUL;
58 IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
60 /* Initialize the system wide memory resources constraints */
61 resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
66 resource->limit = 0xffffffffUL;
68 IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
71 static void tolm_test(void *gp, struct device *dev, struct resource *new)
73 struct resource **best_p = gp;
74 struct resource *best;
76 if (!best || (best->base > new->base)) {
82 static uint32_t find_pci_tolm(struct bus *bus)
87 search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test,
90 if (min && tolm > min->base) {
96 #if HAVE_HIGH_TABLES==1
97 #define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB
98 extern uint64_t high_tables_base, high_tables_size;
100 uint64_t uma_memory_base=0, uma_memory_size=0;
102 static void pci_domain_set_resources(device_t dev)
107 unsigned long long tomk;
109 pci_tolm = find_pci_tolm(&dev->link[0]);
111 printk_spew("Base of stolen memory: 0x%08x\n",
112 pci_read_config32(dev_find_slot(0, PCI_DEVFN(2, 0)), 0x5c));
114 tolud = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), 0x9c);
115 printk_spew("Top of Low Used DRAM: 0x%08x\n", tolud << 24);
119 /* Note: subtract IGD device and TSEG */
120 reg8 = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), 0x9e);
123 printk_debug("TSEG decoded, subtracting ");
129 break; /* TSEG = 1M */
132 break; /* TSEG = 2M */
135 break; /* TSEG = 8M */
138 printk_debug("%dM\n", tseg_size >> 10);
142 reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)), GGC);
145 printk_debug("IGD decoded, subtracting ");
157 printk_debug("%dM UMA\n", uma_size >> 10);
160 /* For reserving UMA memory in the memory map */
161 uma_memory_base = tomk * 1024ULL;
162 uma_memory_size = uma_size * 1024ULL;
165 /* The following needs to be 2 lines, otherwise the second
168 printk_info("Available memory: %dK", (uint32_t)tomk);
169 printk_info(" (%dM)\n", (uint32_t)(tomk >> 10));
171 /* Report the memory regions */
172 ram_resource(dev, 3, 0, 640);
173 ram_resource(dev, 4, 768, (tomk - 768));
174 if (tomk > 4 * 1024 * 1024) {
175 ram_resource(dev, 5, 4096 * 1024, tomk - 4 * 1024 * 1024);
178 assign_resources(&dev->link[0]);
180 #if HAVE_HIGH_TABLES==1
181 /* Leave some space for ACPI, PIRQ and MP tables */
182 high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024;
183 high_tables_size = HIGH_TABLES_SIZE * 1024;
187 static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
189 max = pci_scan_bus(&dev->link[0], 0, 0xff, max);
190 /* TODO We could determine how many PCIe busses we need in
191 * the bar. For now that number is hardcoded to a max of 64.
196 static struct device_operations pci_domain_ops = {
197 .read_resources = pci_domain_read_resources,
198 .set_resources = pci_domain_set_resources,
199 .enable_resources = enable_childrens_resources,
201 .scan_bus = pci_domain_scan_bus,
202 .ops_pci_bus = &pci_cf8_conf1, /* Do we want to use the memory mapped space here? */
205 static void mc_read_resources(device_t dev)
207 struct resource *resource;
209 pci_dev_read_resources(dev);
211 /* So, this is one of the big mysteries in the coreboot resource
212 * allocator. This resource should make sure that the address space
213 * of the PCIe memory mapped config space bar. But it does not.
216 /* We use 0xcf as an unused index for our PCIe bar so that we find it again */
217 resource = new_resource(dev, 0xcf);
218 resource->base = DEFAULT_PCIEXBAR;
219 resource->size = 64 * 1024 * 1024; /* 64MB hard coded PCIe config space */
221 IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED |
223 printk_debug("Adding PCIe enhanced config space BAR 0x%08x-0x%08x.\n",
224 resource->base, (resource->base + resource->size));
227 static void mc_set_resources(device_t dev)
229 struct resource *resource, *last;
231 /* Report the PCIe BAR */
232 last = &dev->resource[dev->resources];
233 resource = find_resource(dev, 0xcf);
235 report_resource_stored(dev, resource, "<mmconfig>");
238 /* And call the normal set_resources */
239 pci_dev_set_resources(dev);
242 static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device)
244 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
245 ((device & 0xffff) << 16) | (vendor & 0xffff));
248 static struct pci_operations intel_pci_ops = {
249 .set_subsystem = intel_set_subsystem,
252 static struct device_operations mc_ops = {
253 .read_resources = mc_read_resources,
254 .set_resources = mc_set_resources,
255 .enable_resources = pci_dev_enable_resources,
258 .ops_pci = &intel_pci_ops,
261 static const struct pci_driver mc_driver __pci_driver = {
263 .vendor = PCI_VENDOR_ID_INTEL,
267 static void cpu_bus_init(device_t dev)
269 initialize_cpus(&dev->link[0]);
272 static void cpu_bus_noop(device_t dev)
276 static struct device_operations cpu_bus_ops = {
277 .read_resources = cpu_bus_noop,
278 .set_resources = cpu_bus_noop,
279 .enable_resources = cpu_bus_noop,
280 .init = cpu_bus_init,
284 static void enable_dev(device_t dev)
286 /* Set the operations if it is a special bus type */
287 if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
288 dev->ops = &pci_domain_ops;
289 } else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
290 dev->ops = &cpu_bus_ops;
294 struct chip_operations northbridge_intel_i945_ops = {
295 CHIP_NAME("Intel i945 Northbridge")
296 .enable_dev = enable_dev,