2 * This file is part of the coreboot project.
4 * Copyright (C) 2007-2008 coresystems GmbH
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <console/console.h>
23 #include <device/device.h>
24 #include <device/pci.h>
25 #include <device/pci_ids.h>
26 #include <device/hypertransport.h>
34 static void ram_resource(device_t dev, unsigned long index, unsigned long basek,
37 struct resource *resource;
39 resource = new_resource(dev, index);
40 resource->base = ((resource_t) basek) << 10;
41 resource->size = ((resource_t) sizek) << 10;
42 resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE |
43 IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
46 static void pci_domain_read_resources(device_t dev)
48 struct resource *resource;
50 /* Initialize the system wide io space constraints */
51 resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
56 resource->limit = 0xffffUL;
58 IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
60 /* Initialize the system wide memory resources constraints */
61 resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
66 resource->limit = 0xffffffffUL;
68 IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
71 static void tolm_test(void *gp, struct device *dev, struct resource *new)
73 struct resource **best_p = gp;
74 struct resource *best;
76 if (!best || (best->base > new->base)) {
82 static uint32_t find_pci_tolm(struct bus *bus)
87 search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test,
90 if (min && tolm > min->base) {
96 static void pci_domain_set_resources(device_t dev)
101 unsigned long long tomk, tolmk;
103 pci_tolm = find_pci_tolm(&dev->link[0]);
105 printk_spew("Base of stolen memory: 0x%08x\n",
106 pci_read_config32(dev_find_slot(0, PCI_DEVFN(2, 0)), 0x5c));
108 tolud = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), 0x9c);
109 printk_spew("Top of Low Used DRAM: 0x%08x\n", tolud << 24);
113 /* Note: subtract IGD device and TSEG */
114 reg8 = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), 0x9e);
117 printk_debug("TSEG decoded, subtracting ");
132 printk_debug("%dM\n", tseg_size >> 10);
136 reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)), GGC);
139 printk_debug("IGD decoded, subtracting ");
151 printk_debug("%dM UMA\n", uma_size >> 10);
155 /* The following needs to be 2 lines, otherwise the second
158 printk_info("Available memory: %dK", tomk);
159 printk_info(" (%dM)\n", (tomk >> 10));
163 /* Report the memory regions */
164 ram_resource(dev, 3, 0, 640);
165 ram_resource(dev, 4, 768, (tolmk - 768));
166 if (tomk > 4 * 1024 * 1024) {
167 ram_resource(dev, 5, 4096 * 1024, tomk - 4 * 1024 * 1024);
170 assign_resources(&dev->link[0]);
173 static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
175 max = pci_scan_bus(&dev->link[0], 0, 0xff, max);
176 /* TODO We could determine how many PCIe busses we need in
177 * the bar. For now that number is hardcoded to a max of 64.
182 static struct device_operations pci_domain_ops = {
183 .read_resources = pci_domain_read_resources,
184 .set_resources = pci_domain_set_resources,
185 .enable_resources = enable_childrens_resources,
187 .scan_bus = pci_domain_scan_bus,
188 .ops_pci_bus = &pci_cf8_conf1, /* Do we want to use the memory mapped space here? */
191 static void mc_read_resources(device_t dev)
193 struct resource *resource;
195 pci_dev_read_resources(dev);
197 /* So, this is one of the big mysteries in the coreboot resource
198 * allocator. This resource should make sure that the address space
199 * of the PCIe memory mapped config space bar. But it does not.
202 /* We use 0xcf as an unused index for our PCIe bar so that we find it again */
203 resource = new_resource(dev, 0xcf);
204 resource->base = DEFAULT_PCIEXBAR;
205 resource->size = 64 * 1024 * 1024; /* 64MB hard coded PCIe config space */
207 IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED |
209 printk_debug("Adding PCIe enhanced config space BAR 0x%08x-0x%08x.\n",
210 resource->base, (resource->base + resource->size));
213 static void mc_set_resources(device_t dev)
215 struct resource *resource, *last;
217 /* Report the PCIe BAR */
218 last = &dev->resource[dev->resources];
219 resource = find_resource(dev, 0xcf);
221 report_resource_stored(dev, resource, "<mmconfig>");
224 /* And call the normal set_resources */
225 pci_dev_set_resources(dev);
228 static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device)
230 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
231 ((device & 0xffff) << 16) | (vendor & 0xffff));
234 static struct pci_operations intel_pci_ops = {
235 .set_subsystem = intel_set_subsystem,
238 static struct device_operations mc_ops = {
239 .read_resources = mc_read_resources,
240 .set_resources = mc_set_resources,
241 .enable_resources = pci_dev_enable_resources,
244 .ops_pci = &intel_pci_ops,
247 static const struct pci_driver mc_driver __pci_driver = {
249 .vendor = PCI_VENDOR_ID_INTEL,
250 .device = PCI_DEVICE_ID_INTEL_945_HOST_BRIDGE,
253 static void cpu_bus_init(device_t dev)
255 initialize_cpus(&dev->link[0]);
258 static void cpu_bus_noop(device_t dev)
262 static struct device_operations cpu_bus_ops = {
263 .read_resources = cpu_bus_noop,
264 .set_resources = cpu_bus_noop,
265 .enable_resources = cpu_bus_noop,
266 .init = cpu_bus_init,
270 static void enable_dev(device_t dev)
272 /* Set the operations if it is a special bus type */
273 if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
274 dev->ops = &pci_domain_ops;
275 } else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
276 dev->ops = &cpu_bus_ops;
280 struct chip_operations northbridge_intel_i945_ops = {
281 CHIP_NAME("Intel i945 Northbridge")
282 .enable_dev = enable_dev,