2 * This file is part of the coreboot project.
4 * Copyright (C) 2007-2009 coresystems GmbH
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <console/console.h>
23 #include <device/device.h>
24 #include <device/pci.h>
25 #include <device/pci_ids.h>
26 #include <device/hypertransport.h>
31 #include <boot/tables.h>
32 #include <arch/acpi.h>
36 static int get_pcie_bar(u32 *base, u32 *len)
44 dev = dev_find_slot(0, PCI_DEVFN(0, 0));
48 pciexbar_reg = pci_read_config32(dev, PCIEXBAR);
50 if (!(pciexbar_reg & (1 << 0)))
53 switch ((pciexbar_reg >> 1) & 3) {
55 *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28));
56 *len = 256 * 1024 * 1024;
59 *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));
60 *len = 128 * 1024 * 1024;
63 *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26));
64 *len = 64 * 1024 * 1024;
72 uint64_t uma_memory_base=0, uma_memory_size=0;
74 static void add_fixed_resources(struct device *dev, int index)
76 struct resource *resource;
77 u32 pcie_config_base, pcie_config_size;
79 printk(BIOS_DEBUG, "Adding UMA memory area\n");
80 resource = new_resource(dev, index);
81 resource->base = (resource_t) uma_memory_base;
82 resource->size = (resource_t) uma_memory_size;
83 resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
84 IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
86 if (get_pcie_bar(&pcie_config_base, &pcie_config_size)) {
87 printk(BIOS_DEBUG, "Adding PCIe config bar\n");
88 resource = new_resource(dev, index+1);
89 resource->base = (resource_t) pcie_config_base;
90 resource->size = (resource_t) pcie_config_size;
91 resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
92 IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
96 #if CONFIG_WRITE_HIGH_TABLES==1
100 static void pci_domain_set_resources(device_t dev)
105 unsigned long long tomk;
107 /* Can we find out how much memory we can use at most
110 pci_tolm = find_pci_tolm(dev->link_list);
111 printk(BIOS_DEBUG, "pci_tolm: 0x%x\n", pci_tolm);
113 printk(BIOS_SPEW, "Base of stolen memory: 0x%08x\n",
114 pci_read_config32(dev_find_slot(0, PCI_DEVFN(2, 0)), 0x5c));
116 tolud = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), 0x9c);
117 printk(BIOS_SPEW, "Top of Low Used DRAM: 0x%08x\n", tolud << 24);
121 /* Note: subtract IGD device and TSEG */
122 reg8 = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), 0x9e);
125 printk(BIOS_DEBUG, "TSEG decoded, subtracting ");
131 break; /* TSEG = 1M */
134 break; /* TSEG = 2M */
137 break; /* TSEG = 8M */
140 printk(BIOS_DEBUG, "%dM\n", tseg_size >> 10);
144 reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)), GGC);
147 printk(BIOS_DEBUG, "IGD decoded, subtracting ");
159 printk(BIOS_DEBUG, "%dM UMA\n", uma_size >> 10);
162 /* For reserving UMA memory in the memory map */
163 uma_memory_base = tomk * 1024ULL;
164 uma_memory_size = uma_size * 1024ULL;
167 /* The following needs to be 2 lines, otherwise the second
170 printk(BIOS_INFO, "Available memory: %dK", (uint32_t)tomk);
171 printk(BIOS_INFO, " (%dM)\n", (uint32_t)(tomk >> 10));
173 /* Report the memory regions */
174 ram_resource(dev, 3, 0, 640);
175 ram_resource(dev, 4, 768, (tomk - 768));
176 if (tomk > 4 * 1024 * 1024) {
177 ram_resource(dev, 5, 4096 * 1024, tomk - 4 * 1024 * 1024);
180 add_fixed_resources(dev, 6);
182 assign_resources(dev->link_list);
184 #if CONFIG_WRITE_HIGH_TABLES==1
185 /* Leave some space for ACPI, PIRQ and MP tables */
186 high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE;
187 high_tables_size = HIGH_MEMORY_SIZE;
191 /* TODO We could determine how many PCIe busses we need in
192 * the bar. For now that number is hardcoded to a max of 64.
193 * See e7525/northbridge.c for an example.
195 static struct device_operations pci_domain_ops = {
196 .read_resources = pci_domain_read_resources,
197 .set_resources = pci_domain_set_resources,
198 .enable_resources = NULL,
200 .scan_bus = pci_domain_scan_bus,
201 #if CONFIG_MMCONF_SUPPORT_DEFAULT
202 .ops_pci_bus = &pci_ops_mmconf,
204 .ops_pci_bus = &pci_cf8_conf1,
208 static void mc_read_resources(device_t dev)
210 struct resource *resource;
212 pci_dev_read_resources(dev);
214 /* So, this is one of the big mysteries in the coreboot resource
215 * allocator. This resource should make sure that the address space
216 * of the PCIe memory mapped config space bar. But it does not.
219 /* We use 0xcf as an unused index for our PCIe bar so that we find it again */
220 resource = new_resource(dev, 0xcf);
221 resource->base = DEFAULT_PCIEXBAR;
222 resource->size = 64 * 1024 * 1024; /* 64MB hard coded PCIe config space */
224 IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED |
226 printk(BIOS_DEBUG, "Adding PCIe enhanced config space BAR 0x%08lx-0x%08lx.\n",
227 (unsigned long)(resource->base), (unsigned long)(resource->base + resource->size));
230 static void mc_set_resources(device_t dev)
232 struct resource *resource;
234 /* Report the PCIe BAR */
235 resource = find_resource(dev, 0xcf);
237 report_resource_stored(dev, resource, "<mmconfig>");
240 /* And call the normal set_resources */
241 pci_dev_set_resources(dev);
244 static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device)
246 if (!vendor || !device) {
247 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
248 pci_read_config32(dev, PCI_VENDOR_ID));
250 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
251 ((device & 0xffff) << 16) | (vendor & 0xffff));
255 #if CONFIG_HAVE_ACPI_RESUME
256 static void northbridge_init(struct device *dev)
258 switch (pci_read_config32(dev, SKPAD)) {
259 case SKPAD_NORMAL_BOOT_MAGIC:
260 printk(BIOS_DEBUG, "Normal boot.\n");
263 case SKPAD_ACPI_S3_MAGIC:
264 printk(BIOS_DEBUG, "S3 Resume.\n");
268 printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n");
275 static struct pci_operations intel_pci_ops = {
276 .set_subsystem = intel_set_subsystem,
279 static struct device_operations mc_ops = {
280 .read_resources = mc_read_resources,
281 .set_resources = mc_set_resources,
282 .enable_resources = pci_dev_enable_resources,
283 #if CONFIG_HAVE_ACPI_RESUME
284 .init = northbridge_init,
287 .ops_pci = &intel_pci_ops,
290 static const struct pci_driver mc_driver __pci_driver = {
292 .vendor = PCI_VENDOR_ID_INTEL,
296 static void cpu_bus_init(device_t dev)
298 initialize_cpus(dev->link_list);
301 static void cpu_bus_noop(device_t dev)
305 static struct device_operations cpu_bus_ops = {
306 .read_resources = cpu_bus_noop,
307 .set_resources = cpu_bus_noop,
308 .enable_resources = cpu_bus_noop,
309 .init = cpu_bus_init,
313 static void enable_dev(device_t dev)
315 /* Set the operations if it is a special bus type */
316 if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
317 dev->ops = &pci_domain_ops;
318 } else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
319 dev->ops = &cpu_bus_ops;
323 struct chip_operations northbridge_intel_i945_ops = {
324 CHIP_NAME("Intel i945 Northbridge")
325 .enable_dev = enable_dev,