src/northbridge/intel/i945/acpi/i945_hostbridge.asl

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007-2009 coresystems GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; version 2 of
   9  * the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
  19  * MA 02110-1301 USA
  20  */
  21
  22
  23 Name(_HID,EISAID("PNP0A08"))    // PCIe
  24 Name(_CID,EISAID("PNP0A03"))    // PCI
  25
  26 Device (MCHC)
  27 {
  28         Name(_ADR, 0x00000000)  // 0:0.0
  29
  30         OperationRegion(MCHP, PCI_Config, 0x00, 0x100)
  31         Field (MCHP, DWordAcc, NoLock, Preserve)
  32         {
  33                 Offset (0x40),  // EPBAR
  34                 EPEN,    1,     // Enable
  35                 ,       11,     //
  36                 EPBR,   20,     // EPBAR
  37
  38                 Offset (0x44),  // MCHBAR
  39                 MHEN,    1,     // Enable
  40                 ,       13,     //
  41                 MHBR,   18,     // MCHBAR
  42
  43                 Offset (0x48),  // PCIe BAR
  44                 PXEN,    1,     // Enable
  45                 PXSZ,    2,     // BAR size
  46                 ,       23,     //
  47                 PXBR,    6,     // PCIe BAR
  48
  49                 Offset (0x4c),  // DMIBAR
  50                 DMEN,    1,     // Enable
  51                 ,       11,     //
  52                 DMBR,   20,     // DMIBAR
  53
  54                 // ...
  55
  56                 Offset (0x90),  // PAM0
  57                 ,        4,
  58                 PM0H,    2,
  59                 ,        2,
  60                 Offset (0x91),  // PAM1
  61                 PM1L,    2,
  62                 ,        2,
  63                 PM1H,    2,
  64                 ,        2,
  65                 Offset (0x92),  // PAM2
  66                 PM2L,    2,
  67                 ,        2,
  68                 PM2H,    2,
  69                 ,        2,
  70                 Offset (0x93),  // PAM3
  71                 PM3L,    2,
  72                 ,        2,
  73                 PM3H,    2,
  74                 ,        2,
  75                 Offset (0x94),  // PAM4
  76                 PM4L,    2,
  77                 ,        2,
  78                 PM4H,    2,
  79                 ,        2,
  80                 Offset (0x95),  // PAM5
  81                 PM5L,    2,
  82                 ,        2,
  83                 PM5H,    2,
  84                 ,        2,
  85                 Offset (0x96),  // PAM6
  86                 PM6L,    2,
  87                 ,        2,
  88                 PM6H,    2,
  89                 ,        2,
  90
  91                 Offset (0x9c),  // Top of Low Used Memory
  92                 ,        3,
  93                 TLUD,    5,
  94
  95                 Offset (0xa0),  // Top of Used Memory
  96                 TOM,    16,
  97         }
  98
  99 }
 100
 101
 102 // Current Resource Settings
 103
 104 Method (_CRS, 0, Serialized)
 105 {
 106         Name (MCRS, ResourceTemplate()
 107         {
 108                 // Bus Numbers
 109                 WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
 110                                 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,, PB00)
 111
 112                 // IO Region 0
 113                 DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
 114                                 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00)
 115
 116                 // PCI Config Space
 117                 Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008)
 118
 119                 // IO Region 1
 120                 DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
 121                                 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300,,, PI01)
 122
 123                 // VGA memory (0xa0000-0xbffff)
 124                 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 125                                 Cacheable, ReadWrite,
 126                                 0x00000000, 0x000a0000, 0x000bffff, 0x00000000,
 127                                 0x00020000,,, ASEG)
 128
 129                 // OPROM reserved (0xc0000-0xc3fff)
 130                 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 131                                 Cacheable, ReadWrite,
 132                                 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000,
 133                                 0x00004000,,, OPR0)
 134
 135                 // OPROM reserved (0xc4000-0xc7fff)
 136                 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 137                                 Cacheable, ReadWrite,
 138                                 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000,
 139                                 0x00004000,,, OPR1)
 140
 141                 // OPROM reserved (0xc8000-0xcbfff)
 142                 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 143                                 Cacheable, ReadWrite,
 144                                 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000,
 145                                 0x00004000,,, OPR2)
 146
 147                 // OPROM reserved (0xcc000-0xcffff)
 148                 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 149                                 Cacheable, ReadWrite,
 150                                 0x00000000, 0x000cc000, 0x000cffff, 0x00000000,
 151                                 0x00004000,,, OPR3)
 152
 153                 // OPROM reserved (0xd0000-0xd3fff)
 154                 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 155                                 Cacheable, ReadWrite,
 156                                 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000,
 157                                 0x00004000,,, OPR4)
 158
 159                 // OPROM reserved (0xd4000-0xd7fff)
 160                 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 161                                 Cacheable, ReadWrite,
 162                                 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000,
 163                                 0x00004000,,, OPR5)
 164
 165                 // OPROM reserved (0xd8000-0xdbfff)
 166                 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 167                                 Cacheable, ReadWrite,
 168                                 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000,
 169                                 0x00004000,,, OPR6)
 170
 171                 // OPROM reserved (0xdc000-0xdffff)
 172                 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 173                                 Cacheable, ReadWrite,
 174                                 0x00000000, 0x000dc000, 0x000dffff, 0x00000000,
 175                                 0x00004000,,, OPR7)
 176
 177                 // BIOS Extension (0xe0000-0xe3fff)
 178                 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 179                                 Cacheable, ReadWrite,
 180                                 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000,
 181                                 0x00004000,,, ESG0)
 182
 183                 // BIOS Extension (0xe4000-0xe7fff)
 184                 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 185                                 Cacheable, ReadWrite,
 186                                 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000,
 187                                 0x00004000,,, ESG1)
 188
 189                 // BIOS Extension (0xe8000-0xebfff)
 190                 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 191                                 Cacheable, ReadWrite,
 192                                 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000,
 193                                 0x00004000,,, ESG2)
 194
 195                 // BIOS Extension (0xec000-0xeffff)
 196                 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 197                                 Cacheable, ReadWrite,
 198                                 0x00000000, 0x000ec000, 0x000effff, 0x00000000,
 199                                 0x00004000,,, ESG3)
 200
 201                 // System BIOS (0xf0000-0xfffff)
 202                 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 203                                 Cacheable, ReadWrite,
 204                                 0x00000000, 0x000f0000, 0x000fffff, 0x00000000,
 205                                 0x00010000,,, FSEG)
 206
 207                  // PCI Memory Region (Top of memory-0xfebfffff)
 208                  DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 209                                  Cacheable, ReadWrite,
 210                                  0x00000000, 0x00000000, 0xfebfffff, 0x00000000,
 211                                  0x00000000,,, PM01)
 212
 213                  // TPM Area (0xfed40000-0xfed44fff)
 214                  DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 215                                  Cacheable, ReadWrite,
 216                                  0x00000000, 0xfed40000, 0xfed44fff, 0x00000000,
 217                                  0x00000000,,, TPMR)
 218         })
 219
 220         // Find PCI resource area in MCRS
 221         CreateDwordField(MCRS, PM01._MIN, PMIN)
 222         CreateDwordField(MCRS, PM01._MAX, PMAX)
 223         CreateDwordField(MCRS, PM01._LEN, PLEN)
 224
 225         // Fix up PCI memory region:
 226         // Enter actual TOLUD. The TOLUD register contains bits 27-31 of
 227         // the top of memory address.
 228         ShiftLeft (^MCHC.TLUD, 27, PMIN)
 229         Add(Subtract(PMAX, PMIN), 1, PLEN)
 230
 231         Return (MCRS)
 232 }
 233
 234 /* IRQ assignment is mainboard specific. Get it from mainboard ACPI code */
 235 Include ("acpi/i945_pci_irqs.asl")
 236
 237