src/northbridge/intel/i945/acpi/i945_hostbridge.asl

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007-2009 coresystems GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; version 2 of
   9  * the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
  19  * MA 02110-1301 USA
  20  */
  21
  22
  23 Name(_HID,EISAID("PNP0A08"))    // PCIe
  24 Name(_CID,EISAID("PNP0A03"))    // PCI
  25
  26 Device (MCHC)
  27 {
  28         Name(_ADR, 0x00000000)  // 0:0.0
  29
  30         OperationRegion(MCHP, PCI_Config, 0x00, 0x100)
  31         Field (MCHP, DWordAcc, NoLock, Preserve)
  32         {
  33                 Offset (0x40),  // EPBAR
  34                 EPEN,    1,     // Enable
  35                 ,       11,     //
  36                 EPBR,   20,     // EPBAR
  37
  38                 Offset (0x48),  // MCHBAR
  39                 MHEN,    1,     // Enable
  40                 ,       13,     //
  41                 MHBR,   18,     // MCHBAR
  42
  43                 Offset (0x60),  // PCIe BAR
  44                 PXEN,    1,     // Enable
  45                 PXSZ,    2,     // BAR size
  46                 ,       23,     //
  47                 PXBR,    6,     // PCIe BAR
  48
  49                 Offset (0x68),  // DMIBAR
  50                 DMEN,    1,     // Enable
  51                 ,       11,     //
  52                 DMBR,   20,     // DMIBAR
  53
  54                 // ...
  55
  56                 Offset (0x90),  // PAM0
  57                 ,        4,
  58                 PM0H,    2,
  59                 ,        2,
  60                 Offset (0x91),  // PAM1
  61                 PM1L,    2,
  62                 ,        2,
  63                 PM1H,    2,
  64                 ,        2,
  65                 Offset (0x92),  // PAM2
  66                 PM2L,    2,
  67                 ,        2,
  68                 PM2H,    2,
  69                 ,        2,
  70                 Offset (0x93),  // PAM3
  71                 PM3L,    2,
  72                 ,        2,
  73                 PM3H,    2,
  74                 ,        2,
  75                 Offset (0x94),  // PAM4
  76                 PM4L,    2,
  77                 ,        2,
  78                 PM4H,    2,
  79                 ,        2,
  80                 Offset (0x95),  // PAM5
  81                 PM5L,    2,
  82                 ,        2,
  83                 PM5H,    2,
  84                 ,        2,
  85                 Offset (0x96),  // PAM6
  86                 PM6L,    2,
  87                 ,        2,
  88                 PM6H,    2,
  89                 ,        2,
  90                 Offset (0xa2),  // Top of upper used dram
  91                 TUUD,   16,
  92                 Offset (0xb0),
  93                 ,        4,
  94                 TLUD,   12      // TOLUD
  95         }
  96
  97 }
  98
  99
 100 // Current Resource Settings
 101
 102 Method (_CRS, 0, Serialized)
 103 {
 104         Name (MCRS, ResourceTemplate()
 105         {
 106                 // Bus Numbers
 107                 WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
 108                                 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,, PB00)
 109
 110                 // IO Region 0
 111                 DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
 112                                 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00)
 113
 114                 // PCI Config Space
 115                 Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008)
 116
 117                 // IO Region 1
 118                 DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
 119                                 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300,,, PI01)
 120
 121                 // VGA memory (0xa0000-0xbffff)
 122                 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 123                                 Cacheable, ReadWrite,
 124                                 0x00000000, 0x000a0000, 0x000bffff, 0x00000000,
 125                                 0x00020000,,, ASEG)
 126
 127                 // OPROM reserved (0xc0000-0xc3fff)
 128                 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 129                                 Cacheable, ReadWrite,
 130                                 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000,
 131                                 0x00004000,,, OPR0)
 132
 133                 // OPROM reserved (0xc4000-0xc7fff)
 134                 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 135                                 Cacheable, ReadWrite,
 136                                 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000,
 137                                 0x00004000,,, OPR1)
 138
 139                 // OPROM reserved (0xc8000-0xcbfff)
 140                 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 141                                 Cacheable, ReadWrite,
 142                                 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000,
 143                                 0x00004000,,, OPR2)
 144
 145                 // OPROM reserved (0xcc000-0xcffff)
 146                 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 147                                 Cacheable, ReadWrite,
 148                                 0x00000000, 0x000cc000, 0x000cffff, 0x00000000,
 149                                 0x00004000,,, OPR3)
 150
 151                 // OPROM reserved (0xd0000-0xd3fff)
 152                 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 153                                 Cacheable, ReadWrite,
 154                                 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000,
 155                                 0x00004000,,, OPR4)
 156
 157                 // OPROM reserved (0xd4000-0xd7fff)
 158                 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 159                                 Cacheable, ReadWrite,
 160                                 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000,
 161                                 0x00004000,,, OPR5)
 162
 163                 // OPROM reserved (0xd8000-0xdbfff)
 164                 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 165                                 Cacheable, ReadWrite,
 166                                 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000,
 167                                 0x00004000,,, OPR6)
 168
 169                 // OPROM reserved (0xdc000-0xdffff)
 170                 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 171                                 Cacheable, ReadWrite,
 172                                 0x00000000, 0x000dc000, 0x000dffff, 0x00000000,
 173                                 0x00004000,,, OPR7)
 174
 175                 // Bios Extension (0xe0000-0xeffff)
 176                 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 177                                 Cacheable, ReadWrite,
 178                                 0x00000000, 0x000e0000, 0x000effff, 0x00000000,
 179                                 0x00010000,,, ESEG)
 180
 181                 // System BIOS (0xf0000-0xfffff)
 182                 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 183                                 Cacheable, ReadWrite,
 184                                 0x00000000, 0x000f0000, 0x000fffff, 0x00000000,
 185                                 0x00010000,,, FSEG)
 186
 187                  // PCI Memory Region (Top of memory-0xfebfffff)
 188                  DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 189                                  Cacheable, ReadWrite,
 190                                  0x00000000, 0x00000000, 0xfebfffff, 0x00000000,
 191                                  0x00000000,,, PM01)
 192         })
 193
 194         // Find PCI resource area in MCRS
 195         CreateDwordField(MCRS, PM01._MIN, PMIN)
 196         CreateDwordField(MCRS, PM01._MAX, PMAX)
 197         CreateDwordField(MCRS, PM01._LEN, PLEN)
 198
 199         // Fix up PCI memory region:
 200         // Enter actual TOLUD. The TOLUD register contains bits 20-31 of
 201         // the top of memory address.
 202         ShiftLeft (^MCHC.TLUD, 20, PMIN)
 203         Add(Subtract(PMAX, PMIN), 1, PLEN)
 204
 205         Return (MCRS)
 206 }
 207
 208 // PCI Interrupt Routing
 209 Method(_PRT)
 210 {
 211         If (PICM) {
 212                 Return (Package() {
 213                         // PCIe Graphics                0:1.0
 214                         Package() { 0x0001ffff, 0, 0, 16 },
 215                         // Onboard graphics (IGD)       0:2.0
 216                         Package() { 0x0002ffff, 0, 0, 16 },
 217                         // High Definition Audio        0:1b.0
 218                         Package() { 0x001bffff, 0, 0, 16 },
 219                         // PCIe Root Ports              0:1c.x
 220                         Package() { 0x001cffff, 0, 0, 16 },
 221                         Package() { 0x001cffff, 1, 0, 17 },
 222                         Package() { 0x001cffff, 2, 0, 18 },
 223                         Package() { 0x001cffff, 3, 0, 19 },
 224                         // USB and EHCI                 0:1d.x
 225                         Package() { 0x001dffff, 0, 0, 23 },
 226                         Package() { 0x001dffff, 1, 0, 19 },
 227                         Package() { 0x001dffff, 2, 0, 18 },
 228                         Package() { 0x001dffff, 3, 0, 16 },
 229                         // LPC device                   0:1f.0
 230                         Package() { 0x001fffff, 0, 0, 19 },
 231                         Package() { 0x001fffff, 1, 0, 19},
 232                         Package() { 0x001fffff, 2, 0, 19 },
 233                         Package() { 0x001fffff, 3, 0, 16 }
 234                 })
 235         } Else {
 236                 Return (Package() {
 237                         // PCIe Graphics                0:1.0
 238                         Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
 239                         // Onboard graphics (IGD)       0:2.0
 240                         Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
 241                         // High Definition Audio        0:1b.0
 242                         Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
 243                         // PCIe Root Ports              0:1c.x
 244                         Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
 245                         Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKA, 0 },
 246                         Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
 247                         Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
 248                         // USB and EHCI                 0:1d.x
 249                         Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKH, 0 },
 250                         Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },
 251                         Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
 252                         // LPC device                   0:1f.0
 253                         Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
 254                         Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },
 255                         Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKD, 0 },
 256                         Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }
 257                 })
 258         }
 259
 260 }