1 /* This was originally for the e7500, modified for i855pm
5 * memory type (must be ddr)
6 * number of row addresses, not counting bank addresses
7 * number of column addresses
8 * number of so-dimm banks
11 * number banks on each device
13 * that's it. No other bytes are used.
15 * 2, 3, 4, 5, 11, 12 17
18 /* converted to C 6/2004 yhlu */
20 #define DEBUG_RAM_CONFIG 2
21 #undef ASM_CONSOLE_LOGLEVEL
22 #define ASM_CONSOLE_LOGLEVEL 8
23 #define dumpnorth() dump_pci_device(PCI_DEV(0, 0, 1))
25 /* DDR DIMM Mode register Definitions */
27 #define BURST_2 (1<<0)
28 #define BURST_4 (2<<0)
29 #define BURST_8 (3<<0)
31 #define BURST_SEQUENTIAL (0<<3)
32 #define BURST_INTERLEAVED (1<<3)
34 #define CAS_2_0 (0x2<<4)
35 #define CAS_3_0 (0x3<<4)
36 #define CAS_1_5 (0x5<<4)
37 #define CAS_2_5 (0x6<<4)
39 #define MODE_NORM (0 << 7)
40 #define MODE_DLL_RESET (2 << 7)
41 #define MODE_TEST (1 << 7)
43 #define BURST_LENGTH BURST_4
44 #define BURST_TYPE BURST_INTERLEAVED
45 #define CAS_LATENCY CAS_2_0
46 /*#define CAS_LATENCY CAS_2_5*/
47 /*#define CAS_LATENCY CAS_1_5*/
49 /* WOW! this could be bad! sets casl to 2 without checking! */
50 #define MRS_VALUE (MODE_NORM | CAS_LATENCY | BURST_TYPE | BURST_LENGTH)
51 #define EMRS_VALUE 0x000
55 #define RAM_COMMAND_NONE 0x0
56 #define RAM_COMMAND_NOP 0x1
57 #define RAM_COMMAND_PRECHARGE 0x2
58 #define RAM_COMMAND_MRS 0x3
59 #define RAM_COMMAND_EMRS 0x4
60 #define RAM_COMMAND_CBR 0x6
61 #define RAM_COMMAND_NORMAL 0x7
64 static inline void do_ram_command (const struct mem_controller *ctrl, uint32_t value) {
69 #if DEBUG_RAM_CONFIG >=2
71 print_debug_hex8(value);
74 /* %ecx - initial address to read from */
75 /* Compute the offset */
77 /* for(i=0;i<4;i++) {*/
79 /* Set the ram command */
80 byte = pci_read_config8(ctrl->d0, 0x70);
82 byte |= (uint8_t)(value & 0xff);
85 print_debug_hex8(byte);
89 pci_write_config8(ctrl->d0, 0x70, byte);
91 /* Assert the command to the memory */
92 #if DEBUG_RAM_CONFIG >= 2
94 print_debug_hex32(dword);
98 result = read32(dword);
101 print_debug("Done\r\n");
103 /* Go to the next base address */
108 /* The command has been sent to all dimms so get out */
111 static inline void RAM_CMD(const struct mem_controller *ctrl, uint32_t command, uint32_t offset) {
112 uint32_t value = ((offset) << (MD_SHIFT + 16))|((command << 4) & 0x70) ;
113 do_ram_command(ctrl, value);
116 #define RAM_NOP(ctrl) RAM_CMD(ctrl, RAM_COMMAND_NOP, 0)
117 #define RAM_PRECHARGE(ctrl) RAM_CMD(ctrl, RAM_COMMAND_PRECHARGE, 0)
118 #define RAM_CBR(ctrl) RAM_CMD(ctrl, RAM_COMMAND_CBR, 0)
119 #define RAM_EMRS(ctrl) RAM_CMD(ctrl, RAM_COMMAND_EMRS, EMRS_VALUE)
121 static const uint8_t ram_cas_latency[] = {
122 CAS_2_5, CAS_2_0, CAS_1_5, CAS_2_5
125 static inline void ram_mrs(const struct mem_controller *ctrl, uint32_t value){
126 /* Read the cas latency setting */
129 byte = pci_read_config8(ctrl->d0, 0x60);
130 /* Transform it into the form expected by SDRAM */
131 dword = ram_cas_latency[(byte>>5) & 1];
132 #warning RAM_MRS -- using BROKEN hard-wired CAS 2.0. FIX ME SOON
135 value |= (dword<<(16+MD_SHIFT));
137 value |= (MODE_NORM | BURST_TYPE | BURST_LENGTH) << (16+MD_SHIFT);
139 do_ram_command(ctrl, value);
142 #define RAM_MRS(ctrl, dll_reset) ram_mrs( ctrl, (dll_reset << (8+MD_SHIFT+ 16)) | ((RAM_COMMAND_MRS <<4)& 0x70) )
144 static void RAM_NORMAL(const struct mem_controller *ctrl) {
146 byte = pci_read_config8(ctrl->d0, 0x70);
148 byte |= (RAM_COMMAND_NORMAL << 4);
149 pci_write_config8(ctrl->d0, 0x70, byte);
152 static void RAM_RESET_DDR_PTR(const struct mem_controller *ctrl) {
154 byte = pci_read_config8(ctrl->d0, 0x88);
156 pci_write_config8(ctrl->d0, 0x88, byte);
157 byte = pci_read_config8(ctrl->d0, 0x88);
159 pci_write_config8(ctrl->d0, 0x88, byte);
162 static void ENABLE_REFRESH(const struct mem_controller *ctrl)
165 dword = pci_read_config32(ctrl->d0, 0x70);
167 pci_write_config32(ctrl->d0, 0x70, dword);
171 * Table: constant_register_values
173 static const long register_values[] = {
174 /* DRB - DRAM Row Boundary Registers
176 * An array of 8 byte registers, which hold the ending
177 * memory address assigned to each pair of DIMMS, in 32MB
180 /* Conservatively say each row has 32MB of ram, we will fix this up later */
181 0x40, 0x00000000, (0x01 << 0) | (0x02 << 8) | (0x03 << 16) | (0x04 << 24),
182 /* DRA - DRAM Row Attribute Register
185 * [2:0] Row Attributes for both rows
192 /* leave it alone for now -- seems bad to set it at all
194 (((0<<3)|(0<<0))<< 0) |
195 (((0<<3)|(0<<0))<< 4) |
196 (((0<<3)|(0<<0))<< 8) |
197 (((0<<3)|(0<<0))<<12) |
198 (((0<<3)|(0<<0))<<16) |
199 (((0<<3)|(0<<0))<<20) |
200 (((0<<3)|(0<<0))<<24) |
201 (((0<<3)|(0<<0))<<28),
203 /* DRT - DRAM Time Register
205 * [31:31] tWTR -- MBZ
206 * [30:30] tWR 0 is 2, 1 is 3 clocks
207 * [29:28] back to back write-read commands spacing
209 * 00 4, 01 3, 10 2, 11 reserved
211 * [27:26] same or different
212 * CL + .5x BL + TA(RD-WR) - DQSS
214 * 00 7, 01 6, 10 5, 11 4
215 * 00 4, 01 3, 10 2, 11 reserved
217 * [25:25] Back to Back Read-read spacing
223 * [14:12] Refresh cycle time
224 * 000 14, 001 13, 010 12, 011 11, 100 10, 101 9, 110 8, 111 7
227 * 0 120 us, 1 reserved
229 * [10:09] Active to Precharge (tRAS)
235 * [06:05] Cas Latency (tCL)
237 * 01 == 2.0 Clocks (default)
241 * [03:02] Ras# to Cas# Delay (tRCD)
242 * 00 == 4 DRAM Clocks
243 * 01 == 3 DRAM Clocks
244 * 10 == 2 DRAM Clocks
246 * [01:00] DRAM RAS# to Precharge (tRP)
247 * 00 == 4 DRAM Clocks
248 * 01 == 3 DRAM Clocks
249 * 10 == 2 DRAM Clocks
253 #define DRT_CAS_2_5 (0<<5)
254 #define DRT_CAS_2_0 (1<<5)
255 #define DRT_CAS_MASK (3<<5)
257 #if CAS_LATENCY == CAS_2_5
258 #define DRT_CL DRT_CAS_2_5
259 #elif CAS_LATENCY == CAS_2_0
260 #define DRT_CL DRT_CAS_2_0
263 /* bios is 0x2a004425 */
264 /* default hardware is 18004425 */
265 /* no setting for now */
267 /* FDHC - Fixed DRAM Hole Control
270 * 0 == No memory Hole
271 * 1 == Memory Hole from 15MB to 16MB
274 * PAM - Programmable Attribute Map
275 * 0x90 [3:0] Reserved
276 * 0x90 [5:4] 0xF0000 - 0xFFFFF
277 * 0x91 [1:0] 0xC0000 - 0xC3FFF
278 * 0x91 [5:4] 0xC4000 - 0xC7FFF
279 * 0x92 [1:0] 0xC8000 - 0xCBFFF
280 * 0x92 [5:4] 0xCC000 - 0xCFFFF
281 * 0x93 [1:0] 0xD0000 - 0xD3FFF
282 * 0x93 [5:4] 0xD4000 - 0xD7FFF
283 * 0x94 [1:0] 0xD8000 - 0xDBFFF
284 * 0x94 [5:4] 0xDC000 - 0xDFFFF
285 * 0x95 [1:0] 0xE0000 - 0xE3FFF
286 * 0x95 [5:4] 0xE4000 - 0xE7FFF
287 * 0x96 [1:0] 0xE8000 - 0xEBFFF
288 * 0x96 [5:4] 0xEC000 - 0xEFFFF
289 * 00 == DRAM Disabled (All Access go to memory mapped I/O space)
290 * 01 == Read Only (Reads to DRAM, Writes to memory mapped I/O space)
291 * 10 == Write Only (Writes to DRAM, Reads to memory mapped I/O space)
292 * 11 == Normal (All Access go to DRAM)
294 /* 0x90, 0xcccccf7f, (0x00 << 0) | (0x30 << 8) | (0x33 << 16) | (0x33 << 24),*/
295 /*0x94, 0xcccccccc, (0x33 << 0) | (0x33 << 8) | (0x33 << 16) | (0x33 << 24),*/
298 /* FIXME why was I attempting to set a reserved bit? */
301 /* DRC - DRAM Contoller Mode Register
304 * [29:29] Initialization Complete
307 * [28:27] Dynamic Power Down Enable (leave at 0 for now)
309 * [23:23] Reduced Comamnd Drive Delay (leave at 0 for now)
310 * [22:22] Reduced Command Drive Enable (leave at 0 for now)
311 * [21:21] DRAM Data Integrity Mode
312 * 0 == Disabled, no ECC
313 * 1 == Error checking, with correction
317 * [17:17] (Intel Undocumented) should always be set to
318 * [16:16] Disable SCK Tri-state in C3/S1-m
322 * [13:13] Dynamic CS Disable
323 * [12:12] SM Interface Tristate enable
325 * [10:08] Refresh mode select
326 * 000 == Refresh disabled
327 * 001 == Refresh interval 15.6 usec
328 * 010 == Refresh interval 7.8 usec
329 * 011 == Refresh interval 64 usec
332 * [06:04] Mode Select (SMS)
333 * 000 == Self Refresh Mode
335 * 010 == All Banks Precharge
336 * 011 == Mode Register Set
337 * 100 == Extended Mode Register Set
340 * 111 == Normal Operation
342 * [00:00] DRAM type --hardwired to 1 to indicate DDR
345 /* undocumnted shit */
352 * Routine: ram_set_registers
355 * Trashed: %eax, %ebx, %ecx, %edx, %esi, %eflags
356 * Effects: Do basic ram setup that does not depend on serial
357 * presence detect information.
358 * This sets PCI configuration registers to known good
359 * values based on the table:
360 * constant_register_values
361 * Which are a triple of configuration regiser, mask, and value.
365 static void write_8dwords(uint32_t src_addr, uint32_t dst_addr) {
369 dword = read32(src_addr);
370 write32(dst_addr, dword);
377 /*#define SLOW_DOWN_IO inb(0x80);*/
378 #define SLOW_DOWN_IO udelay(40);
381 static void ram_set_d0f0_regs(const struct mem_controller *ctrl) {
387 max = sizeof(register_values)/sizeof(register_values[0]);
388 for(i = 0; i < max; i += 3) {
390 #if DEBUG_RAM_CONFIG >=2
391 print_debug_hex32(register_values[i]);
393 print_debug_hex32(register_values[i+2]);
396 reg = pci_read_config32(ctrl->d0,register_values[i]);
397 reg &= register_values[i+1];
398 reg |= register_values[i+2] & ~(register_values[i+1]);
399 pci_write_config32(ctrl->d0,register_values[i], reg);
407 static void sdram_set_registers(const struct mem_controller *ctrl){
408 ram_set_d0f0_regs(ctrl);
413 * Routine: sdram_spd_get_page_size
414 * Arguments: %bl SMBUS_MEM_DEVICE
416 * %edi log base 2 page size of DIMM side 1 in bits
417 * %esi log base 2 page size of DIMM side 2 in bits
419 * Preserved: %ebx (except %bh), %ebp
421 * Trashed: %eax, %bh, %ecx, %edx, %esp, %eflags
422 * Used: %eax, %ebx, %ecx, %edx, %esi, %edi, %esp, %eflags
424 * Effects: Uses serial presence detect to set %edi & %esi
425 * to the page size of a dimm.
427 * %bl SMBUS_MEM_DEVICE
428 * %edi holds the page size for the first side of the DIMM.
429 * %esi holds the page size for the second side of the DIMM.
430 * memory size is represent as a power of 2.
432 * This routine may be worth moving into generic code somewhere.
434 struct dimm_page_size {
439 static struct dimm_page_size sdram_spd_get_page_size(unsigned device) {
443 struct dimm_page_size pgsz;
448 value = spd_read_byte(device, 4); /* columns */
449 if(value < 0) goto hw_err;
450 pgsz.side1 = value & 0xf;
452 /* Get the module data width and convert it to a power of two */
453 value = spd_read_byte(device,7); /* (high byte) */
454 if(value < 0) goto hw_err;
458 value = spd_read_byte(device, 6); /* (low byte) */
459 if(value < 0) goto hw_err;
460 ecx |= (value & 0xff);
462 pgsz.side1 += log2(ecx); /* compute cheap log base 2 */
465 value = spd_read_byte(device, 5); /* number of physical banks */
466 if(value < 0) goto hw_err;
467 if(value==1) goto out;
468 if(value!=2) goto val_err;
470 /* Start with the symmetrical case */
471 pgsz.side2 = pgsz.side1;
472 value = spd_read_byte(device,4); /* columns */
473 if(value < 0) goto hw_err;
474 if((value & 0xf0)==0 ) goto out;
475 pgsz.side2 -=value & 0xf; /* Subtract out columns on side 1 */
476 pgsz.side2 +=(value>>4)& 0xf; /* Add in columns on side 2 */
480 die("Bad SPD value\r\n");
481 /* If an hw_error occurs report that I have no memory */
491 * Routine: sdram_spd_get_width
492 * Arguments: %bl SMBUS_MEM_DEVICE
494 * %edi width of SDRAM chips on DIMM side 1 in bits
495 * %esi width of SDRAM chips on DIMM side 2 in bits
497 * Preserved: %ebx (except %bh), %ebp
499 * Trashed: %eax, %bh, %ecx, %edx, %esp, %eflags
500 * Used: %eax, %ebx, %ecx, %edx, %esi, %edi, %esp, %eflags
502 * Effects: Uses serial presence detect to set %edi & %esi
503 * to the width of a dimm.
505 * %bl SMBUS_MEM_DEVICE
506 * %edi holds the width for the first side of the DIMM.
507 * %esi holds the width for the second side of the DIMM.
508 * memory size is represent as a power of 2.
510 * This routine may be worth moving into generic code somewhere.
517 static struct dimm_width sdram_spd_get_width(unsigned device) {
519 struct dimm_width wd;
525 value = spd_read_byte(device, 13); /* sdram width */
526 if(value < 0 ) goto hw_err;
529 wd.side1 = value & 0x7f;
532 value = spd_read_byte(device, 5); /* number of physical banks */
533 if(value < 0 ) goto hw_err;
534 if(value <=1 ) goto out;
536 /* Start with the symmetrical case */
539 if((ecx & 0x80)==0) goto out;
551 * Routine: sdram_spd_get_dimm_size
552 * Arguments: %bl SMBUS_MEM_DEVICE
554 * %edi log base 2 size of DIMM side 1 in bits
555 * %esi log base 2 size of DIMM side 2 in bits
557 * Preserved: %ebx (except %bh), %ebp
559 * Trashed: %eax, %bh, %ecx, %edx, %esp, %eflags
560 * Used: %eax, %ebx, %ecx, %edx, %esi, %edi, %esp, %eflags
562 * Effects: Uses serial presence detect to set %edi & %esi
563 * the size of a dimm.
565 * %bl SMBUS_MEM_DEVICE
566 * %edi holds the memory size for the first side of the DIMM.
567 * %esi holds the memory size for the second side of the DIMM.
568 * memory size is represent as a power of 2.
570 * This routine may be worth moving into generic code somewhere.
578 static struct dimm_size spd_get_dimm_size(unsigned device)
580 /* Calculate the log base 2 size of a DIMM in bits */
586 /* Note it might be easier to use byte 31 here, it has the DIMM size as
587 * a multiple of 4MB. The way we do it now we can size both
588 * sides of an assymetric dimm.
590 /* the hell with that! just use byte 31 -- rgm */
591 value = spd_read_byte(device, 31); /* size * 4 MB */
593 /* this is in 4 MB chunks, or 32 MBits chunks.
594 * log base 2 of 32 Mbits is log2 of (32*1024*1024) is 25
601 print_debug("returned size log 2 in bits is :");
602 print_debug_hex32(value);
607 die("Bad SPD value\r\n");
608 /* If an hw_error occurs report that I have no memory */
619 * This is a place holder fill this out
620 * Routine: spd_set_row_attributes
621 * Arguments: %bl SMBUS_MEM_DEVICE
623 * %edi log base 2 size of DIMM side 1 in bits
624 * %esi log base 2 size of DIMM side 2 in bits
626 * Preserved: %ebx (except %bh), %ebp
628 * Trashed: %eax, %bh, %ecx, %edx, %esp, %eflags
629 * Used: %eax, %ebx, %ecx, %edx, %esi, %edi, %esp, %eflags
631 * Effects: Uses serial presence detect to set %edi & %esi
632 * the size of a dimm.
634 * %bl SMBUS_MEM_DEVICE
635 * %edi holds the memory size for the first side of the DIMM.
636 * %esi holds the memory size for the second side of the DIMM.
637 * memory size is represent as a power of 2.
639 * This routine may be worth moving into generic code somewhere.
641 static long spd_set_row_attributes(const struct mem_controller *ctrl, long dimm_mask) {
643 uint16_t word=0x7777;
647 /* Walk through all dimms and find the interesection of the support
648 * for ecc sdram and refresh rates
652 for(i = 0; i < DIMM_SOCKETS; i++) {
653 if (!(dimm_mask & (1 << i))) {
656 /* Test to see if I have ecc sdram */
657 struct dimm_page_size sz;
658 sz = sdram_spd_get_page_size(ctrl->channel0[i]); /* SDRAM type */
660 print_debug("page size =");
661 print_debug_hex32(sz.side1);
663 print_debug_hex32(sz.side2);
667 /* Test to see if the dimm is present */
670 /* Test for a valid dimm width */
671 if((sz.side1 <15) || (sz.side1>18) ) {
672 print_err("unsupported page size\r\n");
675 /* Convert to the format needed for the DRA register */
676 /* subtract 3 (there are 8 bytes)
678 * (since 12 bit size should map to a value of 1)
679 * so subtract 14 total
683 /* Place in the %ebp the dra place holder */ /*i*/
685 word |= sz.side1<<(i<<3);
687 /* Test to see if the second side is present */
691 /* Test for a valid dimm width */
692 if((sz.side2 <15) || (sz.side2>18) ) {
693 print_err("unsupported page size\r\n");
696 /* Convert to the format needed for the DRA register */
699 /* Place in the %ebp the dra place holder */ /*i*/
701 word |= sz.side2<<((i<<3) + 4 );
705 /* go to the next DIMM */
708 /* Write the new row attributes register */
709 pci_write_config32(ctrl->d0, 0x50, word);
714 #define spd_pre_init "Reading SPD data...\r\n"
715 #define spd_pre_set "setting based on SPD data...\r\n"
716 #define spd_post_init "done\r\n"
719 static const uint32_t refresh_rate_rank[]= {
720 /* Refresh rates ordered from most conservative (lowest)
721 * to most agressive (highest)
722 * disabled 0 -> rank 3
723 * 15.6usec 1 -> rank 1
724 * 7.8 usec 2 -> rank 0
728 static const uint32_t refresh_rate_index[] = {
729 /* Map the spd refresh rates to memory controller settings
739 #define MAX_SPD_REFRESH_RATE 5
741 static long spd_set_dram_controller_mode (const struct mem_controller *ctrl, long dimm_mask) {
748 /* on this chipset we only do refresh "slow" or "fast" for now */
749 /* we start out assuming "slow" (15.6 microseconds) */
750 uint32_t refrate = 1; /* better than 7.8 */
752 /* Read the inititial state */
753 dword = pci_read_config32(ctrl->d0, 0x70);
755 /*dword |= 0x10000;*/
756 #if 0 /* DEBUG_RAM_CONFIG*/
757 print_debug("spd_detect_dimms: 0x70.l is:");
758 print_debug_hex32(dword);
763 /* Test if ECC cmos option is enabled */
764 /* Clear the ecc enable */
769 /* Walk through all dimms and find the interesection of the support
770 * for ecc sdram and refresh rates
774 for(i = 0; i < DIMM_SOCKETS; i++) {
775 if (!(dimm_mask & (1 << i))) {
778 /* Test to see if I have ecc sdram */
779 value = spd_read_byte(ctrl->channel0[i], 11); /* SDRAM type */
780 if(value < 0) continue;
783 print_debug("spd_detect_dimms:\r\n");
785 /* Clear the ecc enable */
787 #if 0 &&DEBUG_RAM_CONFIG
788 print_debug("spd_detect_dimms: no ecc so set:");
789 print_debug_hex32(dword);
794 value = spd_read_byte(ctrl->channel0[i], 12); /* SDRAM refresh rate */
795 if(value < 0 ) continue;
797 if(value > MAX_SPD_REFRESH_RATE) { print_err("unsupported refresh rate\r\n");}
798 /* if(value == 0xff) { print_err("unsupported refresh rate\r\n");}*/
801 print_debug("spd_detect_dimms: ref rate index:");
802 print_debug_hex8(value);
805 if (value == 2) /* have to go faster */
807 #if 0 &&DEBUG_RAM_CONFIG
808 print_debug("spd_detect_dimms: dword is now w/refresh:");
809 print_debug_hex32(dword);
812 /* no applicability here but there are similar things
816 value = spd_read_byte(ctrl->channel0[i], 33); /* Address and command hold time after clock */
817 if(value < 0) continue;
818 if(value >= 0xa0) { /* At 133Mhz this constant should be 0x75 */
819 dword &= ~(1<<16); /* Use two clock cyles instead of one */
823 /* go to the next DIMM */
826 /* set the refrate now */
827 dword |= (refrate << 7);
828 /* Now write the controller mode */
829 pci_write_config32(ctrl->d0, 0x70, dword);
834 static long spd_enable_clocks(const struct mem_controller *ctrl, long dimm_mask)
840 /* Read the inititial state */
841 dword = pci_read_config32(ctrl->d0, 0x8c);
843 Intel clears top bit here, should we?
844 No the default is on and for normal timming it should be on. Tom Z
848 for(i = 0; i < DIMM_SOCKETS; i++) {
849 if (!(dimm_mask & (1 << i))) {
852 /* Read any spd byte to see if the dimm is present */
853 value = spd_read_byte(ctrl->channel0[i], 5); /* Physical Banks */
854 if(value < 0) continue;
859 pci_write_config32(ctrl->d0, 0x8c, dword);
864 static const uint16_t cas_latency_80[] = {
865 /* For cas latency 2.0 0x01 works and until I see a large test sample
866 * I am not prepared to change this value, to the intel recommended value
867 * of 0x0d. Eric Biederman
869 /* The E7501 requires b1 rather than 01 for CAS2 or memory will be hosed
870 * CAS 1.5 is claimed to be unsupported, will try to test that
871 * will need to determine correct values for other CAS values
872 * (perhaps b5, b1, b6?)
873 * Steven James 02/06/2003
876 /*# .byte 0x05, 0x01, 0x06 */
877 /*# .byte 0xb5, 0xb1, 0xb6 */
878 0x0, 0x0bb1, 0x0662 /* RCVEN */
880 static const uint16_t cas_latency_80_4dimms[] = {
885 static const uint8_t cas_latency_78[] = {
886 DRT_CAS_2_0, DRT_CAS_2_5
889 static long spd_set_cas_latency(const struct mem_controller *ctrl, long dimm_mask) {
890 /* Walk through all dimms and find the interesection of the
891 * supported cas latencies.
894 /* Initially allow cas latencies 2.5, 2.0
895 * which the chipset supports.
897 uint32_t dword = (1<<3)| (1<<2);/* esi*/
906 for(i = 0; i < DIMM_SOCKETS; i++) {
907 if (!(dimm_mask & (1 << i))) {
910 value = spd_read_byte(ctrl->channel0[i], 18);
911 if(value < 0) continue;
912 /* Find the highest supported cas latency */
913 ecx = log2(value & 0xff);
916 /* Remember the supported cas latencies */
917 ecx = (value & 0xff);
919 /* Verify each cas latency at 133Mhz */
920 /* Verify slowest/highest CAS latency */
921 value = spd_read_byte(ctrl->channel0[i], 9);
922 if(value < 0 ) continue;
924 /* The bus is too fast so we cannot support this case latency */
928 /* Verify the highest CAS latency - 0.5 clocks */
931 value = spd_read_byte(ctrl->channel0[i], 23);
932 if(value < 0 ) continue;
934 /* The bus is too fast so we cannot support this cas latency */
939 /* Verify the highest CAS latency - 1.0 clocks */
942 value = spd_read_byte(ctrl->channel0[i], 25);
943 if(value < 0 ) continue;
945 /* The bus is too fast so we cannot support this cas latency */
950 /* Now find which cas latencies are supported for the bus */
952 /* go to the next DIMM */
955 /* After all of the arduous calculation setup with the fastest
956 * cas latency I can use.
958 value = __builtin_bsf(dword); /* bsrl = log2 how about bsfl?*/
959 if(value ==0 ) return -1;
962 byte = pci_read_config8(ctrl->d0, 0x78);
963 byte &= ~(DRT_CAS_MASK);
964 byte |= cas_latency_78[ecx];
965 pci_write_config8(ctrl->d0,0x78, byte);
967 /* set master DLL reset */
968 dword = pci_read_config32(ctrl->d0, 0x88);
971 /* the rest of the references are words */
972 /* ecx<<=1; // don't need shift left, because we already define that in u16 array*/
973 pci_write_config32(ctrl->d0, 0x88, dword);
976 dword &= 0x0c0000ff; /* patch try register 88 is undocumented tnz */
979 pci_write_config32(ctrl->d0, 0x88, dword);
981 word = pci_read_config16(ctrl->d0, 0x80);
983 word |= cas_latency_80[ecx];
985 dword = pci_read_config32(ctrl->d0, 0x70);
987 if((dword & 0xff) !=0 ) {
989 if((dword & 0xff)!=0) {
991 if((dword & 0xff)!=0) {
993 if( (dword & 0xff)!=0) {
994 word &=~(0x0fff); /* we have dimms in all 4 slots */
995 word |=cas_latency_80_4dimms[ecx];
1001 pci_write_config16(ctrl->d0, 0x80, word);
1003 dword = pci_read_config32(ctrl->d0, 0x88); /* reset master DLL reset */
1005 pci_write_config32(ctrl->d0, 0x88, dword);
1007 RAM_RESET_DDR_PTR(ctrl);
1013 static const unsigned int bustimings[8] = {
1014 /* first four are for GM part */
1016 /* and then the GME part */
1020 static long spd_set_dram_timing(const struct mem_controller *ctrl, long dimm_mask) {
1021 /* Walk through all dimms and find the interesection of the
1022 * supported dram timings.
1029 /* well, shit. Intel has not seen fit to document the observed
1030 * setting for these bits. On my chipset it is 3 right now, and
1031 * that's not in the table documented for this chip.
1032 * What a shame. We will assume 133 mhz I guess? not sure.
1033 * also they say in one place it is two bits and in another
1034 * they say it is 3 bits! we'll assume two bits, that's
1035 * the only one that makes sense.
1037 uint32_t rambusfrequency;
1040 /* what kind of chip is it? */
1041 /* only bit that really matters is high order bit ... */
1042 /* here is a problem with the memory controller struct ...
1043 * ram control is spread across d0/d1 on this part!
1045 ramindex = pci_read_config8(PCI_DEV(0,0,0), 0x44);
1048 /* compute the index into the table. Use the type of chip
1049 * as the high order bit and the 0:0.3:c0 & 7 as the low
1053 ramindex |= pci_read_config8(PCI_DEV(0,0,3), 0xc0) & 7;
1054 /* we now have an index into the clock rate table ... */
1056 rambusfrequency = bustimings[ramindex];
1058 /* Read the inititial state */
1059 dword = pci_read_config32(ctrl->d0, 0x60);
1060 #if DEBUG_RAM_CONFIG >= 10
1061 print_debug("spd_detect_dimms: bus timing index: ");
1062 print_debug_hex32(ramindex);
1063 print_debug(" and speed ");
1064 print_debug_hex32(rambusfrequency);
1065 print_debug("\r\n");
1068 /* for now, since we are on deadline, set to "known good" and
1071 pci_write_config32(ctrl->d0, 0x60, 0x2a004425);
1075 Intel clears top bit here, should we?
1076 No the default is on and for normal timming it should be on. Tom Z
1081 /* HERE. WHat's the frequency kenneth? */
1082 for(i = 0; i < DIMM_SOCKETS; i++) {
1083 if (!(dimm_mask & (1 << i))) {
1087 value = spd_read_byte(ctrl->channel0[i], 27);
1088 if(value < 0) continue;
1089 if(value > (15<<2)) {
1090 /* At 133Mhz if row precharge time is above than 15ns than we
1091 * need 3 clocks not 2 clocks.
1096 value = spd_read_byte(ctrl->channel0[i],29);
1097 if(value < 0 ) continue;
1098 if(value > (15<<2)) {
1099 /* At 133Mhz if the Minimum ras to cas delay is about 15ns we
1100 * need 3 clocks not 2 clocks.
1102 dword &= ~((1<<3)|(1<<1));
1105 value = spd_read_byte(ctrl->channel0[i],30);
1106 if(value < 0 ) continue;
1107 /* Convert tRAS from ns to 133Mhz clock cycles */
1108 value <<=1; /* mult by 2 to make 7.5 15 */
1109 value += 15; /* Make certain we round up */
1111 value &= 0xff; /* Clear the upper bits of eax */
1114 /* Don't even process small timings */
1117 /* Die if the value is to large */
1119 die ("unsupported_rcd\r\n");
1121 /* Convert to clocks - 5 */
1123 /* Convert the existing value into clocks - 5 */
1124 tmp = (~((dword>>9) & 3) - 1) & 3;
1125 /* See if we need a slower timing */
1127 /* O.k. put in our slower timing */
1129 dword |= ((~(value + 1)) & 3)<<9 ;
1134 /* Set to a 7 clock read delay. This is for 133Mhz
1135 * with a CAS latency of 2.5 if 2.0 a 6 clock
1137 if( (pci_read_config8(ctrl->d0, 0x78) & 0x30) ==0 ){
1138 dword &= ~(7<<24); /* CAS latency is 2.5, make 7 clks */
1142 * Back to Back Read Turn Around
1144 /* Set to a 3 clock back to back read turn around. This
1145 * is good for CAS latencys 2.5 and 2.0 */
1148 * Back to Back Read-Write Turn Around
1150 /* Set to a 5 clock back to back read to write turn around.
1151 * 4 is a good delay if the CAS latency is 2.0 */
1152 if( ( pci_read_config8(ctrl->d0, 0x78) & (1<<4)) == 0) {
1156 * Back to Back Write-Read Turn Around
1158 /* Set to a 2 clock back to back write to read turn around.
1159 * This is good for 2.5 and 2.0 CAS Latencies. */
1163 pci_write_config32(ctrl->d0, 0x60, dword);
1168 static unsigned int spd_detect_dimms(const struct mem_controller *ctrl)
1173 #if DEBUG_RAM_CONFIG
1174 print_debug("spd_detect_dimms:\r\n");
1176 for(i = 0; i < DIMM_SOCKETS; i++) {
1179 #if DEBUG_RAM_CONFIG
1180 print_debug_hex32(i);
1181 print_debug("\r\n");
1183 device = ctrl->channel0[i];
1185 byte = spd_read_byte(ctrl->channel0[i], 2); /* Type */
1187 dimm_mask |= (1 << i);
1195 static uint32_t set_dimm_size(const struct mem_controller *ctrl, struct dimm_size sz, uint32_t memsz, unsigned index)
1198 uint32_t base0, base1;
1202 /* I think size2 is always 0 ... */
1203 /* Double the size if we are using dual channel memory */
1204 if (sz.side1 != sz.side2) {
1209 /* Make certain side1 of the dimm is at least 32MB */
1210 /* This 28 is weird.
1211 * sz.size1 is log2 size in bits.
1212 * so what's 28? So think of it as this:
1213 * in log2 space: 10 + 10 + 8, i.e. 1024 * 1024 * 256 or
1214 * 256 Mbits, or 32 Mbytes.
1216 /* this is from the e7500 code and it's just wrong for small dimes (< 64 MB)
1217 * However, realistically, this case will never happen! the dimms are all bigger ...
1218 * so skip the conditional completely.
1219 * if (sz.side1 >= (28)) { }
1221 memsz += (1 << (sz.side1 - (28)) ) ;
1223 /* Write the size of side 1 of the dimm */
1224 #if DEBUG_RAM_CONFIG
1225 print_debug("Write size ");
1226 print_debug_hex8(memsz);
1227 print_debug(" to ");
1228 print_debug_hex8(0x40 + index);
1229 print_debug("\r\n");
1232 pci_write_config8(ctrl->d0, 0x40+index, byte);
1234 /* now, fill in DRBs where no physical slot exists */
1236 for(i=index+1;i<4;i++) {
1237 pci_write_config8(ctrl->d0, 0x40+i, byte);
1244 #define LAST_DRB_SLOT 0x43
1246 static long spd_set_ram_size(const struct mem_controller *ctrl, long dimm_mask)
1252 for(i = 0; i < DIMM_SOCKETS; i++) {
1253 struct dimm_size sz;
1254 if (!(dimm_mask & (1 << i))) {
1257 sz = spd_get_dimm_size(ctrl->channel0[i]);
1258 #if DEBUG_RAM_CONFIG
1259 print_debug("dimm size =");
1260 print_debug_hex32(sz.side1);
1262 print_debug_hex32(sz.side2);
1263 print_debug("\r\n");
1266 if (sz.side1 == 0) {
1267 return -1; /* Report SPD error */
1269 memsz = set_dimm_size(ctrl, sz, memsz, i);
1272 /* For now hardset everything at 128MB boundaries */
1273 /* %ebp has the ram size in multiples of 64MB */
1274 /* cmpl $0, %ebp /* test if there is no mem - smbus went bad */*/
1275 /* jz no_memory_bad_smbus*/
1277 /* I should really adjust all of this in C after I have resources
1278 * to all of the pcie devices.
1281 /* Round up to 128M granularity */
1286 pci_write_config16(ctrl->d0, 0xc4, word);
1289 /* FIXME will this work with 3.5G of ram? */
1290 /* Put TOLM at 3G */
1291 pci_write_config16(ctrl->d0, 0xc4, 0xc000);
1292 /* Hard code a 1G remap window, right after the ram */
1294 word = 0x40; /* Ensure we are over 4G */
1298 pci_write_config16(ctrl->d0, 0xc6, word);
1300 pci_write_config16(ctrl->d0, 0xc8, word);
1308 static void sdram_set_spd_registers(const struct mem_controller *ctrl) {
1310 #if DEBUG_RAM_CONFIG
1311 print_debug(spd_pre_init);
1313 /*activate_spd_rom(ctrl);*/
1314 dimm_mask = spd_detect_dimms(ctrl);
1315 if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) {
1316 print_debug("No memory for this controller\n");
1319 dimm_mask = spd_enable_clocks(ctrl, dimm_mask);
1322 /*spd_verify_dimms(ctrl);*/
1323 #if DEBUG_RAM_CONFIG
1324 print_debug(spd_pre_set);
1326 dimm_mask = spd_set_row_attributes(ctrl,dimm_mask);
1330 dimm_mask = spd_set_dram_controller_mode(ctrl,dimm_mask);
1335 /* skip for now until we just get "known good" up
1336 dimm_mask = spd_set_cas_latency(ctrl,dimm_mask);
1341 dimm_mask = spd_set_dram_timing(ctrl,dimm_mask);
1345 #if DEBUG_RAM_CONFIG
1346 print_debug(spd_post_init);
1348 /*moved from dram_post_init*/
1349 spd_set_ram_size(ctrl, dimm_mask);
1350 dump_pci_device(PCI_DEV(0,0,1));
1354 /* Unrecoverable error reading SPD data */
1355 print_err("SPD error - reset\r\n");
1361 /* I have finally seen ram bad enough to cause LinuxBIOS
1362 * to die in mysterious ways, before booting up far
1363 * enough to run a memory tester. This code attempts
1364 * to catch this blatantly bad ram, with a spot check.
1365 * For most cases you should boot all of the way up
1366 * and run a memory tester.
1368 /* Ensure I read/write each stick of bank of memory &&
1369 * that I do more than 1000 bytes to avoid the northbridge cache.
1370 * Only 64M of each side of each DIMM is currently mapped,
1371 * so we can handle > 4GB of ram here.
1374 static void ram_postinit(const struct mem_controller *ctrl) {
1375 #if DEBUG_RAM_CONFIG
1378 /*spd_set_ram_size(ctrl);*/
1380 #define FIRST_NORMAL_REFERENCE() CALL_LABEL(ram_postinit)
1382 #define SPECIAL_FINISHUP() CALL_LABEL(dram_finish)
1385 #define ecc_pre_init "Initializing ECC state...\r\n"
1386 #define ecc_post_init "ECC state initialized.\r\n"
1387 static void dram_finish(const struct mem_controller *ctrl)
1391 /* Test to see if ECC support is enabled */
1392 dword = pci_read_config32(ctrl->d0, 0x70);
1397 #if DEBUG_RAM_CONFIG
1398 // print_debug(ecc_pre_init);
1400 #if DEBUG_RAM_CONFIG
1401 // print_debug(ecc_post_init);
1404 /* Clear the ECC error bits */
1405 dword = pci_read_config32(ctrl->d0, 0x7c); /* FCS_EN */
1407 pci_write_config32(ctrl->d0, 0x7c, dword);
1411 #if DEBUG_RAM_CONFIG
1418 #if ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG
1419 #define ram_enable_1 "Ram Enable 1\r\n"
1420 #define ram_enable_2 "Ram Enable 2\r\n"
1421 #define ram_enable_3 "Ram Enable 3\r\n"
1422 #define ram_enable_4 "Ram Enable 4\r\n"
1423 #define ram_enable_5 "Ram Enable 5\r\n"
1424 #define ram_enable_6 "Ram Enable 6\r\n"
1425 #define ram_enable_7 "Ram Enable 7\r\n"
1426 #define ram_enable_8 "Ram Enable 8\r\n"
1427 #define ram_enable_9 "Ram Enable 9\r\n"
1428 #define ram_enable_10 "Ram Enable 10\r\n"
1429 #define ram_enable_11 "Ram Enable 11\r\n"
1432 /* Estimate that SLOW_DOWN_IO takes about 50&76us*/
1433 /* delay for 200us */
1434 void udelay(int usecs)
1437 for(i = 0; i < usecs; i++)
1443 static void DO_DELAY(void){
1448 #define DO_DELAY udelay(200);
1450 for(i=0; i<16;i++) { SLOW_DOWN_IO }
1454 #define EXTRA_DELAY DO_DELAY
1456 static void sdram_enable(int controllers, const struct mem_controller *ctrl)
1460 /* 1 & 2 Power up and start clocks */
1461 /* let the games begin. More undocumented shit, so we'll just set it
1464 mchtst = pci_read_config32(ctrl->d0, 0x68);
1465 #if DEBUG_RAM_CONFIG
1466 print_debug(ram_enable_1);
1467 print_debug_hex32(mchtst);
1471 mchtst = 0x10f10038;
1472 pci_write_config32(ctrl->d0, 0x68, mchtst);
1473 * can't find a ram power register ...
1476 #if DEBUG_RAM_CONFIG
1478 print_debug(ram_enable_2);
1481 /* A 200us delay is needed */
1487 #if DEBUG_RAM_CONFIG
1488 dump_pci_device(PCI_DEV(0, 0, 0)) ;
1489 print_debug(ram_enable_3);
1493 #undef DEBUG_RAM_CONFIG
1494 #define DEBUG_RAM_CONFIG 0
1495 /* 4 Precharge all */
1496 #if DEBUG_RAM_CONFIG
1497 print_debug(ram_enable_4);
1499 #undef DEBUG_RAM_CONFIG
1500 #define DEBUG_RAM_CONFIG 0
1501 RAM_PRECHARGE(ctrl);
1504 /* wait until the all banks idle state... */
1505 /* 5. Issue EMRS to enable DLL */
1506 #if DEBUG_RAM_CONFIG
1507 print_debug(ram_enable_5);
1513 #if DEBUG_RAM_CONFIG
1514 print_debug(ram_enable_6);
1519 /* Ensure a 200us delay between the DLL reset in step 6 and the final
1520 * mode register set in step 9.
1521 * Infineon needs this before any other command is sent to the ram.
1526 /* 7 Precharge all */
1527 #if DEBUG_RAM_CONFIG
1528 print_debug(ram_enable_7);
1530 RAM_PRECHARGE(ctrl);
1533 /* 8 Now we need 2 AUTO REFRESH / CBR cycles to be performed */
1534 #if DEBUG_RAM_CONFIG
1535 print_debug(ram_enable_8);
1541 /* And for good luck 6 more CBRs */
1555 /* 9 mode register set */
1556 #if DEBUG_RAM_CONFIG
1557 print_debug(ram_enable_9);
1562 /* 10 DDR Receive FIFO RE-Sync */
1563 #if DEBUG_RAM_CONFIG
1564 print_debug(ram_enable_10);
1566 RAM_RESET_DDR_PTR(ctrl);
1569 /* 11 normal operation */
1570 #if DEBUG_RAM_CONFIG
1571 print_debug(ram_enable_11);
1576 /* special from v1*/
1577 /*FIRST_NORMAL_REFERENCE();*/
1578 /*spd_set_ram_size(ctrl, 0x03);*/
1580 /* Finally enable refresh */
1581 ENABLE_REFRESH(ctrl);
1583 /*SPECIAL_FINISHUP();*/
1585 { char *c = (char *) 0;
1587 print_debug("Test: ");
1588 print_debug_hex8(*c);
1589 print_debug("\r\n");