src/northbridge/intel/i855pm/northbridge.c

   1 #include <console/console.h>
   2 #include <arch/io.h>
   3 #include <stdint.h>
   4 #include <device/device.h>
   5 #include <device/pci.h>
   6 #include <device/pci_ids.h>
   7 #include <cpu/cpu.h>
   8 #include <stdlib.h>
   9 #include <string.h>
  10 #include <bitops.h>
  11 #include "chip.h"
  12
  13 static void ram_resource(device_t dev, unsigned long index,
  14         unsigned long basek, unsigned long sizek)
  15 {
  16         struct resource *resource;
  17
  18         if (!sizek) {
  19                 return;
  20         }
  21         resource = new_resource(dev, index);
  22         resource->base  = ((resource_t)basek) << 10;
  23         resource->size  = ((resource_t)sizek) << 10;
  24         resource->flags =  IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
  25                 IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
  26 }
  27
  28 static void tolm_test(void *gp, struct device *dev, struct resource *new)
  29 {
  30         struct resource **best_p = gp;
  31         struct resource *best;
  32         best = *best_p;
  33         if (!best || (best->base > new->base)) {
  34                 best = new;
  35         }
  36         *best_p = best;
  37 }
  38
  39 static uint32_t find_pci_tolm(struct bus *bus)
  40 {
  41         struct resource *min;
  42         uint32_t tolm;
  43         min = 0;
  44         search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min);
  45         tolm = 0xffffffffUL;
  46         if (min && tolm > min->base) {
  47                 tolm = min->base;
  48         }
  49         return tolm;
  50 }
  51
  52 #if CONFIG_WRITE_HIGH_TABLES==1
  53 #define HIGH_TABLES_SIZE 64     // maximum size of high tables in KB
  54 extern uint64_t high_tables_base, high_tables_size;
  55 #endif
  56
  57 static void pci_domain_set_resources(device_t dev)
  58 {
  59         device_t mc_dev;
  60         uint32_t pci_tolm;
  61
  62         pci_tolm = find_pci_tolm(&dev->link[0]);
  63         mc_dev = dev->link[0].children;
  64         if (mc_dev) {
  65                 /* Figure out which areas are/should be occupied by RAM.
  66                  * This is all computed in kilobytes and converted to/from
  67                  * the memory controller right at the edges.
  68                  * Having different variables in different units is
  69                  * too confusing to get right.  Kilobytes are good up to
  70                  * 4 Terabytes of RAM...
  71                  */
  72                 uint16_t tolm_r;
  73                 unsigned long tomk, tolmk;
  74                 int idx;
  75
  76                 /* Get the value of the highest DRB. This tells the end of
  77                  * the physical memory.  The units are ticks of 32MB
  78                  * i.e. 1 means 32MB.
  79                  */
  80                 tomk = ((unsigned long)pci_read_config8(mc_dev, 0x63)) << 15;
  81                 /* Compute the top of Low memory */
  82                 tolmk = pci_tolm >> 10;
  83                 if (tolmk >= tomk) {
  84                         /* The PCI hole does does not overlap the memory.
  85                          */
  86                         tolmk = tomk;
  87                 }
  88                 /* Write the ram configuration registers,
  89                  * preserving the reserved bits.
  90                  */
  91                 tolm_r = pci_read_config16(mc_dev, 0xc4);
  92                 tolm_r = ((tolmk >> 10) << 3) | (tolm_r & 0xf);
  93                 pci_write_config16(mc_dev, 0xc4, tolm_r);
  94
  95                 /* Report the memory regions */
  96                 idx = 10;
  97                 ram_resource(dev, idx++, 0, 640);
  98                 ram_resource(dev, idx++, 768, tolmk - 768);
  99
 100 #if CONFIG_WRITE_HIGH_TABLES==1
 101                 /* Leave some space for ACPI, PIRQ and MP tables */
 102                 high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024;
 103                 high_tables_size = HIGH_TABLES_SIZE * 1024;
 104 #endif
 105         }
 106         assign_resources(&dev->link[0]);
 107 }
 108
 109 static struct device_operations pci_domain_ops = {
 110         .read_resources   = pci_domain_read_resources,
 111         .set_resources    = pci_domain_set_resources,
 112         .enable_resources = enable_childrens_resources,
 113         .init             = 0,
 114         .scan_bus         = pci_domain_scan_bus,
 115 };
 116
 117 static void cpu_bus_init(device_t dev)
 118 {
 119         initialize_cpus(&dev->link[0]);
 120 }
 121
 122 static void cpu_bus_noop(device_t dev)
 123 {
 124 }
 125
 126 static struct device_operations cpu_bus_ops = {
 127         .read_resources   = cpu_bus_noop,
 128         .set_resources    = cpu_bus_noop,
 129         .enable_resources = cpu_bus_noop,
 130         .init             = cpu_bus_init,
 131         .scan_bus         = 0,
 132 };
 133
 134 static void enable_dev(struct device *dev)
 135 {
 136         struct device_path path;
 137
 138         /* Set the operations if it is a special bus type */
 139         if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
 140                 dev->ops = &pci_domain_ops;
 141                 pci_set_method(dev);
 142         }
 143         else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
 144                 dev->ops = &cpu_bus_ops;
 145         }
 146 }
 147
 148 struct chip_operations northbridge_intel_i855pm_ops = {
 149         CHIP_NAME("Intel 855PM Northbridge")
 150         .enable_dev = enable_dev,
 151 };