2 * This file is part of the coreboot project.
4 * Copyright (C) 2006 Jon Dufresne <jon.dufresne@gmail.com>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #include <sdram_mode.h>
24 #define dumpnorth() dump_pci_device(PCI_DEV(0, 0, 1))
25 #define VG85X_MODE (SDRAM_BURST_4 | SDRAM_BURST_INTERLEAVED | SDRAM_CAS_2_5)
28 * Set only what I need until it works, then make it figure things out on boot
29 * assumes only one dimm is populated
32 static void sdram_set_registers(const struct mem_controller *ctrl)
35 print_debug("Before configuration:\n");
40 static void spd_set_row_attributes(const struct mem_controller *ctrl)
45 pci_write_config16(ctrl->d0, 0x50, dra_reg);
48 static void spd_set_dram_controller_mode(const struct mem_controller *ctrl)
52 /* drc_reg = 0x00009101; */
54 pci_write_config32(ctrl->d0, 0x70, drc_reg);
57 static void spd_set_dram_timing(const struct mem_controller *ctrl)
62 pci_write_config32(ctrl->d0, 0x60, drt_reg);
65 static void spd_set_dram_size(const struct mem_controller *ctrl)
70 pci_write_config32(ctrl->d0, 0x40, drb_reg);
73 static void spd_set_dram_pwr_management(const struct mem_controller *ctrl)
77 pwrmg_reg = 0x10f10430;
78 pci_write_config32(ctrl->d0, 0x68, pwrmg_reg);
81 static void spd_set_dram_throttle_control(const struct mem_controller *ctrl)
86 pci_write_config32(ctrl->d0, 0xa0, dtc_reg);
89 #define delay() udelay(200)
91 /* if ram still doesn't work do this function */
92 static void spd_set_undocumented_registers(const struct mem_controller *ctrl)
96 pci_write_config32(PCI_DEV(0, 0, 0), 0x10, 0xe0000008);
97 pci_write_config32(PCI_DEV(0, 0, 0), 0x2c, 0x35808086);
98 pci_write_config32(PCI_DEV(0, 0, 0), 0x48, 0xfec10000);
99 pci_write_config32(PCI_DEV(0, 0, 0), 0x50, 0x00440100);
101 pci_write_config32(PCI_DEV(0, 0, 0), 0x58, 0x11111000);
103 pci_write_config16(PCI_DEV(0, 0, 0), 0x52, 0x0002);
105 pci_write_config16(PCI_DEV(0, 0, 0), 0x52, 0x0044);
107 pci_write_config16(PCI_DEV(0, 0, 0), 0x52, 0x0000);
109 pci_write_config32(PCI_DEV(0, 0, 0), 0x58, 0x33333000);
110 pci_write_config32(PCI_DEV(0, 0, 0), 0x5c, 0x33333333);
112 pci_write_config32(PCI_DEV(0, 0, 0), 0x60, 0x0000390a);
113 pci_write_config32(PCI_DEV(0, 0, 0), 0x74, 0x02006056);
114 pci_write_config32(PCI_DEV(0, 0, 0), 0x78, 0x00800001);
116 pci_write_config32(PCI_DEV(0, 0, 0), 0xa8, 0x00000001);
118 pci_write_config32(PCI_DEV(0, 0, 0), 0xbc, 0x00001020);
120 pci_write_config32(PCI_DEV(0, 0, 0), 0xfc, 0x00000109);
124 pci_write_config32(ctrl->d0, 0x74, 0x00000001);
125 pci_write_config32(ctrl->d0, 0x78, 0x001fe974);
126 pci_write_config32(ctrl->d0, 0x80, 0x00af0039);
127 pci_write_config32(ctrl->d0, 0x84, 0x0000033c);
128 pci_write_config32(ctrl->d0, 0x88, 0x00000010);
129 pci_write_config32(ctrl->d0, 0x98, 0xde5a868c);
130 pci_write_config32(ctrl->d0, 0x9c, 0x404e0046);
131 pci_write_config32(ctrl->d0, 0xa8, 0x00020e1a);
132 pci_write_config32(ctrl->d0, 0xb4, 0x0044cdac);
133 pci_write_config32(ctrl->d0, 0xb8, 0x000055d4);
134 pci_write_config32(ctrl->d0, 0xbc, 0x024acd38);
135 pci_write_config32(ctrl->d0, 0xc0, 0x00000003);
139 pci_write_config32(PCI_DEV(0, 0, 3), 0x2c, 0x35858086);
140 pci_write_config32(PCI_DEV(0, 0, 3), 0x44, 0x11110000);
141 pci_write_config32(PCI_DEV(0, 0, 3), 0x48, 0x09614a3c);
142 pci_write_config32(PCI_DEV(0, 0, 3), 0x4c, 0x4b09604a);
143 pci_write_config32(PCI_DEV(0, 0, 3), 0x50, 0x00000962);
144 pci_write_config32(PCI_DEV(0, 0, 3), 0x5c, 0x0b023331);
145 pci_write_config32(PCI_DEV(0, 0, 3), 0x6c, 0x0000402e);
146 pci_write_config32(PCI_DEV(0, 0, 3), 0x78, 0xe7c70f7f);
147 pci_write_config32(PCI_DEV(0, 0, 3), 0x7c, 0x0284007f);
148 pci_write_config32(PCI_DEV(0, 0, 3), 0x84, 0x000000ef);
152 pci_write_config16(PCI_DEV(0, 0, 3), 0xc0, 0x0200);
153 pci_write_config16(PCI_DEV(0, 0, 3), 0xc0, 0x0400);
157 pci_write_config32(PCI_DEV(0, 0, 3), 0xc4, 0x00000000);
158 pci_write_config32(PCI_DEV(0, 0, 3), 0xd8, 0xff00c308);
159 pci_write_config32(PCI_DEV(0, 0, 3), 0xdc, 0x00000025);
160 pci_write_config32(PCI_DEV(0, 0, 3), 0xe0, 0x001f002a);
161 pci_write_config32(PCI_DEV(0, 0, 3), 0xe4, 0x009f0098);
162 pci_write_config32(PCI_DEV(0, 0, 3), 0xec, 0x00000400);
163 pci_write_config32(PCI_DEV(0, 0, 3), 0xf0, 0xc0000000);
167 static void sdram_set_spd_registers(const struct mem_controller *ctrl)
169 spd_set_row_attributes(ctrl);
170 spd_set_dram_controller_mode(ctrl);
171 spd_set_dram_timing(ctrl);
172 spd_set_dram_size(ctrl);
173 spd_set_dram_pwr_management(ctrl);
174 spd_set_dram_throttle_control(ctrl);
175 spd_set_undocumented_registers(ctrl);
178 static void ram_command(const struct mem_controller *ctrl,
184 drc_reg = pci_read_config32(ctrl->d0, 0x70);
185 drc_reg &= ~(7 << 4);
186 drc_reg |= (command << 4);
187 pci_write_config8(ctrl->d0, 0x70, drc_reg);
191 static void ram_command_mrs(const struct mem_controller *ctrl,
197 uint32_t adjusted_mode;
199 drc_reg = pci_read_config32(ctrl->d0, 0x70);
200 drc_reg &= ~(7 << 4);
201 drc_reg |= (command << 4);
202 pci_write_config8(ctrl->d0, 0x70, drc_reg);
203 /* Host address lines [13:3] map to DIMM address lines [11, 9:0] */
204 adjusted_mode = ((mode & 0x800) << (13 - 11)) | ((mode & 0x3ff) << (12 - 9));
205 print_debug("Setting mode: ");
206 print_debug_hex32(adjusted_mode + addr);
208 read32(adjusted_mode + addr);
211 static void set_initialize_complete(const struct mem_controller *ctrl)
215 drc_reg = pci_read_config32(ctrl->d0, 0x70);
216 drc_reg |= (1 << 29);
217 pci_write_config32(ctrl->d0, 0x70, drc_reg);
220 static void sdram_enable(int controllers, const struct mem_controller *ctrl)
223 uint32_t rank1 = (1 << 30) / 2;
224 print_debug("Ram enable 1\n");
228 print_debug("Ram enable 2\n");
229 ram_command(ctrl, 1, 0);
230 ram_command(ctrl, 1, rank1);
234 print_debug("Ram enable 3\n");
235 ram_command(ctrl, 2, 0);
236 ram_command(ctrl, 2, rank1);
240 print_debug("Ram enable 4\n");
241 ram_command_mrs(ctrl, 4, SDRAM_EXTMODE_DLL_ENABLE, 0);
242 ram_command_mrs(ctrl, 4, SDRAM_EXTMODE_DLL_ENABLE, rank1);
246 print_debug("Ram enable 5\n");
247 ram_command_mrs(ctrl, 3, VG85X_MODE | SDRAM_MODE_DLL_RESET, 0);
248 ram_command_mrs(ctrl, 3, VG85X_MODE | SDRAM_MODE_DLL_RESET, rank1);
250 print_debug("Ram enable 6\n");
251 ram_command(ctrl, 2, 0);
252 ram_command(ctrl, 2, rank1);
256 print_debug("Ram enable 7\n");
257 for(i = 0; i < 8; i++) {
258 ram_command(ctrl, 6, 0);
259 ram_command(ctrl, 6, rank1);
264 print_debug("Ram enable 8\n");
265 ram_command_mrs(ctrl, 3, VG85X_MODE | SDRAM_MODE_NORMAL, 0);
266 ram_command_mrs(ctrl, 3, VG85X_MODE | SDRAM_MODE_NORMAL, rank1);
268 print_debug("Ram enable 9\n");
269 ram_command(ctrl, 7, 0);
270 ram_command(ctrl, 7, rank1);
274 print_debug("Ram enable 9\n");
275 set_initialize_complete(ctrl);
281 print_debug("After configuration:\n");
282 /* dump_pci_devices(); */
285 print_debug("\n\n***** RAM TEST *****\n");
286 ram_check(0, 0xa0000);
287 ram_check(0x100000, 0x40000000);