2 * This file is part of the coreboot project.
4 * Copyright (C) 2008-2010 Joseph Smith <joe@settoplinux.org>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #include <console/console.h>
24 #include <device/device.h>
25 #include <device/pci.h>
26 #include <device/pci_ids.h>
31 #include <boot/tables.h>
35 static void northbridge_init(device_t dev)
37 printk(BIOS_SPEW, "Northbridge init\n");
40 static struct device_operations northbridge_operations = {
41 .read_resources = pci_dev_read_resources,
42 .set_resources = pci_dev_set_resources,
43 .enable_resources = pci_dev_enable_resources,
44 .init = northbridge_init,
49 static const struct pci_driver northbridge_driver __pci_driver = {
50 .ops = &northbridge_operations,
51 .vendor = PCI_VENDOR_ID_INTEL,
55 static void ram_resource(device_t dev, unsigned long index,
56 unsigned long basek, unsigned long sizek)
58 struct resource *resource;
62 resource = new_resource(dev, index);
63 resource->base = ((resource_t) basek) << 10;
64 resource->size = ((resource_t) sizek) << 10;
65 resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE |
66 IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
69 static void tolm_test(void *gp, struct device *dev, struct resource *new)
71 struct resource **best_p = gp;
72 struct resource *best;
74 if (!best || (best->base > new->base))
79 static uint32_t find_pci_tolm(struct bus *bus)
84 search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test,
87 if (min && tolm > min->base)
93 uint64_t uma_memory_base=0, uma_memory_size=0;
95 int add_northbridge_resources(struct lb_memory *mem)
97 printk(BIOS_DEBUG, "Adding IGD UMA memory area\n");
98 lb_add_memory_range(mem, LB_MEM_RESERVED,
99 uma_memory_base, uma_memory_size);
104 #if CONFIG_WRITE_HIGH_TABLES==1
105 #define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB
106 extern uint64_t high_tables_base, high_tables_size;
108 static void pci_domain_set_resources(device_t dev)
114 pci_tolm = find_pci_tolm(dev->link_list);
115 mc_dev = dev->link_list->children;
119 unsigned long tomk, tolmk;
122 if (CONFIG_VIDEO_MB == 512) {
123 igd_memory = (CONFIG_VIDEO_MB);
124 printk(BIOS_DEBUG, "%dKB IGD UMA\n", igd_memory >> 10);
126 igd_memory = (CONFIG_VIDEO_MB * 1024);
127 printk(BIOS_DEBUG, "%dMB IGD UMA\n", igd_memory >> 10);
130 /* Get the value of the highest DRB. This tells the end of
131 * the physical memory. The units are ticks of 32MB
134 tomk = ((unsigned long)pci_read_config8(mc_dev, DRB + 3)) << 15;
137 /* For reserving UMA memory in the memory map */
138 uma_memory_base = tomk * 1024ULL;
139 uma_memory_size = igd_memory * 1024ULL;
140 printk(BIOS_DEBUG, "Available memory: %ldKB\n", tomk);
142 /* Compute the top of low memory. */
143 tolmk = pci_tolm >> 10;
145 /* The PCI hole does does not overlap the memory. */
149 /* Report the memory regions. */
151 ram_resource(dev, idx++, 0, 640);
152 ram_resource(dev, idx++, 768, 256);
153 ram_resource(dev, idx++, 1024, tolmk - 1024);
155 assign_resources(dev->link_list);
157 #if CONFIG_WRITE_HIGH_TABLES==1
158 /* Leave some space for ACPI, PIRQ and MP tables */
159 high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024;
160 high_tables_size = HIGH_TABLES_SIZE * 1024;
164 static struct device_operations pci_domain_ops = {
165 .read_resources = pci_domain_read_resources,
166 .set_resources = pci_domain_set_resources,
167 .enable_resources = enable_childrens_resources,
169 .scan_bus = pci_domain_scan_bus,
172 static void cpu_bus_init(device_t dev)
174 initialize_cpus(dev->link_list);
177 static void cpu_bus_noop(device_t dev)
181 static struct device_operations cpu_bus_ops = {
182 .read_resources = cpu_bus_noop,
183 .set_resources = cpu_bus_noop,
184 .enable_resources = cpu_bus_noop,
185 .init = cpu_bus_init,
189 static void enable_dev(struct device *dev)
193 /* Set the operations if it is a special bus type. */
194 if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
195 dev->ops = &pci_domain_ops;
197 } else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
198 dev->ops = &cpu_bus_ops;
202 struct chip_operations northbridge_intel_i82830_ops = {
203 CHIP_NAME("Intel 82830 Northbridge")
204 .enable_dev = enable_dev,