2 * This file is part of the coreboot project.
4 * Copyright (C) 2007-2009 Uwe Hermann <uwe@hermann-uwe.de>
5 * Copyright (C) 2007 Corey Osgood <corey.osgood@gmail.com>
6 * Copyright (C) 2008-2009 Elia Yehuda <z4ziggy@gmail.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
27 /*-----------------------------------------------------------------------------
28 Macros and definitions.
29 -----------------------------------------------------------------------------*/
31 /* Debugging macros. */
32 #define HAVE_ENOUGH_REGISTERS 0 /* Don't have enough registers to compile all
33 * debugging code with ROMCC
35 #if CONFIG_DEBUG_RAM_SETUP
36 #define PRINT_DEBUG(x) print_debug(x)
37 #define PRINT_DEBUG_HEX8(x) print_debug_hex8(x)
38 #define PRINT_DEBUG_HEX16(x) print_debug_hex16(x)
39 #define PRINT_DEBUG_HEX32(x) print_debug_hex32(x)
40 // no dump_pci_device in src/northbridge/intel/i82810/
41 // #define DUMPNORTH() dump_pci_device(PCI_DEV(0, 0, 0))
44 #define PRINT_DEBUG(x)
45 #define PRINT_DEBUG_HEX8(x)
46 #define PRINT_DEBUG_HEX16(x)
47 #define PRINT_DEBUG_HEX32(x)
51 /* DRAMT[7:5] - SDRAM Mode Select (SMS). */
52 #define RAM_COMMAND_SELF_REFRESH 0x0 /* Disable refresh */
53 #define RAM_COMMAND_NORMAL 0x1 /* Refresh: 15.6/11.7us for 100/133MHz */
54 #define RAM_COMMAND_NORMAL_FR 0x2 /* Refresh: 7.8/5.85us for 100/133MHz */
55 #define RAM_COMMAND_NOP 0x4 /* NOP command */
56 #define RAM_COMMAND_PRECHARGE 0x5 /* All bank precharge */
57 #define RAM_COMMAND_MRS 0x6 /* Mode register set */
58 #define RAM_COMMAND_CBR 0x7 /* CBR */
61 * Table which returns the RAM size in MB when fed the DRP[7:4] or [3:0] value.
62 * Note that 2 is a value which the DRP should never be programmed to.
63 * Some size values appear twice, due to single-sided vs dual-sided banks.
65 static const u16 translate_i82810_to_mb[] = {
66 /* DRP 0 1 (2) 3 4 5 6 7 8 9 A B C D E F */
67 /* MB */0, 8, 0, 16, 16, 24, 32, 32, 48, 64, 64, 96, 128, 128, 192, 256,
70 /* Size of bank#0 for dual-sided DIMMs */
71 static const u8 translate_i82810_to_bank[] = {
72 /* DRP 0 1 (2) 3 4 5 6 7 8 9 A B C D E F */
73 /* MB */0, 0, 0, 8, 0, 16, 16, 0, 32, 32, 0, 64, 64, 0, 128, 128,
77 u8 ds; /* dual-sided */
78 u8 ss; /* single-sided */
82 /*-----------------------------------------------------------------------------
83 SDRAM configuration functions.
84 -----------------------------------------------------------------------------*/
87 * Send the specified RAM command to all DIMMs.
89 * @param The RAM command to send to the DIMM(s).
91 static void do_ram_command(u8 command)
93 u32 addr, addr_offset;
94 u16 dimm_size, dimm_start, dimm_bank;
98 /* Configure the RAM command. */
99 reg8 = pci_read_config8(PCI_DEV(0, 0, 0), DRAMT);
100 reg8 &= 0x1f; /* Clear bits 7-5. */
101 reg8 |= command << 5;
102 pci_write_config8(PCI_DEV(0, 0, 0), DRAMT, reg8);
105 * RAM_COMMAND_NORMAL affects only the memory controller and
106 * doesn't need to be "sent" to the DIMMs.
108 if (command == RAM_COMMAND_NORMAL)
112 for (i = 0; i < DIMM_SOCKETS; i++) {
114 * Calculate the address offset where we need to "send" the
115 * DIMM command to. For most commands the offset is 0, only
116 * RAM_COMMAND_MRS needs special values, see below.
117 * The final address offset bits depend on three things:
119 * (1) Some hardcoded values specified in the datasheet.
120 * (2) Which CAS latency we will use/set. This is the SMAA[4]
121 * bit, which is 1 for CL3, and 0 for CL2. The bitstring
122 * so far has the form '00000001X1010', X being SMAA[4].
123 * (3) The DIMM to which we want to send the command. For
124 * DIMM0 no special handling is needed, but for DIMM1 we
125 * must invert the four bits SMAA[7:4] (see datasheet).
127 * Finally, the bitstring has to be shifted 3 bits to the left.
128 * See i810 datasheet pages 43, 85, and 86 for details.
131 caslatency = 3; /* TODO: Dynamically get CAS latency later. */
132 if (i == 0 && command == RAM_COMMAND_MRS && caslatency == 3)
133 addr_offset = 0x1d0; /* DIMM0, CL3, 0000111010000 */
134 if (i == 1 && command == RAM_COMMAND_MRS && caslatency == 3)
135 addr_offset = 0x650; /* DIMM1, CL3, 0011001010000 */
136 if (i == 0 && command == RAM_COMMAND_MRS && caslatency == 2)
137 addr_offset = 0x150; /* DIMM0, CL2, 0000101010000 */
138 if (i == 1 && command == RAM_COMMAND_MRS && caslatency == 2)
139 addr_offset = 0x1a0; /* DIMM1, CL2, 0000110100000 */
141 drp = pci_read_config8(PCI_DEV(0, 0, 0), DRP);
142 drp = (drp >> (i * 4)) & 0x0f;
144 dimm_size = translate_i82810_to_mb[drp];
146 addr = (dimm_start * 1024 * 1024) + addr_offset;
147 #if HAVE_ENOUGH_REGISTERS
148 PRINT_DEBUG(" Sending RAM command 0x");
149 PRINT_DEBUG_HEX8(reg8);
150 PRINT_DEBUG(" to 0x");
151 PRINT_DEBUG_HEX32(addr);
158 dimm_bank = translate_i82810_to_bank[drp];
160 addr = ((dimm_start + dimm_bank) * 1024 * 1024) + addr_offset;
161 #if HAVE_ENOUGH_REGISTERS
162 PRINT_DEBUG(" Sending RAM command 0x");
163 PRINT_DEBUG_HEX8(reg8);
164 PRINT_DEBUG(" to 0x");
165 PRINT_DEBUG_HEX32(addr);
171 dimm_start += dimm_size;
175 /*-----------------------------------------------------------------------------
176 DIMM-independant configuration functions.
177 -----------------------------------------------------------------------------*/
180 * Set DRP - DRAM Row Population Register (Device 0).
182 static void spd_set_dram_size(void)
184 /* The variables drp and dimm_size have to be ints since all the
185 * SMBus-related functions return ints, and its just easier this way.
187 int i, drp, dimm_size;
191 for (i = 0; i < DIMM_SOCKETS; i++) {
192 /* First check if a DIMM is actually present. */
193 if (smbus_read_byte(DIMM_SPD_BASE + i, 2) == 4) {
194 print_debug("Found DIMM in slot ");
198 dimm_size = smbus_read_byte(DIMM_SPD_BASE + i, 31);
200 /* WISHLIST: would be nice to display it as decimal? */
201 print_debug("DIMM is 0x");
202 print_debug_hex8(dimm_size * 4);
205 /* The i810 can't handle DIMMs larger than 128MB per
206 * side. This will fail if the DIMM uses a
207 * non-supported DRAM tech, and can't be used until
208 * buffers are done dynamically.
209 * Note: the factory BIOS just dies if it spots this :D
211 if (dimm_size > 32) {
212 print_err("DIMM row sizes larger than 128MB not"
213 "supported on i810\n");
215 ("Attempting to treat as 128MB DIMM\n");
219 /* This array is provided in raminit.h, because it got
220 * extremely messy. The above way is cleaner, but
221 * doesn't support any asymetrical/odd configurations.
223 dimm_size = translate_spd_to_i82810[dimm_size];
225 print_debug("After translation, dimm_size is 0x");
226 print_debug_hex8(dimm_size);
229 /* If the DIMM is dual-sided, the DRP value is +2 */
230 /* TODO: Figure out asymetrical configurations. */
231 if ((smbus_read_byte(DIMM_SPD_BASE + i, 127) | 0xf) ==
233 print_debug("DIMM is dual-sided\n");
237 print_debug("No DIMM found in slot ");
241 /* If there's no DIMM in the slot, set value to 0. */
245 /* Put in dimm_size to reflect the current DIMM. */
246 drp |= dimm_size << (i * 4);
249 print_debug("DRP calculated to 0x");
250 print_debug_hex8(drp);
253 pci_write_config8(PCI_DEV(0, 0, 0), DRP, drp);
256 static void set_dram_timing(void)
258 /* TODO, for now using default, hopefully safe values. */
259 // pci_write_config8(PCI_DEV(0, 0, 0), DRAMT, 0x00);
263 * TODO: BUFF_SC needs to be set according to the DRAM tech (x8, x16,
264 * or x32), but the datasheet doesn't list all the details. Currently, it
265 * needs to be pulled from the output of 'lspci -xxx Rx92'.
267 * Common results (tested on actual hardware) are:
269 * (DRP: c = 128MB dual sided, d = 128MB single sided, f = 256MB dual sided)
271 * BUFF_SC TOM DRP DIMM0 DIMM1
272 * ----------------------------------------------------------------------------
273 * 0x3356 128MB 0x0c 128MB dual-sided -
274 * 0xcc56 128MB 0xc0 - 128MB dual-sided
275 * 0x77da 128MB 0x0d 128MB single-sided -
276 * 0xddda 128MB 0xd0 - 128MB single-sided
277 * 0x0001 256MB 0xcc 128MB dual-sided 128MB dual-sided
278 * 0x55c6 256MB 0xdd 128MB single-sided 128MB single-sided
279 * 0x4445 256MB 0xcd 128MB single-sided 128MB dual-sided
280 * 0x1145 256MB 0xdc 128MB dual-sided 128MB single-sided
281 * 0x3356 256MB 0x0f 256MB dual-sided -
282 * 0xcc56 256MB 0xf0 - 256MB dual-sided
283 * 0x0001 384MB 0xcf 256MB dual-sided 128MB dual-sided
284 * 0x0001 384MB 0xfc 128MB dual-sided 256MB dual-sided
285 * 0x1145 384MB 0xdf 256MB dual-sided 128MB single-sided
286 * 0x4445 384MB 0xfd 128MB single-sided 256MB dual-sided
287 * 0x0001 512MB 0xff 256MB dual-sided 256MB dual-sided
290 * http://www.coreboot.org/pipermail/coreboot/2009-May/047966.html
292 static void set_dram_buffer_strength(void)
294 struct dimm_info d0, d1;
297 /* Check first slot. */
298 d0.size = d0.ds = d0.ss = 0;
299 if (smbus_read_byte(DIMM_SPD_BASE, SPD_MEMORY_TYPE)
300 == SPD_MEMORY_TYPE_SDRAM) {
301 d0.size = smbus_read_byte(DIMM_SPD_BASE, SPD_BANK_DENSITY);
302 d0.ds = smbus_read_byte(DIMM_SPD_BASE, SPD_NUM_DIMM_BANKS) > 1;
306 /* Check second slot. */
307 d1.size = d1.ds = d1.ss = 0;
308 if (smbus_read_byte(DIMM_SPD_BASE + 1, SPD_MEMORY_TYPE)
309 == SPD_MEMORY_TYPE_SDRAM) {
310 d1.size = smbus_read_byte(DIMM_SPD_BASE + 1, SPD_BANK_DENSITY);
311 d1.ds = smbus_read_byte(DIMM_SPD_BASE + 1,
312 SPD_NUM_DIMM_BANKS) > 1;
318 /* Tame the beast... */
319 if ((d0.ds && d1.ds) || (d0.ds && d1.ss) || (d0.ss && d1.ds))
321 if ((d0.size && !d1.size) || (!d0.size && d1.size) || (d0.ss && d1.ss))
323 if ((d0.ds && !d1.size) || (!d0.size && d1.ds) || (d0.ss && d1.ss)
324 || (d0.ds && d1.ss) || (d0.ss && d1.ds))
326 if ((d0.ss && !d1.size) || (!d0.size && d1.ss))
328 if ((d0.size && !d1.size) || (!d0.size && d1.size))
330 if ((d0.ds && !d1.size) || (!d0.size && d1.ds) || (d0.ds && d1.ss)
333 if ((d0.ss && !d1.size) || (!d0.size && d1.ss) || (d0.ss && d1.ss))
335 if ((!d0.size && d1.ss) || (d0.ds && d1.ss) || (d0.ss && d1.ss))
337 if (d0.size && !d1.size)
339 if ((d0.ss && !d1.size) || (d0.ss && d1.ss) || (d0.ss && d1.ds))
341 if (!d0.size && d1.size)
343 if ((d0.size && !d1.size) || (d0.ss && !d1.size) || (!d0.size && d1.ss)
344 || (d0.ss && d1.ss) || (d0.ds && d1.ss))
346 if (d0.size && !d1.size)
348 if ((!d0.size && d1.size) || (d0.ss && !d1.size) || (d0.ss && d1.ss)
351 if (!d0.size && d1.size)
354 print_debug("BUFF_SC calculated to 0x");
355 print_debug_hex16(buff_sc);
358 pci_write_config16(PCI_DEV(0, 0, 0), BUFF_SC, buff_sc);
361 /*-----------------------------------------------------------------------------
363 -----------------------------------------------------------------------------*/
365 static void sdram_set_registers(void)
370 did = pci_read_config16(PCI_DEV(0, 0, 0), PCI_DEVICE_ID);
372 /* Ideally, this should be R/W for as many ranges as possible. */
373 pci_write_config8(PCI_DEV(0, 0, 0), PAMR, 0xff);
375 /* Set size for onboard-VGA framebuffer. */
376 reg8 = pci_read_config8(PCI_DEV(0, 0, 0), SMRAM);
377 reg8 &= 0x3f; /* Disable graphics (for now). */
379 if (CONFIG_VIDEO_MB == 512)
380 reg8 |= (1 << 7); /* Enable graphics (512KB RAM). */
381 else if (CONFIG_VIDEO_MB == 1)
382 reg8 |= (1 << 7) | (1 << 6); /* Enable graphics (1MB RAM). */
384 pci_write_config8(PCI_DEV(0, 0, 0), SMRAM, reg8);
386 /* MISSC2: Bits 1, 2, 6, 7 must be set for VGA (see datasheet). */
387 reg8 = pci_read_config8(PCI_DEV(0, 0, 0), MISSC2);
388 reg8 |= (1 << 1); /* Instruction Parser Unit-Level Clock Gating */
389 reg8 |= (1 << 2); /* Palette Load Select */
391 /* Bits 6 and 7 are only available on 82810E (not 82810). */
392 reg8 |= (1 << 6); /* Text Immediate Blit */
393 reg8 |= (1 << 7); /* Must be 1 as per datasheet. */
395 pci_write_config8(PCI_DEV(0, 0, 0), MISSC2, reg8);
398 static void sdram_set_spd_registers(void)
401 set_dram_buffer_strength();
408 static void sdram_enable(void)
413 PRINT_DEBUG("RAM Enable 1: Apply NOP\n");
414 do_ram_command(RAM_COMMAND_NOP);
417 /* 2. Precharge all. Wait tRP. */
418 PRINT_DEBUG("RAM Enable 2: Precharge all\n");
419 do_ram_command(RAM_COMMAND_PRECHARGE);
422 /* 3. Perform 8 refresh cycles. Wait tRC each time. */
423 PRINT_DEBUG("RAM Enable 3: CBR\n");
424 for (i = 0; i < 8; i++) {
425 do_ram_command(RAM_COMMAND_CBR);
429 /* 4. Mode register set. Wait two memory cycles. */
430 PRINT_DEBUG("RAM Enable 4: Mode register set\n");
431 do_ram_command(RAM_COMMAND_MRS);
434 /* 5. Normal operation (enables refresh at 15.6usec). */
435 PRINT_DEBUG("RAM Enable 5: Normal operation\n");
436 do_ram_command(RAM_COMMAND_NORMAL);
439 PRINT_DEBUG("Northbridge following SDRAM init:\n");