2 * This file is part of the coreboot project.
4 * Copyright (C) 2007-2009 Uwe Hermann <uwe@hermann-uwe.de>
5 * Copyright (C) 2007 Corey Osgood <corey.osgood@gmail.com>
6 * Copyright (C) 2008-2009 Elia Yehuda <z4ziggy@gmail.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
27 /*-----------------------------------------------------------------------------
28 Macros and definitions.
29 -----------------------------------------------------------------------------*/
31 /* Debugging macros. */
32 #define HAVE_ENOUGH_REGISTERS 0 /* Don't have enough registers to compile all
33 * debugging code with ROMCC
35 #if CONFIG_DEBUG_RAM_SETUP
36 #define PRINT_DEBUG(x) print_debug(x)
37 #define PRINT_DEBUG_HEX8(x) print_debug_hex8(x)
38 #define PRINT_DEBUG_HEX16(x) print_debug_hex16(x)
39 #define PRINT_DEBUG_HEX32(x) print_debug_hex32(x)
40 // no dump_pci_device in src/northbridge/intel/i82810/
41 // #define DUMPNORTH() dump_pci_device(PCI_DEV(0, 0, 0))
44 #define PRINT_DEBUG(x)
45 #define PRINT_DEBUG_HEX8(x)
46 #define PRINT_DEBUG_HEX16(x)
47 #define PRINT_DEBUG_HEX32(x)
51 /* DRAMT[7:5] - SDRAM Mode Select (SMS). */
52 #define RAM_COMMAND_SELF_REFRESH 0x0 /* Disable refresh */
53 #define RAM_COMMAND_NORMAL 0x1 /* Refresh: 15.6/11.7us for 100/133MHz */
54 #define RAM_COMMAND_NORMAL_FR 0x2 /* Refresh: 7.8/5.85us for 100/133MHz */
55 #define RAM_COMMAND_NOP 0x4 /* NOP command */
56 #define RAM_COMMAND_PRECHARGE 0x5 /* All bank precharge */
57 #define RAM_COMMAND_MRS 0x6 /* Mode register set */
58 #define RAM_COMMAND_CBR 0x7 /* CBR */
61 * This table is used to translate the value read from SPD Byte 31 to a value
62 * the northbridge can understand in DRP, aka Rx52[7:4], [3:0]. Where most
63 * northbridges have some sort of simple calculation that can be done for this,
64 * I haven't yet figured out one for this northbridge. Until someone does,
65 * this table is necessary.
67 static const u8 translate_spd_to_i82810[] = {
68 /* Note: 4MB sizes are not supported, so dual-sided DIMMs with a 4MB
69 * side can't be either, at least for now.
71 /* TODO: For above case, only use the other side if > 4MB, and get some
72 * of these DIMMs to test it with. Same for unsupported 128/x sizes.
75 /* SPD Byte 31 Memory Size [Side 1/2] */
76 0xff, /* 0x01 No memory */
80 0x04, /* 0x04 16/0 or 16 */
83 0xff, /* 0x07 Invalid */
84 0x07, /* 0x08 32/0 or 32 */
87 0xff, /* 0x0B Invalid */
88 0x08, /* 0x0C 32/16 */
89 0xff, 0xff, 0xff, /* 0x0D-0F Invalid */
90 0x0a, /* 0x10 64/0 or 64 */
93 0xff, /* 0x13 Invalid */
94 0xff, /* 0x14 64/16 */
95 0xff, 0xff, 0xff, /* 0x15-17 Invalid */
96 0x0b, /* 0x18 64/32 */
97 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 0x19-1f Invalid */
98 0x0d, /* 0x20 128/0 or 128 */
99 /* These configurations are not supported by the i810 */
100 0xff, /* 0x21 128/4 */
101 0xff, /* 0x22 128/8 */
102 0xff, /* 0x23 Invalid */
103 0xff, /* 0x24 128/16 */
104 0xff, 0xff, 0xff, /* 0x25-27 Invalid */
105 0xff, /* 0x28 128/32 */
106 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 0x29-2f Invalid */
107 0x0e, /* 0x30 128/64 */
108 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
109 0xff, 0xff, 0xff, /* 0x31-3f Invalid */
110 0x0f, /* 0x40 256/0 or 256 */
111 /* Anything larger is not supported by the 82810. */
115 * Table which returns the RAM size in MB when fed the DRP[7:4] or [3:0] value.
116 * Note that 2 is a value which the DRP should never be programmed to.
117 * Some size values appear twice, due to single-sided vs dual-sided banks.
119 static const u16 translate_i82810_to_mb[] = {
120 /* DRP 0 1 (2) 3 4 5 6 7 8 9 A B C D E F */
121 /* MB */0, 8, 0, 16, 16, 24, 32, 32, 48, 64, 64, 96, 128, 128, 192, 256,
124 /* Size of bank#0 for dual-sided DIMMs */
125 static const u8 translate_i82810_to_bank[] = {
126 /* DRP 0 1 (2) 3 4 5 6 7 8 9 A B C D E F */
127 /* MB */0, 0, 0, 8, 0, 16, 16, 0, 32, 32, 0, 64, 64, 0, 128, 128,
131 u8 ds; /* dual-sided */
132 u8 ss; /* single-sided */
136 /*-----------------------------------------------------------------------------
137 SDRAM configuration functions.
138 -----------------------------------------------------------------------------*/
140 static inline int spd_read_byte(unsigned device, unsigned address)
142 return smbus_read_byte(device, address);
146 * Send the specified RAM command to all DIMMs.
148 * @param The RAM command to send to the DIMM(s).
150 static void do_ram_command(u8 command)
152 u32 addr, addr_offset;
153 u16 dimm_size, dimm_start, dimm_bank;
157 /* Configure the RAM command. */
158 reg8 = pci_read_config8(PCI_DEV(0, 0, 0), DRAMT);
159 reg8 &= 0x1f; /* Clear bits 7-5. */
160 reg8 |= command << 5;
161 pci_write_config8(PCI_DEV(0, 0, 0), DRAMT, reg8);
164 * RAM_COMMAND_NORMAL affects only the memory controller and
165 * doesn't need to be "sent" to the DIMMs.
167 if (command == RAM_COMMAND_NORMAL)
171 for (i = 0; i < DIMM_SOCKETS; i++) {
173 * Calculate the address offset where we need to "send" the
174 * DIMM command to. For most commands the offset is 0, only
175 * RAM_COMMAND_MRS needs special values, see below.
176 * The final address offset bits depend on three things:
178 * (1) Some hardcoded values specified in the datasheet.
179 * (2) Which CAS latency we will use/set. This is the SMAA[4]
180 * bit, which is 1 for CL3, and 0 for CL2. The bitstring
181 * so far has the form '00000001X1010', X being SMAA[4].
182 * (3) The DIMM to which we want to send the command. For
183 * DIMM0 no special handling is needed, but for DIMM1 we
184 * must invert the four bits SMAA[7:4] (see datasheet).
186 * Finally, the bitstring has to be shifted 3 bits to the left.
187 * See i810 datasheet pages 43, 85, and 86 for details.
190 caslatency = 3; /* TODO: Dynamically get CAS latency later. */
191 if (i == 0 && command == RAM_COMMAND_MRS && caslatency == 3)
192 addr_offset = 0x1d0; /* DIMM0, CL3, 0000111010000 */
193 if (i == 1 && command == RAM_COMMAND_MRS && caslatency == 3)
194 addr_offset = 0x650; /* DIMM1, CL3, 0011001010000 */
195 if (i == 0 && command == RAM_COMMAND_MRS && caslatency == 2)
196 addr_offset = 0x150; /* DIMM0, CL2, 0000101010000 */
197 if (i == 1 && command == RAM_COMMAND_MRS && caslatency == 2)
198 addr_offset = 0x1a0; /* DIMM1, CL2, 0000110100000 */
200 drp = pci_read_config8(PCI_DEV(0, 0, 0), DRP);
201 drp = (drp >> (i * 4)) & 0x0f;
203 dimm_size = translate_i82810_to_mb[drp];
205 addr = (dimm_start * 1024 * 1024) + addr_offset;
206 #if HAVE_ENOUGH_REGISTERS
207 PRINT_DEBUG(" Sending RAM command 0x");
208 PRINT_DEBUG_HEX8(reg8);
209 PRINT_DEBUG(" to 0x");
210 PRINT_DEBUG_HEX32(addr);
217 dimm_bank = translate_i82810_to_bank[drp];
219 addr = ((dimm_start + dimm_bank) * 1024 * 1024) + addr_offset;
220 #if HAVE_ENOUGH_REGISTERS
221 PRINT_DEBUG(" Sending RAM command 0x");
222 PRINT_DEBUG_HEX8(reg8);
223 PRINT_DEBUG(" to 0x");
224 PRINT_DEBUG_HEX32(addr);
230 dimm_start += dimm_size;
234 /*-----------------------------------------------------------------------------
235 DIMM-independant configuration functions.
236 -----------------------------------------------------------------------------*/
239 * Set DRP - DRAM Row Population Register (Device 0).
241 static void spd_set_dram_size(void)
243 /* The variables drp and dimm_size have to be ints since all the
244 * SMBus-related functions return ints, and its just easier this way.
246 int i, drp, dimm_size;
250 for (i = 0; i < DIMM_SOCKETS; i++) {
251 /* First check if a DIMM is actually present. */
252 if (smbus_read_byte(DIMM_SPD_BASE + i, 2) == 4) {
253 print_debug("Found DIMM in slot ");
257 dimm_size = smbus_read_byte(DIMM_SPD_BASE + i, 31);
259 /* WISHLIST: would be nice to display it as decimal? */
260 print_debug("DIMM is 0x");
261 print_debug_hex8(dimm_size * 4);
264 /* The i810 can't handle DIMMs larger than 128MB per
265 * side. This will fail if the DIMM uses a
266 * non-supported DRAM tech, and can't be used until
267 * buffers are done dynamically.
268 * Note: the factory BIOS just dies if it spots this :D
270 if (dimm_size > 32) {
271 print_err("DIMM row sizes larger than 128MB not"
272 "supported on i810\n");
274 ("Attempting to treat as 128MB DIMM\n");
278 /* This array is provided in raminit.h, because it got
279 * extremely messy. The above way is cleaner, but
280 * doesn't support any asymetrical/odd configurations.
282 dimm_size = translate_spd_to_i82810[dimm_size];
284 print_debug("After translation, dimm_size is 0x");
285 print_debug_hex8(dimm_size);
288 /* If the DIMM is dual-sided, the DRP value is +2 */
289 /* TODO: Figure out asymetrical configurations. */
290 if ((smbus_read_byte(DIMM_SPD_BASE + i, 127) | 0xf) ==
292 print_debug("DIMM is dual-sided\n");
296 print_debug("No DIMM found in slot ");
300 /* If there's no DIMM in the slot, set value to 0. */
304 /* Put in dimm_size to reflect the current DIMM. */
305 drp |= dimm_size << (i * 4);
308 print_debug("DRP calculated to 0x");
309 print_debug_hex8(drp);
312 pci_write_config8(PCI_DEV(0, 0, 0), DRP, drp);
315 static void set_dram_timing(void)
317 /* TODO, for now using default, hopefully safe values. */
318 // pci_write_config8(PCI_DEV(0, 0, 0), DRAMT, 0x00);
322 * TODO: BUFF_SC needs to be set according to the DRAM tech (x8, x16,
323 * or x32), but the datasheet doesn't list all the details. Currently, it
324 * needs to be pulled from the output of 'lspci -xxx Rx92'.
326 * Common results (tested on actual hardware) are:
328 * (DRP: c = 128MB dual sided, d = 128MB single sided, f = 256MB dual sided)
330 * BUFF_SC TOM DRP DIMM0 DIMM1
331 * ----------------------------------------------------------------------------
332 * 0x3356 128MB 0x0c 128MB dual-sided -
333 * 0xcc56 128MB 0xc0 - 128MB dual-sided
334 * 0x77da 128MB 0x0d 128MB single-sided -
335 * 0xddda 128MB 0xd0 - 128MB single-sided
336 * 0x0001 256MB 0xcc 128MB dual-sided 128MB dual-sided
337 * 0x55c6 256MB 0xdd 128MB single-sided 128MB single-sided
338 * 0x4445 256MB 0xcd 128MB single-sided 128MB dual-sided
339 * 0x1145 256MB 0xdc 128MB dual-sided 128MB single-sided
340 * 0x3356 256MB 0x0f 256MB dual-sided -
341 * 0xcc56 256MB 0xf0 - 256MB dual-sided
342 * 0x0001 384MB 0xcf 256MB dual-sided 128MB dual-sided
343 * 0x0001 384MB 0xfc 128MB dual-sided 256MB dual-sided
344 * 0x1145 384MB 0xdf 256MB dual-sided 128MB single-sided
345 * 0x4445 384MB 0xfd 128MB single-sided 256MB dual-sided
346 * 0x0001 512MB 0xff 256MB dual-sided 256MB dual-sided
349 * http://www.coreboot.org/pipermail/coreboot/2009-May/047966.html
351 static void set_dram_buffer_strength(void)
353 struct dimm_info d0, d1;
356 /* Check first slot. */
357 d0.size = d0.ds = d0.ss = 0;
358 if (smbus_read_byte(DIMM_SPD_BASE, SPD_MEMORY_TYPE)
359 == SPD_MEMORY_TYPE_SDRAM) {
360 d0.size = smbus_read_byte(DIMM_SPD_BASE, SPD_BANK_DENSITY);
361 d0.ds = smbus_read_byte(DIMM_SPD_BASE, SPD_NUM_DIMM_BANKS) > 1;
365 /* Check second slot. */
366 d1.size = d1.ds = d1.ss = 0;
367 if (smbus_read_byte(DIMM_SPD_BASE + 1, SPD_MEMORY_TYPE)
368 == SPD_MEMORY_TYPE_SDRAM) {
369 d1.size = smbus_read_byte(DIMM_SPD_BASE + 1, SPD_BANK_DENSITY);
370 d1.ds = smbus_read_byte(DIMM_SPD_BASE + 1,
371 SPD_NUM_DIMM_BANKS) > 1;
377 /* Tame the beast... */
378 if ((d0.ds && d1.ds) || (d0.ds && d1.ss) || (d0.ss && d1.ds))
380 if ((d0.size && !d1.size) || (!d0.size && d1.size) || (d0.ss && d1.ss))
382 if ((d0.ds && !d1.size) || (!d0.size && d1.ds) || (d0.ss && d1.ss)
383 || (d0.ds && d1.ss) || (d0.ss && d1.ds))
385 if ((d0.ss && !d1.size) || (!d0.size && d1.ss))
387 if ((d0.size && !d1.size) || (!d0.size && d1.size))
389 if ((d0.ds && !d1.size) || (!d0.size && d1.ds) || (d0.ds && d1.ss)
392 if ((d0.ss && !d1.size) || (!d0.size && d1.ss) || (d0.ss && d1.ss))
394 if ((!d0.size && d1.ss) || (d0.ds && d1.ss) || (d0.ss && d1.ss))
396 if (d0.size && !d1.size)
398 if ((d0.ss && !d1.size) || (d0.ss && d1.ss) || (d0.ss && d1.ds))
400 if (!d0.size && d1.size)
402 if ((d0.size && !d1.size) || (d0.ss && !d1.size) || (!d0.size && d1.ss)
403 || (d0.ss && d1.ss) || (d0.ds && d1.ss))
405 if (d0.size && !d1.size)
407 if ((!d0.size && d1.size) || (d0.ss && !d1.size) || (d0.ss && d1.ss)
410 if (!d0.size && d1.size)
413 print_debug("BUFF_SC calculated to 0x");
414 print_debug_hex16(buff_sc);
417 pci_write_config16(PCI_DEV(0, 0, 0), BUFF_SC, buff_sc);
420 /*-----------------------------------------------------------------------------
422 -----------------------------------------------------------------------------*/
424 static void sdram_set_registers(void)
429 did = pci_read_config16(PCI_DEV(0, 0, 0), PCI_DEVICE_ID);
431 /* Ideally, this should be R/W for as many ranges as possible. */
432 pci_write_config8(PCI_DEV(0, 0, 0), PAMR, 0xff);
434 /* Set size for onboard-VGA framebuffer. */
435 reg8 = pci_read_config8(PCI_DEV(0, 0, 0), SMRAM);
436 reg8 &= 0x3f; /* Disable graphics (for now). */
438 if (CONFIG_VIDEO_MB == 512)
439 reg8 |= (1 << 7); /* Enable graphics (512KB RAM). */
440 else if (CONFIG_VIDEO_MB == 1)
441 reg8 |= (1 << 7) | (1 << 6); /* Enable graphics (1MB RAM). */
443 pci_write_config8(PCI_DEV(0, 0, 0), SMRAM, reg8);
445 /* MISSC2: Bits 1, 2, 6, 7 must be set for VGA (see datasheet). */
446 reg8 = pci_read_config8(PCI_DEV(0, 0, 0), MISSC2);
447 reg8 |= (1 << 1); /* Instruction Parser Unit-Level Clock Gating */
448 reg8 |= (1 << 2); /* Palette Load Select */
450 /* Bits 6 and 7 are only available on 82810E (not 82810). */
451 reg8 |= (1 << 6); /* Text Immediate Blit */
452 reg8 |= (1 << 7); /* Must be 1 as per datasheet. */
454 pci_write_config8(PCI_DEV(0, 0, 0), MISSC2, reg8);
457 static void sdram_set_spd_registers(void)
460 set_dram_buffer_strength();
467 static void sdram_enable(void)
472 PRINT_DEBUG("RAM Enable 1: Apply NOP\n");
473 do_ram_command(RAM_COMMAND_NOP);
476 /* 2. Precharge all. Wait tRP. */
477 PRINT_DEBUG("RAM Enable 2: Precharge all\n");
478 do_ram_command(RAM_COMMAND_PRECHARGE);
481 /* 3. Perform 8 refresh cycles. Wait tRC each time. */
482 PRINT_DEBUG("RAM Enable 3: CBR\n");
483 for (i = 0; i < 8; i++) {
484 do_ram_command(RAM_COMMAND_CBR);
488 /* 4. Mode register set. Wait two memory cycles. */
489 PRINT_DEBUG("RAM Enable 4: Mode register set\n");
490 do_ram_command(RAM_COMMAND_MRS);
493 /* 5. Normal operation (enables refresh at 15.6usec). */
494 PRINT_DEBUG("RAM Enable 5: Normal operation\n");
495 do_ram_command(RAM_COMMAND_NORMAL);
498 PRINT_DEBUG("Northbridge following SDRAM init:\n");