2 * This file is part of the LinuxBIOS project.
4 * Copyright (C) 2007 Corey Osgood <corey@slightlyhackish.com>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #include <console/console.h>
24 #include <device/device.h>
25 #include <device/pci.h>
26 #include <device/pci_ids.h>
31 #include "northbridge.h"
34 static void northbridge_init(device_t dev)
36 printk_spew("Northbridge init\n");
39 static struct device_operations northbridge_operations = {
40 .read_resources = pci_dev_read_resources,
41 .set_resources = pci_dev_set_resources,
42 .enable_resources = pci_dev_enable_resources,
43 .init = northbridge_init,
48 static struct pci_driver northbridge_driver __pci_driver = {
49 .ops = &northbridge_operations,
50 .vendor = PCI_VENDOR_ID_INTEL,
54 #define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM)
56 static void pci_domain_read_resources(device_t dev)
58 struct resource *resource;
61 /* Initialize the system wide io space constraints */
62 resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
63 resource->base = 0x400;
64 resource->limit = 0xffffUL;
65 resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
67 /* Initialize the system wide memory resources constraints */
68 resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
69 resource->limit = 0xffffffffULL;
70 resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
73 static void ram_resource(device_t dev, unsigned long index,
74 unsigned long basek, unsigned long sizek)
76 struct resource *resource;
81 resource = new_resource(dev, index);
82 resource->base = ((resource_t)basek) << 10;
83 resource->size = ((resource_t)sizek) << 10;
84 resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
85 IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
88 static void tolm_test(void *gp, struct device *dev, struct resource *new)
90 struct resource **best_p = gp;
91 struct resource *best;
93 if (!best || (best->base > new->base)) {
99 static uint32_t find_pci_tolm(struct bus *bus)
101 struct resource *min;
104 search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min);
106 if (min && tolm > min->base) {
112 /* Table which returns the RAM size in MB when fed the DRP[7:4] or [3:0] value.
113 * Note that 2 is a value which the DRP should never be programmed to.
114 * Some size values appear twice, due to single-sided vs dual-sided banks.
116 static int translate_i82810_to_mb[] = {
117 /* DRP 0 1 (2) 3 4 5 6 7 8 9 A B C D E F */
118 /* MB */0, 8, 0, 16, 16, 24, 32, 32, 48, 64, 64, 96, 128, 128, 192, 256,
121 static void pci_domain_set_resources(device_t dev)
126 pci_tolm = find_pci_tolm(&dev->link[0]);
127 mc_dev = dev->link[0].children;
130 /* Figure out which areas are/should be occupied by RAM.
131 * This is all computed in kilobytes and converted to/from
132 * the memory controller right at the edges.
133 * Having different variables in different units is
134 * too confusing to get right. Kilobytes are good up to
135 * 4 Terabytes of RAM...
137 unsigned long tomk, tolmk;
141 /* First get the value for DIMM 0. */
142 drp_value = pci_read_config8(mc_dev, DRP);
143 /* Translate it to MB and add to tomk. */
144 tomk = (unsigned long)(translate_i82810_to_mb[drp_value & 0xf]);
145 /* Now do the same for DIMM 1. */
146 drp_value = drp_value >> 4; // >>= 4; //? mess with later
147 tomk += (unsigned long)(translate_i82810_to_mb[drp_value]);
149 printk_debug("Setting RAM size to %d MB\n", tomk);
151 /* Convert tomk from MB to KB. */
154 /* Compute the top of Low memory. */
155 tolmk = pci_tolm >> 10;
157 /* The PCI hole does does not overlap the memory. */
161 /* Report the memory regions. */
163 ram_resource(dev, idx++, 0, 640);
164 ram_resource(dev, idx++, 1024, tolmk - 1024);
166 assign_resources(&dev->link[0]);
169 static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
171 max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
175 static struct device_operations pci_domain_ops = {
176 .read_resources = pci_domain_read_resources,
177 .set_resources = pci_domain_set_resources,
178 .enable_resources = enable_childrens_resources,
180 .scan_bus = pci_domain_scan_bus,
183 static void cpu_bus_init(device_t dev)
185 initialize_cpus(&dev->link[0]);
188 static void cpu_bus_noop(device_t dev)
192 static struct device_operations cpu_bus_ops = {
193 .read_resources = cpu_bus_noop,
194 .set_resources = cpu_bus_noop,
195 .enable_resources = cpu_bus_noop,
196 .init = cpu_bus_init,
200 static void enable_dev(struct device *dev)
202 struct device_path path;
204 /* Set the operations if it is a special bus type */
205 if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
206 dev->ops = &pci_domain_ops;
209 else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
210 dev->ops = &cpu_bus_ops;
214 struct chip_operations northbridge_intel_i82810_ops = {
215 CHIP_NAME("Intel 82810 Northbridge")
216 .enable_dev = enable_dev,