2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 Corey Osgood <corey@slightlyhackish.com>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #include <console/console.h>
24 #include <device/device.h>
25 #include <device/pci.h>
26 #include <device/pci_ids.h>
32 #include "northbridge.h"
35 static void northbridge_init(device_t dev)
37 printk(BIOS_SPEW, "Northbridge init\n");
40 static struct device_operations northbridge_operations = {
41 .read_resources = pci_dev_read_resources,
42 .set_resources = pci_dev_set_resources,
43 .enable_resources = pci_dev_enable_resources,
44 .init = northbridge_init,
49 /* Intel 82810/82810-DC100 */
50 static const struct pci_driver i810_northbridge_driver __pci_driver = {
51 .ops = &northbridge_operations,
52 .vendor = PCI_VENDOR_ID_INTEL,
57 static const struct pci_driver i810e_northbridge_driver __pci_driver = {
58 .ops = &northbridge_operations,
59 .vendor = PCI_VENDOR_ID_INTEL,
63 static void ram_resource(device_t dev, unsigned long index,
64 unsigned long basek, unsigned long sizek)
66 struct resource *resource;
71 resource = new_resource(dev, index);
72 resource->base = ((resource_t) basek) << 10;
73 resource->size = ((resource_t) sizek) << 10;
74 resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE |
75 IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
78 static void tolm_test(void *gp, struct device *dev, struct resource *new)
80 struct resource **best_p = gp;
81 struct resource *best;
83 if (!best || (best->base > new->base)) {
89 static uint32_t find_pci_tolm(struct bus *bus)
94 search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test,
97 if (min && tolm > min->base) {
103 /* Table which returns the RAM size in MB when fed the DRP[7:4] or [3:0] value.
104 * Note that 2 is a value which the DRP should never be programmed to.
105 * Some size values appear twice, due to single-sided vs dual-sided banks.
107 static int translate_i82810_to_mb[] = {
108 /* DRP 0 1 (2) 3 4 5 6 7 8 9 A B C D E F */
109 /* MB */0, 8, 0, 16, 16, 24, 32, 32, 48, 64, 64, 96, 128, 128, 192, 256,
112 #if CONFIG_WRITE_HIGH_TABLES==1
113 #define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB
114 extern uint64_t high_tables_base, high_tables_size;
117 static void pci_domain_set_resources(device_t dev)
122 pci_tolm = find_pci_tolm(&dev->link[0]);
123 mc_dev = dev->link[0].children;
126 /* Figure out which areas are/should be occupied by RAM.
127 * This is all computed in kilobytes and converted to/from
128 * the memory controller right at the edges.
129 * Having different variables in different units is
130 * too confusing to get right. Kilobytes are good up to
131 * 4 Terabytes of RAM...
133 unsigned long tomk, tolmk;
137 /* First get the value for DIMM 0. */
138 drp_value = pci_read_config8(mc_dev, DRP);
139 /* Translate it to MB and add to tomk. */
140 tomk = (unsigned long)(translate_i82810_to_mb[drp_value & 0xf]);
141 /* Now do the same for DIMM 1. */
142 drp_value = drp_value >> 4; // >>= 4; //? mess with later
143 tomk += (unsigned long)(translate_i82810_to_mb[drp_value]);
145 printk(BIOS_DEBUG, "Setting RAM size to %ld MB\n", tomk);
147 /* Convert tomk from MB to KB. */
151 /* Check for VGA reserved memory. */
152 if (CONFIG_VIDEO_MB == 512) {
154 printk(BIOS_DEBUG, "Allocating %s RAM for VGA\n", "512KB");
155 } else if (CONFIG_VIDEO_MB == 1) {
157 printk(BIOS_DEBUG, "Allocating %s RAM for VGA\n", "1MB");
159 printk(BIOS_DEBUG, "Allocating %s RAM for VGA\n", "0MB");
163 /* Compute the top of Low memory. */
164 tolmk = pci_tolm >> 10;
166 /* The PCI hole does does not overlap the memory. */
170 /* Report the memory regions. */
172 ram_resource(dev, idx++, 0, 640);
173 ram_resource(dev, idx++, 768, tolmk - 768);
175 #if CONFIG_WRITE_HIGH_TABLES==1
176 /* Leave some space for ACPI, PIRQ and MP tables */
177 high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024;
178 high_tables_size = HIGH_TABLES_SIZE * 1024;
181 assign_resources(&dev->link[0]);
184 static struct device_operations pci_domain_ops = {
185 .read_resources = pci_domain_read_resources,
186 .set_resources = pci_domain_set_resources,
187 .enable_resources = enable_childrens_resources,
189 .scan_bus = pci_domain_scan_bus,
192 static void cpu_bus_init(device_t dev)
194 initialize_cpus(&dev->link[0]);
197 static void cpu_bus_noop(device_t dev)
201 static struct device_operations cpu_bus_ops = {
202 .read_resources = cpu_bus_noop,
203 .set_resources = cpu_bus_noop,
204 .enable_resources = cpu_bus_noop,
205 .init = cpu_bus_init,
209 static void enable_dev(struct device *dev)
211 /* Set the operations if it is a special bus type */
212 if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
213 dev->ops = &pci_domain_ops;
215 } else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
216 dev->ops = &cpu_bus_ops;
220 struct chip_operations northbridge_intel_i82810_ops = {
221 CHIP_NAME("Intel 82810 Northbridge")
222 .enable_dev = enable_dev,