2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 Corey Osgood <corey.osgood@gmail.com>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
23 * - Name: Intel 810 Chipset:
24 * 82810/82810-DC100 Graphics and Memory Controller Hub (GMCH)
25 * - URL: http://www.intel.com/design/chipsets/datashts/290656.htm
26 * - PDF: ftp://download.intel.com/design/chipsets/datashts/29065602.pdf
27 * - Order Number: 290656-002
31 * PCI Configuration Registers.
33 * Any addresses between 0x50 and 0xff not listed below are reserved and
34 * should not be touched.
37 #define GMCHCFG 0x50 /* GMCH Configuration */
38 #define PAMR 0x51 /* Programmable Attributes */
39 #define DRP 0x52 /* DRAM Row Population */
40 #define DRAMT 0x53 /* DRAM Timing */
41 #define FDHC 0x58 /* Fixed DRAM Hole Control */
42 #define SMRAM 0x70 /* System Management RAM Control */
43 #define MISSC 0x72 /* Miscellaneous Control */
44 #define MISSC2 0x80 /* Miscellaneous Control 2 */
45 #define BUFF_SC 0x92 /* System Memory Buffer Strength Control */