2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
5 * Copyright (C) 2009 Maciej Pijanka <maciej.pijanka@gmail.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 #include <console/console.h>
25 #include <device/device.h>
26 #include <device/pci.h>
27 #include <device/pci_ids.h>
32 #include <pc80/keyboard.h>
34 #include "northbridge.h"
37 /* This code is mostly same as 440BX created by Uwe Hermann,
38 * i done only very minor changes like renamed functions to 440lx etc
43 * - maybe this could print Northbridge i440LX Init?
45 static void northbridge_init(device_t dev)
47 printk(BIOS_SPEW, "Northbridge Init\n");
50 static struct device_operations northbridge_operations = {
51 .read_resources = pci_dev_read_resources,
52 .set_resources = pci_dev_set_resources,
53 .enable_resources = pci_dev_enable_resources,
54 .init = northbridge_init,
59 static const struct pci_driver northbridge_driver __pci_driver = {
60 .ops = &northbridge_operations,
61 .vendor = PCI_VENDOR_ID_INTEL,
65 #if CONFIG_WRITE_HIGH_TABLES==1
69 static void i440lx_domain_set_resources(device_t dev)
74 pci_tolm = find_pci_tolm(dev->link_list);
75 mc_dev = dev->link_list->children;
77 unsigned long tomk, tolmk;
80 /* Figure out which areas are/should be occupied by RAM. The
81 * value of the highest DRB denotes the end of the physical
82 * memory (in units of 8MB).
84 tomk = ((unsigned long)pci_read_config8(mc_dev, DRB7));
89 printk(BIOS_DEBUG, "Setting RAM size to %lu MB\n", tomk / 1024);
91 /* Compute the top of low memory. */
92 tolmk = pci_tolm / 1024;
95 /* The PCI hole does not overlap the memory. */
99 /* Report the memory regions. */
101 ram_resource(dev, idx++, 0, 640);
102 ram_resource(dev, idx++, 768, tolmk - 768);
104 #if CONFIG_WRITE_HIGH_TABLES==1
105 /* Leave some space for ACPI, PIRQ and MP tables */
106 high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE;
107 high_tables_size = HIGH_MEMORY_SIZE;
110 assign_resources(dev->link_list);
113 static struct device_operations pci_domain_ops = {
114 .read_resources = pci_domain_read_resources,
115 .set_resources = i440lx_domain_set_resources,
116 .enable_resources = NULL,
118 .scan_bus = pci_domain_scan_bus,
121 static void cpu_bus_init(device_t dev)
123 initialize_cpus(dev->link_list);
126 static void cpu_bus_noop(device_t dev)
130 static struct device_operations cpu_bus_ops = {
131 .read_resources = cpu_bus_noop,
132 .set_resources = cpu_bus_noop,
133 .enable_resources = cpu_bus_noop,
134 .init = cpu_bus_init,
138 static void enable_dev(struct device *dev)
140 /* Set the operations if it is a special bus type */
141 if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
142 dev->ops = &pci_domain_ops;
145 else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
146 dev->ops = &cpu_bus_ops;
150 struct chip_operations northbridge_intel_i440lx_ops = {
151 CHIP_NAME("Intel 82443LX (440LX) Northbridge")
152 .enable_dev = enable_dev,