src/northbridge/intel/i440bx/northbridge.c

   1 #include <console/console.h>
   2 #include <arch/io.h>
   3 #include <stdint.h>
   4 #include <device/device.h>
   5 #include <device/pci.h>
   6 #include <device/pci_ids.h>
   7 #include <stdlib.h>
   8 #include <string.h>
   9 #include <bitops.h>
  10 #include "chip.h"
  11 #include "northbridge.h"
  12
  13 /*
  14 */
  15 static void northbridge_init(device_t dev)
  16 {
  17         printk_spew("Northbridge Init\n");
  18 }
  19
  20
  21 static struct device_operations northbridge_operations = {
  22         .read_resources   = pci_dev_read_resources,
  23         .set_resources    = pci_dev_set_resources,
  24         .enable_resources = pci_dev_enable_resources,
  25         .init             = northbridge_init,
  26         .enable           = 0,
  27         .ops_pci          = 0,
  28 };
  29
  30 static struct pci_driver northbridge_driver __pci_driver = {
  31         .ops = &northbridge_operations,
  32         .vendor = PCI_VENDOR_ID_INTEL,
  33         .device = 0x7190,
  34 };
  35
  36
  37
  38 #define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM)
  39
  40 static void pci_domain_read_resources(device_t dev)
  41 {
  42         struct resource *resource;
  43
  44         /* Initialize the system wide io space constraints */
  45         resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0));
  46         resource->limit = 0xffffUL;
  47         resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
  48
  49         /* Initialize the system wide memory resources constraints */
  50         resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0));
  51         resource->limit = 0xffffffffULL;
  52         resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
  53 }
  54
  55 static void ram_resource(device_t dev, unsigned long index,
  56         unsigned long basek, unsigned long sizek)
  57 {
  58         struct resource *resource;
  59
  60         if (!sizek) {
  61                 return;
  62         }
  63         resource = new_resource(dev, index);
  64         resource->base  = ((resource_t)basek) << 10;
  65         resource->size  = ((resource_t)sizek) << 10;
  66         resource->flags =  IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
  67                 IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
  68 }
  69
  70 static void tolm_test(void *gp, struct device *dev, struct resource *new)
  71 {
  72         struct resource **best_p = gp;
  73         struct resource *best;
  74         best = *best_p;
  75         if (!best || (best->base > new->base)) {
  76                 best = new;
  77         }
  78         *best_p = best;
  79 }
  80
  81 static uint32_t find_pci_tolm(struct bus *bus)
  82 {
  83         struct resource *min;
  84         uint32_t tolm;
  85         min = 0;
  86         search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min);
  87         tolm = 0xffffffffUL;
  88         if (min && tolm > min->base) {
  89                 tolm = min->base;
  90         }
  91         return tolm;
  92 }
  93
  94 static void pci_domain_set_resources(device_t dev)
  95 {
  96         static const uint8_t ramregs[] = {
  97                 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f, 0x56, 0x57
  98         };
  99         device_t mc_dev;
 100         uint32_t pci_tolm;
 101
 102         pci_tolm = find_pci_tolm(&dev->link[0]);
 103         mc_dev = dev->link[0].children;
 104         if (mc_dev) {
 105                 unsigned long tomk, tolmk;
 106                 unsigned char rambits;
 107                 int i, idx;
 108
 109                 for(rambits = 0, i = 0; i < sizeof(ramregs)/sizeof(ramregs[0]); i++) {
 110                         unsigned char reg;
 111                         reg = pci_read_config8(mc_dev, ramregs[i]);
 112                         /* these are ENDING addresses, not sizes.
 113                          * if there is memory in this slot, then reg will be > rambits.
 114                          * So we just take the max, that gives us total.
 115                          * We take the highest one to cover for once and future linuxbios
 116                          * bugs. We warn about bugs.
 117                          */
 118                         if (reg > rambits)
 119                                 rambits = reg;
 120                         if (reg < rambits)
 121                                 printk_err("ERROR! register 0x%x is not set!\n",
 122                                         ramregs[i]);
 123                 }
 124                 printk_debug("I would set ram size to 0x%x Kbytes\n", (rambits)*8*1024);
 125                 tomk = rambits*8*1024;
 126                 /* Compute the top of Low memory */
 127                 tolmk = pci_tolm >> 10;
 128                 if (tolmk >= tomk) {
 129                         /* The PCI hole does does not overlap the memory.
 130                          */
 131                         tolmk = tomk;
 132                 }
 133                 /* Report the memory regions */
 134                 idx = 10;
 135                 ram_resource(dev, idx++, 0, tolmk);
 136         }
 137         assign_resources(&dev->link[0]);
 138 }
 139
 140 static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
 141 {
 142         max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
 143         return max;
 144 }
 145
 146 static struct device_operations pci_domain_ops = {
 147         .read_resources   = pci_domain_read_resources,
 148         .set_resources    = pci_domain_set_resources,
 149         .enable_resources = enable_childrens_resources,
 150         .init             = 0,
 151         .scan_bus         = pci_domain_scan_bus,
 152 };
 153
 154 static void cpu_bus_init(device_t dev)
 155 {
 156         initialize_cpus(&dev->link[0]);
 157 }
 158
 159 static void cpu_bus_noop(device_t dev)
 160 {
 161 }
 162
 163 static struct device_operations cpu_bus_ops = {
 164         .read_resources   = cpu_bus_noop,
 165         .set_resources    = cpu_bus_noop,
 166         .enable_resources = cpu_bus_noop,
 167         .init             = cpu_bus_init,
 168         .scan_bus         = 0,
 169 };
 170
 171 static void enable_dev(struct device *dev)
 172 {
 173         /* Set the operations if it is a special bus type */
 174         if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
 175                 dev->ops = &pci_domain_ops;
 176                 pci_set_method(dev);
 177         }
 178         else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
 179                 dev->ops = &cpu_bus_ops;
 180         }
 181 }
 182
 183 struct chip_operations northbridge_intel_i440bx_ops = {
 184         CHIP_NAME("Intel 440bx Northbridge")
 185         .enable_dev = enable_dev,
 186 };