src/northbridge/intel/i440bx/northbridge.c

   1 #include <console/console.h>
   2 #include <arch/io.h>
   3 #include <stdint.h>
   4 #include <device/device.h>
   5 #include <device/pci.h>
   6 #include <device/pci_ids.h>
   7 #include <stdlib.h>
   8 #include <string.h>
   9 #include <bitops.h>
  10 #include "chip.h"
  11 #include "northbridge.h"
  12 #include "i440bx.h"
  13
  14 static void northbridge_init(device_t dev)
  15 {
  16         printk_spew("Northbridge Init\n");
  17 }
  18
  19 static struct device_operations northbridge_operations = {
  20         .read_resources   = pci_dev_read_resources,
  21         .set_resources    = pci_dev_set_resources,
  22         .enable_resources = pci_dev_enable_resources,
  23         .init             = northbridge_init,
  24         .enable           = 0,
  25         .ops_pci          = 0,
  26 };
  27
  28 static struct pci_driver northbridge_driver __pci_driver = {
  29         .ops = &northbridge_operations,
  30         .vendor = PCI_VENDOR_ID_INTEL,
  31         .device = 0x7190,
  32 };
  33
  34
  35 #define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM)
  36
  37 static void pci_domain_read_resources(device_t dev)
  38 {
  39         struct resource *resource;
  40         unsigned reg;
  41
  42         /* Initialize the system wide io space constraints */
  43         resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
  44         resource->limit = 0xffffUL;
  45         resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
  46
  47         /* Initialize the system wide memory resources constraints */
  48         resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
  49         resource->limit = 0xffffffffULL;
  50         resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
  51 }
  52
  53 static void ram_resource(device_t dev, unsigned long index,
  54         unsigned long basek, unsigned long sizek)
  55 {
  56         struct resource *resource;
  57
  58         if (!sizek) {
  59                 return;
  60         }
  61         resource = new_resource(dev, index);
  62         resource->base  = ((resource_t)basek) << 10;
  63         resource->size  = ((resource_t)sizek) << 10;
  64         resource->flags =  IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
  65                 IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
  66 }
  67
  68 static void tolm_test(void *gp, struct device *dev, struct resource *new)
  69 {
  70         struct resource **best_p = gp;
  71         struct resource *best;
  72         best = *best_p;
  73         if (!best || (best->base > new->base)) {
  74                 best = new;
  75         }
  76         *best_p = best;
  77 }
  78
  79 static uint32_t find_pci_tolm(struct bus *bus)
  80 {
  81         struct resource *min;
  82         uint32_t tolm;
  83         min = 0;
  84         search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min);
  85         tolm = 0xffffffffUL;
  86         if (min && tolm > min->base) {
  87                 tolm = min->base;
  88         }
  89         return tolm;
  90 }
  91
  92 static void pci_domain_set_resources(device_t dev)
  93 {
  94         device_t mc_dev;
  95         uint32_t pci_tolm;
  96
  97         pci_tolm = find_pci_tolm(&dev->link[0]);
  98         mc_dev = dev->link[0].children;
  99
 100         if (mc_dev) {
 101                 uint16_t tolm_r;
 102                 unsigned long tomk, tolmk;
 103                 int idx;
 104
 105                 /* Figure out which areas are/should be occupied by RAM. The
 106                  * value of the highest DRB denotes the end of the physical
 107                  * memory (in units of 8MB).
 108                  */
 109                 tomk = ((unsigned long)pci_read_config8(mc_dev, DRB7));
 110
 111                 /* Convert to KB. */
 112                 tomk *= (8 * 1024);
 113
 114                 printk_debug("Setting RAM size to %d MB\n", tomk / 1024);
 115
 116                 /* Compute the top of low memory. */
 117                 tolmk = pci_tolm / 1024;
 118
 119                 if (tolmk >= tomk) {
 120                         /* The PCI hole does does not overlap the memory. */
 121                         tolmk = tomk;
 122                 }
 123
 124                 /* Report the memory regions. */
 125                 idx = 10;
 126                 ram_resource(dev, idx++, 0, 640);
 127                 ram_resource(dev, idx++, 768, tolmk - 768);
 128         }
 129
 130         assign_resources(&dev->link[0]);
 131 }
 132
 133 static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
 134 {
 135         max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
 136         return max;
 137 }
 138
 139 static struct device_operations pci_domain_ops = {
 140         .read_resources   = pci_domain_read_resources,
 141         .set_resources    = pci_domain_set_resources,
 142         .enable_resources = enable_childrens_resources,
 143         .init             = 0,
 144         .scan_bus         = pci_domain_scan_bus,
 145 };
 146
 147 static void cpu_bus_init(device_t dev)
 148 {
 149         initialize_cpus(&dev->link[0]);
 150 }
 151
 152 static void cpu_bus_noop(device_t dev)
 153 {
 154 }
 155
 156 static struct device_operations cpu_bus_ops = {
 157         .read_resources   = cpu_bus_noop,
 158         .set_resources    = cpu_bus_noop,
 159         .enable_resources = cpu_bus_noop,
 160         .init             = cpu_bus_init,
 161         .scan_bus         = 0,
 162 };
 163
 164 static void enable_dev(struct device *dev)
 165 {
 166         struct device_path path;
 167
 168         /* Set the operations if it is a special bus type */
 169         if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
 170                 dev->ops = &pci_domain_ops;
 171                 pci_set_method(dev);
 172         }
 173         else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
 174                 dev->ops = &cpu_bus_ops;
 175         }
 176 }
 177
 178 struct chip_operations northbridge_intel_i440bx_ops = {
 179         CHIP_NAME("Intel 82443BX (440BX) Northbridge")
 180         .enable_dev = enable_dev,
 181 };