2 * This file is part of the coreboot project.
4 * Copyright (C) 2005 Eric W. Biederman and Tom Zimmerman
5 * Copyright (C) 2008 Arastra, Inc.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 #include <cpu/x86/mtrr.h>
23 #include <cpu/x86/cache.h>
28 /* DDR2 memory controller register space */
29 #define MCBAR 0x90000000
31 static void sdram_set_registers(const struct mem_controller *ctrl)
33 static const u32 register_values[] = {
35 /* CKDIS 0x8c disable clocks */
36 PCI_ADDR(0, 0x00, 0, CKDIS), 0xffff0000, 0x0000ffff,
38 /* 0x9c Device present and extended RAM control
39 * DEVPRES is very touchy, hard code the initialization
40 * of PCI-E ports here.
42 PCI_ADDR(0, 0x00, 0, DEVPRES), 0x00000000, 0x07020801 | DEVPRES_CONFIG,
44 /* 0xc8 Remap RAM base and limit off */
45 PCI_ADDR(0, 0x00, 0, REMAPLIMIT), 0x00000000, 0x03df0000,
48 PCI_ADDR(0, 0x00, 0, 0xd8), 0x00000000, 0xb5930000,
49 PCI_ADDR(0, 0x00, 0, 0xe8), 0x00000000, 0x00004a2a,
52 PCI_ADDR(0, 0x00, 0, MCHCFG0), 0xfce0ffff, 0x00006000, /* 6000 */
55 PCI_ADDR(0, 0x00, 0, PAM-1), 0xcccccc7f, 0x33333000,
56 PCI_ADDR(0, 0x00, 0, PAM+3), 0xcccccccc, 0x33333333,
59 PCI_ADDR(0, 0x00, 0, DEVPRES1), 0xffbffff, (1<<22)|(6<<2) | DEVPRES1_CONFIG,
62 PCI_ADDR(0, 0x00, 0, IURBASE), 0x00000fff, MCBAR |0,
67 max = ARRAY_SIZE(register_values);
68 for(i = 0; i < max; i += 3) {
72 dev = (register_values[i] & ~0xff) - PCI_DEV(0, 0x00, 0) + ctrl->f0;
73 where = register_values[i] & 0xff;
74 reg = pci_read_config32(dev, where);
75 reg &= register_values[i+1];
76 reg |= register_values[i+2];
77 pci_write_config32(dev, where, reg);
79 print_spew("done.\n");
87 static struct dimm_size spd_get_dimm_size(u16 device)
89 /* Calculate the log base 2 size of a DIMM in bits */
95 /* Note it might be easier to use byte 31 here, it has the DIMM size as
96 * a multiple of 4MB. The way we do it now we can size both
97 * sides of an assymetric dimm.
99 value = spd_read_byte(device, 3); /* rows */
100 if (value < 0) goto hw_err;
101 if ((value & 0xf) == 0) goto val_err;
102 sz.side1 += value & 0xf;
104 value = spd_read_byte(device, 4); /* columns */
105 if (value < 0) goto hw_err;
106 if ((value & 0xf) == 0) goto val_err;
107 sz.side1 += value & 0xf;
109 value = spd_read_byte(device, 17); /* banks */
110 if (value < 0) goto hw_err;
111 if ((value & 0xff) == 0) goto val_err;
112 sz.side1 += log2(value & 0xff);
114 /* Get the module data width and convert it to a power of two */
115 value = spd_read_byte(device, 7); /* (high byte) */
116 if (value < 0) goto hw_err;
120 low = spd_read_byte(device, 6); /* (low byte) */
121 if (low < 0) goto hw_err;
122 value = value | (low & 0xff);
123 if ((value != 72) && (value != 64)) goto val_err;
124 sz.side1 += log2(value);
127 value = spd_read_byte(device, 5); /* number of physical banks */
129 if (value < 0) goto hw_err;
132 if (value == 1) goto out;
133 if (value != 2) goto val_err;
135 /* Start with the symmetrical case */
138 value = spd_read_byte(device, 3); /* rows */
139 if (value < 0) goto hw_err;
140 if ((value & 0xf0) == 0) goto out; /* If symmetrical we are done */
141 sz.side2 -= (value & 0x0f); /* Subtract out rows on side 1 */
142 sz.side2 += ((value >> 4) & 0x0f); /* Add in rows on side 2 */
144 value = spd_read_byte(device, 4); /* columns */
145 if (value < 0) goto hw_err;
146 if ((value & 0xff) == 0) goto val_err;
147 sz.side2 -= (value & 0x0f); /* Subtract out columns on side 1 */
148 sz.side2 += ((value >> 4) & 0x0f); /* Add in columns on side 2 */
152 die("Bad SPD value\n");
153 /* If an hw_error occurs report that I have no memory */
162 static long spd_set_ram_size(const struct mem_controller *ctrl, long dimm_mask)
167 for(i = cum = 0; i < DIMM_SOCKETS; i++) {
169 if (dimm_mask & (1 << i)) {
170 sz = spd_get_dimm_size(ctrl->channel0[i]);
172 return -1; /* Report SPD error */
174 /* convert bits to multiples of 64MB */
176 cum += (1 << sz.side1);
178 pci_write_config8(ctrl->f0, DRB + (i*2), cum);
181 cum += (1 << sz.side2);
183 pci_write_config8(ctrl->f0, DRB+1 + (i*2), cum);
186 pci_write_config8(ctrl->f0, DRB + (i*2), cum);
187 pci_write_config8(ctrl->f0, DRB+1 + (i*2), cum);
191 /* set TOM top of memory 0xcc */
192 pci_write_config16(ctrl->f0, TOM, cum);
193 /* set TOLM top of low memory */
199 pci_write_config16(ctrl->f0, TOLM, cum);
204 static u32 spd_detect_dimms(const struct mem_controller *ctrl)
209 for(i = 0; i < DIMM_SOCKETS; i++) {
212 device = ctrl->channel0[i];
214 byte = spd_read_byte(device, 2); /* Type */
216 dimm_mask |= (1 << i);
219 device = ctrl->channel1[i];
221 byte = spd_read_byte(device, 2);
223 dimm_mask |= (1 << (i + DIMM_SOCKETS));
231 static int spd_set_row_attributes(const struct mem_controller *ctrl,
240 for(cnt=0; cnt < 4; cnt++) {
241 if (!(dimm_mask & (1 << cnt))) {
245 value = spd_read_byte(ctrl->channel0[cnt], 3); /* rows */
246 if (value < 0) goto hw_err;
247 if ((value & 0xf) == 0) goto val_err;
250 value = spd_read_byte(ctrl->channel0[cnt], 4); /* columns */
251 if (value < 0) goto hw_err;
252 if ((value & 0xf) == 0) goto val_err;
255 value = spd_read_byte(ctrl->channel0[cnt], 17); /* banks */
256 if (value < 0) goto hw_err;
257 if ((value & 0xff) == 0) goto val_err;
258 reg += log2(value & 0xff);
260 /* Get the device width and convert it to a power of two */
261 value = spd_read_byte(ctrl->channel0[cnt], 13);
262 if (value < 0) goto hw_err;
263 value = log2(value & 0xff);
265 if(reg < 27) goto hw_err;
269 dra += reg << (cnt*8);
270 value = spd_read_byte(ctrl->channel0[cnt], 5);
272 dra += reg << ((cnt*8)+4);
276 pci_write_config32(ctrl->f0, DRA, dra);
280 die("Bad SPD value\n");
281 /* If an hw_error occurs report that I have no memory */
290 static int spd_set_drt_attributes(const struct mem_controller *ctrl,
291 long dimm_mask, u32 drc)
302 static const u8 cycle_time[3] = { 0x75, 0x60, 0x50 };
303 static const u8 latency_indicies[] = { 26, 23, 9 };
306 drt = pci_read_config32(ctrl->f0, DRT);
307 drt &= 3; /* save bits 1:0 */
309 for(first_dimm = 0; first_dimm < 4; first_dimm++) {
310 if (dimm_mask & (1 << first_dimm))
314 drt |= (1<<6); /* back to back write turn around */
316 drt |= (3<<18); /* Trasmax */
318 for(cnt=0; cnt < 4; cnt++) {
319 if (!(dimm_mask & (1 << cnt))) {
322 reg = spd_read_byte(ctrl->channel0[cnt], 18); /* CAS Latency */
323 /* Compute the lowest cas latency supported */
324 latency = log2(reg) -2;
326 /* Loop through and find a fast clock with a low latency */
327 for(index = 0; index < 3; index++, latency++) {
328 if ((latency < 2) || (latency > 4) ||
329 (!(reg & (1 << latency)))) {
332 value = spd_read_byte(ctrl->channel0[cnt],
333 latency_indicies[index]);
335 if(value <= cycle_time[drc&3]) {
336 if( latency > cas_latency) {
337 cas_latency = latency;
343 index = (cas_latency-2);
344 if((index)==0) cas_latency = 20;
345 else if((index)==1) cas_latency = 25;
346 else cas_latency = 30;
348 for(cnt=0;cnt<4;cnt++) {
349 if (!(dimm_mask & (1 << cnt))) {
352 reg = spd_read_byte(ctrl->channel0[cnt], 27)&0x0ff;
353 if(((index>>8)&0x0ff)<reg) {
354 index &= ~(0x0ff << 8);
357 reg = spd_read_byte(ctrl->channel0[cnt], 28)&0x0ff;
358 if(((index>>16)&0x0ff)<reg) {
359 index &= ~(0x0ff << 16);
362 reg = spd_read_byte(ctrl->channel0[cnt], 29)&0x0ff;
363 if(((index2>>0)&0x0ff)<reg) {
364 index2 &= ~(0x0ff << 0);
367 reg = spd_read_byte(ctrl->channel0[cnt], 41)&0x0ff;
368 if(((index2>>8)&0x0ff)<reg) {
369 index2 &= ~(0x0ff << 8);
372 reg = spd_read_byte(ctrl->channel0[cnt], 42)&0x0ff;
373 if(((index2>>16)&0x0ff)<reg) {
374 index2 &= ~(0x0ff << 16);
380 value = cycle_time[drc&3];
381 if(value <= 0x50) { /* 200 MHz */
383 drt |= (2<<2); /* CAS latency 4 */
386 drt |= (1<<2); /* CAS latency 3 */
389 if((index&0x0ff00)<=0x03c00) {
390 drt |= (1<<8); /* Trp RAS Precharg */
392 drt |= (2<<8); /* Trp RAS Precharg */
395 /* Trcd RAS to CAS delay */
396 if((index2&0x0ff)<=0x03c) {
402 /* Tdal Write auto precharge recovery delay */
406 if((index2&0x0ff00)<=0x03700)
408 else if((index2&0xff00)<=0x03c00)
411 drt |= (2<<14); /* spd 41 */
413 drt |= (2<<16); /* Twr not defined for DDR docs say use 2 */
416 if((index&0x0ff0000)<=0x0140000) {
418 } else if((index&0x0ff0000)<=0x0280000) {
420 } else if((index&0x0ff0000)<=0x03c0000) {
426 /* Trfc Auto refresh cycle time */
427 if((index2&0x0ff0000)<=0x04b0000) {
429 } else if((index2&0x0ff0000)<=0x0690000) {
434 /* Docs say use 55 for all 200Mhz */
437 else if(value <= 0x60) { /* 167 Mhz */
438 /* according to new documentation CAS latency is 00
439 * for bits 3:2 for all 167 Mhz
440 drt |= ((index&3)<<2); */ /* set CAS latency */
441 if((index&0x0ff00)<=0x03000) {
442 drt |= (1<<8); /* Trp RAS Precharg */
444 drt |= (2<<8); /* Trp RAS Precharg */
447 /* Trcd RAS to CAS delay */
448 if((index2&0x0ff)<=0x030) {
454 /* Tdal Write auto precharge recovery delay */
458 drt |= (2<<14); /* spd 41, but only one choice */
460 drt |= (2<<16); /* Twr not defined for DDR docs say 2 */
463 if((index&0x0ff0000)<=0x0180000) {
465 } else if((index&0x0ff0000)<=0x0300000) {
471 /* Trfc Auto refresh cycle time */
472 if((index2&0x0ff0000)<=0x0480000) {
474 } else if((index2&0x0ff0000)<=0x0780000) {
479 /* Docs state to use 99 for all 167 Mhz */
482 else if(value <= 0x75) { /* 133 Mhz */
483 drt |= ((index&3)<<2); /* set CAS latency */
484 if((index&0x0ff00)<=0x03c00) {
485 drt |= (1<<8); /* Trp RAS Precharg */
487 drt |= (2<<8); /* Trp RAS Precharg */
490 /* Trcd RAS to CAS delay */
491 if((index2&0x0ff)<=0x03c) {
497 /* Tdal Write auto precharge recovery delay */
501 drt |= (2<<14); /* spd 41, but only one choice */
503 drt |= (1<<16); /* Twr not defined for DDR docs say 1 */
506 if((index&0x0ff0000)<=0x01e0000) {
508 } else if((index&0x0ff0000)<=0x03c0000) {
514 /* Trfc Auto refresh cycle time */
515 if((index2&0x0ff0000)<=0x04b0000) {
517 } else if((index2&0x0ff0000)<=0x0780000) {
523 /* Based on CAS latency */
531 die("Invalid SPD 9 bus speed.\n");
535 pci_write_config32(ctrl->f0, DRT, drt);
540 static int spd_set_dram_controller_mode(const struct mem_controller *ctrl,
548 static const u8 spd_rates[6] = {15,3,7,7,62,62};
549 static const u8 drc_rates[5] = {0,15,7,62,3};
550 static const u8 fsb_conversion[8] = {0,1,3,2,3,0,3,3};
553 drc = pci_read_config32(ctrl->f0, DRC);
554 for(cnt=0; cnt < 4; cnt++) {
555 if (!(dimm_mask & (1 << cnt))) {
558 value = spd_read_byte(ctrl->channel0[cnt], 11); /* ECC */
559 if (value != 2) die("ERROR - Non ECC memory dimm\n");
561 value = spd_read_byte(ctrl->channel0[cnt], 12); /*refresh rate*/
562 value &= 0x0f; /* clip self refresh bit */
563 if (value > 5) goto hw_err;
564 if (rate > spd_rates[value])
565 rate = spd_rates[value];
567 value = spd_read_byte(ctrl->channel0[cnt], 9); /* cycle time */
568 if (value > 0x75) goto hw_err;
570 drc |= (1 << 20); /* enable ECC */
571 for (cnt = 1; cnt < 5; cnt++)
572 if (drc_rates[cnt] == rate)
575 drc &= ~(7 << 8); /* clear the rate bits */
579 drc |= (1 << 26); /* set the overlap bit - the factory BIOS does */
580 drc |= (1 << 27); /* set DED retry enable - the factory BIOS does */
582 drc &= ~(1 << 5); /* enable ODT */
583 drc |= (1 << 4); /* independent clocks */
585 /* set front side bus speed */
586 msr = rdmsr(0xcd); /* returns 0 on Pentium M 90nm */
587 value = msr.lo & 0x07;
589 drc |= (fsb_conversion[value] << 2);
591 /* set dram type to ddr2 */
597 /* If an hw_error occurs report that I have no memory */
604 static void sdram_set_spd_registers(const struct mem_controller *ctrl)
608 /* Test if we can read the spd and if ram is ddr or ddr2 */
609 dimm_mask = spd_detect_dimms(ctrl);
610 if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) {
611 print_err("No memory for this cpu\n");
617 static void do_delay(void)
625 #define TIMEOUT_LOOPS 300000
627 #define DCALCSR 0x100
628 #define DCALADDR 0x104
629 #define DCALDATA 0x108
631 static void set_on_dimm_termination_enable(const struct mem_controller *ctrl)
638 /* Set up northbridge values */
640 pci_write_config32(ctrl->f0, SDRC, 0x30000000);
641 /* Figure out which slots are Empty, Single, or Double sided */
642 for(i=0,t4=0,c2=0;i<8;i+=2) {
643 c1 = pci_read_config8(ctrl->f0, DRB+i);
644 if(c1 == c2) continue;
645 c2 = pci_read_config8(ctrl->f0, DRB+1+i);
653 if( ((t4>>8)&0x0f) == 0 ) {
654 data32 = 0x00000010; /* EEES */
657 if ( ((t4>>16)&0x0f) == 0 ) {
658 data32 = 0x00003132; /* EESS */
661 if ( ((t4>>24)&0x0f) == 0 ) {
662 data32 = 0x00335566; /* ESSS */
665 data32 = 0x77bbddee; /* SSSS */
669 if( ((t4>>8)&0x0f) == 0 ) {
670 data32 = 0x00003132; /* EEED */
673 if ( ((t4>>8)&0x0f) == 2 ) {
674 data32 = 0xb373ecdc; /* EEDD */
677 if ( ((t4>>16)&0x0f) == 0 ) {
678 data32 = 0x00b3a898; /* EESD */
681 data32 = 0x777becdc; /* ESSD */
684 die("Error - First dimm slot empty\n");
687 print_debug("ODT Value = ");
688 print_debug_hex32(data32);
691 pci_write_config32(ctrl->f0, DDR2ODTC, data32);
693 for(dimm=0;dimm<8;dimm+=2) {
695 write32(MCBAR+DCALADDR, 0x0b840001);
696 write32(MCBAR+DCALCSR, 0x81000003 | (dimm << 20));
698 for(i=0;i<1001;i++) {
699 data32 = read32(MCBAR+DCALCSR);
700 if(!(data32 & (1<<31)))
705 static void set_receive_enable(const struct mem_controller *ctrl)
724 for(dimm=0;dimm<8;dimm+=1) {
727 write32(MCBAR+DCALDATA+(17*4), 0x04020000);
728 write32(MCBAR+DCALCSR, 0x81800004 | (dimm << 20));
730 for(i=0;i<1001;i++) {
731 data32 = read32(MCBAR+DCALCSR);
732 if(!(data32 & (1<<31)))
738 dcal_data32_0 = read32(MCBAR+DCALDATA + 0);
739 dcal_data32_1 = read32(MCBAR+DCALDATA + 4);
740 dcal_data32_2 = read32(MCBAR+DCALDATA + 8);
741 dcal_data32_3 = read32(MCBAR+DCALDATA + 12);
744 dcal_data32_0 = read32(MCBAR+DCALDATA + 16);
745 dcal_data32_1 = read32(MCBAR+DCALDATA + 20);
746 dcal_data32_2 = read32(MCBAR+DCALDATA + 24);
747 dcal_data32_3 = read32(MCBAR+DCALDATA + 28);
750 /* check if bank is installed */
751 if((dcal_data32_0 == 0) && (dcal_data32_2 == 0))
753 /* Calculate the timing value */
756 for(i=0,edge=0,bit=63,cnt=31,data32r=0,
757 work32l=dcal_data32_1,work32h=dcal_data32_3;
760 if(work32l & (1<<cnt))
763 work32l = dcal_data32_0;
764 work32h = dcal_data32_2;
770 if(!(work32l & (1<<cnt)))
773 work32l = dcal_data32_0;
774 work32h = dcal_data32_2;
782 data32 = ((bit%8) << 1);
783 if(work32h & (1<<cnt))
808 work32l = dcal_data32_0;
809 work32h = dcal_data32_2;
815 if(!(work32l & (1<<cnt)))
818 if(work32l & (1<<cnt))
821 data32 = (((cnt-1)%8)<<1);
822 if(work32h & (1<<(cnt-1))) {
825 /* test for frame edge cross overs */
826 if((edge == 1) && (data32 > 12) &&
827 (((recen+16)-data32) < 3)) {
831 if((edge == 2) && (data32 < 4) &&
832 ((recen - data32) > 12)) {
836 if(((recen+3) >= data32) && ((recen-3) <= data32))
846 recen+=2; /* this is not in the spec, but matches
847 the factory output, and has less failure */
848 recen <<= (dimm/2) * 8;
857 /* Check for Eratta problem */
858 for(i=cnt=0;i<32;i+=8) {
859 if (((recena>>i)&0x0f)>7) {
863 if((recena>>i)&0x0f) {
869 cnt = (cnt&0x0f) - (cnt>>16);
872 if(((recena>>i)&0x0f)>7) {
873 recena &= ~(0x0f<<i);
880 if(((recena>>i)&0x0f)<8) {
881 recena &= ~(0x0f<<i);
887 for(i=cnt=0;i<32;i+=8) {
888 if (((recenb>>i)&0x0f)>7) {
892 if((recenb>>i)&0x0f) {
898 cnt = (cnt&0x0f) - (cnt>>16);
901 if(((recenb>>i)&0x0f)>7) {
902 recenb &= ~(0x0f<<i);
909 if(((recenb>>8)&0x0f)<8) {
910 recenb &= ~(0x0f<<i);
917 print_debug("Receive enable A = ");
918 print_debug_hex32(recena);
919 print_debug(", Receive enable B = ");
920 print_debug_hex32(recenb);
923 /* clear out the calibration area */
924 write32(MCBAR+DCALDATA+(16*4), 0x00000000);
925 write32(MCBAR+DCALDATA+(17*4), 0x00000000);
926 write32(MCBAR+DCALDATA+(18*4), 0x00000000);
927 write32(MCBAR+DCALDATA+(19*4), 0x00000000);
930 write32(MCBAR+DCALCSR, 0x0000000f);
932 write32(MCBAR+0x150, recena);
933 write32(MCBAR+0x154, recenb);
937 static void sdram_enable(int controllers, const struct mem_controller *ctrl)
949 static const struct {
953 {{ 0x00000010, 0x00000000, 0x00000002, 0x00000001}},
955 {{ 0x00000120, 0x00000000, 0x00000032, 0x00000010}},
957 {{ 0x00154320, 0x00000000, 0x00065432, 0x00010000}},
958 /* FSB 200 DIMM 400 */
959 {{ 0x00000001, 0x00000000, 0x00000001, 0x00000000}},
962 static const u32 dqs_data[] = {
963 0xffffffff, 0xffffffff, 0x000000ff,
964 0xffffffff, 0xffffffff, 0x000000ff,
965 0xffffffff, 0xffffffff, 0x000000ff,
966 0xffffffff, 0xffffffff, 0x000000ff,
967 0xffffffff, 0xffffffff, 0x000000ff,
968 0xffffffff, 0xffffffff, 0x000000ff,
969 0xffffffff, 0xffffffff, 0x000000ff,
970 0xffffffff, 0xffffffff, 0x000000ff};
972 mask = spd_detect_dimms(ctrl);
973 print_debug("Starting SDRAM Enable\n");
976 pci_write_config32(ctrl->f0, DRM,
977 0x00410000 | CONFIG_DIMM_MAP_LOGICAL);
978 /* set dram type and Front Side Bus freq. */
979 drc = spd_set_dram_controller_mode(ctrl, mask);
981 die("Error calculating DRC\n");
983 data32 = drc & ~(3 << 20); /* clear ECC mode */
984 data32 = data32 & ~(7 << 8); /* clear refresh rates */
985 data32 = data32 | (1 << 5); /* temp turn off ODT */
986 /* Set gearing, then dram controller mode */
987 /* drc bits 3:2 = FSB speed */
988 for(iptr = gearing[(drc>>2)&3].clkgr,cnt=0;cnt<4;cnt++) {
989 pci_write_config32(ctrl->f0, 0xa0+(cnt*4), iptr[cnt]);
992 pci_write_config32(ctrl->f0, DRC, data32);
994 /* turn the clocks on */
996 pci_write_config16(ctrl->f0, CKDIS, 0x0000);
998 /* 0x9a DDRCSR Take subsystem out of idle */
999 data16 = pci_read_config16(ctrl->f0, DDRCSR);
1000 data16 &= ~(7 << 12);
1001 data16 |= (1 << 12);
1002 pci_write_config16(ctrl->f0, DDRCSR, data16);
1004 /* program row size DRB */
1005 spd_set_ram_size(ctrl, mask);
1007 /* program page size DRA */
1008 spd_set_row_attributes(ctrl, mask);
1010 /* program DRT timing values */
1011 cas_latency = spd_set_drt_attributes(ctrl, mask, drc);
1013 for(i=0;i<8;i+=2) { /* loop through each dimm to test */
1014 print_debug("DIMM ");
1015 print_debug_hex8(i);
1020 write32(MCBAR+DCALCSR, (0x01000000 | (i<<20)));
1021 write32(MCBAR+DCALCSR, (0x81000000 | (i<<20)));
1023 do data32 = read32(MCBAR+DCALCSR);
1024 while(data32 & 0x80000000);
1030 for(cs=0;cs<8;cs+=2) {
1031 write32(MCBAR + DCALCSR, (0x81000000 | (cs<<20)));
1032 do data32 = read32(MCBAR+DCALCSR);
1033 while(data32 & 0x80000000);
1036 /* Precharg all banks */
1038 for(cs=0;cs<8;cs+=2) {
1039 write32(MCBAR+DCALADDR, 0x04000000);
1040 write32(MCBAR+DCALCSR, (0x81000002 | (cs<<20)));
1041 do data32 = read32(MCBAR+DCALCSR);
1042 while(data32 & 0x80000000);
1045 /* EMRS dll's enabled */
1047 for(cs=0;cs<8;cs+=2) {
1048 /* fixme hard code AL additive latency */
1049 write32(MCBAR+DCALADDR, 0x0b940001);
1050 write32(MCBAR+DCALCSR, (0x81000003 | (cs<<20)));
1051 do data32 = read32(MCBAR+DCALCSR);
1052 while(data32 & 0x80000000);
1054 /* MRS reset dll's */
1056 if(cas_latency == 30)
1057 mode_reg = 0x053a0000;
1059 mode_reg = 0x054a0000;
1060 for(cs=0;cs<8;cs+=2) {
1061 write32(MCBAR+DCALADDR, mode_reg);
1062 write32(MCBAR+DCALCSR, (0x81000003 | (cs<<20)));
1063 do data32 = read32(MCBAR+DCALCSR);
1064 while(data32 & 0x80000000);
1067 /* Precharg all banks */
1071 for(cs=0;cs<8;cs+=2) {
1072 write32(MCBAR+DCALADDR, 0x04000000);
1073 write32(MCBAR+DCALCSR, (0x81000002 | (cs<<20)));
1074 do data32 = read32(MCBAR+DCALCSR);
1075 while(data32 & 0x80000000);
1078 /* Do 2 refreshes */
1080 for(cs=0;cs<8;cs+=2) {
1081 write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20)));
1082 do data32 = read32(MCBAR+DCALCSR);
1083 while(data32 & 0x80000000);
1086 for(cs=0;cs<8;cs+=2) {
1087 write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20)));
1088 do data32 = read32(MCBAR+DCALCSR);
1089 while(data32 & 0x80000000);
1092 /* for good luck do 6 more */
1093 for(cs=0;cs<8;cs+=2) {
1094 write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20)));
1097 for(cs=0;cs<8;cs+=2) {
1098 write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20)));
1101 for(cs=0;cs<8;cs+=2) {
1102 write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20)));
1105 for(cs=0;cs<8;cs+=2) {
1106 write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20)));
1109 for(cs=0;cs<8;cs+=2) {
1110 write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20)));
1113 for(cs=0;cs<8;cs+=2) {
1114 write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20)));
1117 /* MRS reset dll's normal */
1119 for(cs=0;cs<8;cs+=2) {
1120 write32(MCBAR+DCALADDR, (mode_reg & ~(1<<24)));
1121 write32(MCBAR+DCALCSR, (0x81000003 | (cs<<20)));
1122 do data32 = read32(MCBAR+DCALCSR);
1123 while(data32 & 0x80000000);
1126 /* Do only if DDR2 EMRS dll's enabled */
1128 for(cs=0;cs<8;cs+=2) {
1129 write32(MCBAR+DCALADDR, (0x0b940001));
1130 write32(MCBAR+DCALCSR, (0x81000003 | (cs<<20)));
1131 do data32 = read32(MCBAR+DCALCSR);
1132 while(data32 & 0x80000000);
1137 write32(MCBAR+DCALCSR, 0x0000000f);
1139 /* enable on dimm termination */
1140 set_on_dimm_termination_enable(ctrl);
1142 /* receive enable calibration */
1143 set_receive_enable(ctrl);
1146 pci_write_config32(ctrl->f0, 0x94, 0x3904aa00);
1147 for(i = 0, cnt = (MCBAR+0x200); i < 24; i++, cnt+=4) {
1148 write32(cnt, dqs_data[i]);
1150 pci_write_config32(ctrl->f0, 0x94, 0x3900aa00);
1152 /* Enable refresh */
1154 data32 = drc & ~(3 << 20); /* clear ECC mode */
1155 pci_write_config32(ctrl->f0, DRC, data32);
1156 write32(MCBAR+DCALCSR, 0x0008000f);
1158 /* clear memory and init ECC */
1159 print_debug("Clearing memory\n");
1160 for(i=0;i<64;i+=4) {
1161 write32(MCBAR+DCALDATA+i, 0x00000000);
1164 for(cs=0;cs<8;cs+=2) {
1165 write32(MCBAR+DCALCSR, (0x810831d8 | (cs<<20)));
1166 do data32 = read32(MCBAR+DCALCSR);
1167 while(data32 & 0x80000000);
1170 /* Bring memory subsystem on line */
1171 data32 = pci_read_config32(ctrl->f0, 0x98);
1172 data32 |= (1 << 31);
1173 pci_write_config32(ctrl->f0, 0x98, data32);
1174 /* wait for completion */
1175 print_debug("Waiting for mem complete\n");
1177 data32 = pci_read_config32(ctrl->f0, 0x98);
1178 if( (data32 & (1<<31)) == 0)
1181 print_debug("Done\n");
1183 /* Set initialization complete */
1186 data32 = drc & ~(3 << 20); /* clear ECC mode */
1187 pci_write_config32(ctrl->f0, DRC, data32);
1189 /* Set the ecc mode */
1190 pci_write_config32(ctrl->f0, DRC, drc);
1192 /* Enable memory scrubbing */
1194 data16 = pci_read_config16(ctrl->f0, MCHSCRB);
1196 data16 |= ((2 << 2) | (2 << 0));
1197 pci_write_config16(ctrl->f0, MCHSCRB, data16);
1199 /* The memory is now setup, use it */
1200 #if CONFIG_CACHE_AS_RAM == 0
1201 cache_lbmem(MTRR_TYPE_WRBACK);